CN113314519A - ESD protection circuit of chip IO pin - Google Patents

ESD protection circuit of chip IO pin Download PDF

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Publication number
CN113314519A
CN113314519A CN202110648522.2A CN202110648522A CN113314519A CN 113314519 A CN113314519 A CN 113314519A CN 202110648522 A CN202110648522 A CN 202110648522A CN 113314519 A CN113314519 A CN 113314519A
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type mos
static device
port
pin
chip
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戴兴科
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Shenzhen Weiyuan Semiconductor Co ltd
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Shenzhen Weiyuan Semiconductor Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses an ESD protection circuit of an IO pin of a chip, which comprises an internal circuit module of the chip, and the IO pin, a VDD port and a GND port which are connected with the internal circuit module of the chip; a protection diode, a first anti-static device and a second anti-static device are further connected between the VDD port and the GND port; and the common connecting end of the chip internal circuit module and the GND port or the common connecting end of the chip internal circuit module and the VDD port is connected with the IO pin through the first anti-static device and the second anti-static device in sequence. When a GND port or a VDD port generates a noise signal, the circuit only interferes with the second anti-static device through the first anti-static device, so that an IO pin is not interfered, and the problem that the noise signal is generated by the GND port or the VDD port to interfere with the IO pin can be effectively solved.

Description

ESD protection circuit of chip IO pin
Technical Field
The invention relates to the technical field of ESD protection of chips, in particular to an ESD protection circuit of an IO pin of a chip.
Background
As shown in fig. 1, the ESD (electrostatic discharge, electrostatic discharge protection) protection circuit for an IO pin commonly used in a conventional chip is shown, where IO is an IO pin to be protected, Dp is a diode for ESD protection of a VDD port, Dn is a diode for ESD protection of a GND port, and Dpower is a diode for ESD protection between the VDD port and the GND port.
Referring to fig. 2, when a positive voltage ESD is applied to the GND port from the IO pin, the ESD current leaks out the path, and when the ESD voltage is applied to the IO pin, when the IO voltage exceeds the breakdown voltage of the diode Dn, Dn is turned on to conduct the ESD charge to the GND port, so that the ESD charge does not flow to the Internal Circuit, thereby preventing the ESD charge from being damaged, and further achieving the ESD protection effect.
Referring to fig. 3, when a negative voltage ESD is applied to the GND port from the IO pin, the ESD current leaks out the path, and when the ESD voltage is applied to the IO pin, and the IO voltage is lower than the GND port and exceeds the forward bias voltage of Dn, Dn is turned on to conduct the ESD charges to the GND port, thereby achieving the ESD protection function.
Referring to fig. 4, when a positive voltage ESD is applied to the VDD port from the IO pin, the ESD current leaks out the path, and when the ESD voltage is applied to the IO pin, and when the IO voltage exceeds the forward bias voltage of Dp, Dp is turned on, so as to conduct the ESD charges to the VDD port, thereby achieving the ESD protection effect.
Referring to fig. 5, when a negative voltage ESD is applied to the VDD port from the IO pin, the ESD current leaks out the path, and when the IO voltage is applied to the IO pin and the IO voltage exceeds the breakdown voltage of Dp, Dp is turned on to conduct the ESD charges to the VDD port, thereby achieving the ESD protection function.
As can be seen from the above, the conventional ESD protection circuit has a certain protection effect, but if the ESD protection circuit is used in an application with a large ground noise, the ground noise level will interfere with the IO pin signal. As shown in fig. 1, when the ground noise Voltage (VGND) of the GND port is larger and exceeds the Dn forward bias voltage (Vdn) plus the IO Voltage (VIO), Dn will generate forward bias current (input), which will raise VIO and generate noise signal, and when the noise signal is too large, the chip will not work normally. In addition, the power management chip is often used in high current applications, and the high power transistor in the chip is always in an on/off switching state, which is more likely to cause larger ground noise interference, and therefore, it needs to be protected.
Disclosure of Invention
The invention aims to provide an ESD protection circuit of an IO pin of a chip, which aims to solve the problem that the chip cannot work normally due to interference on the IO pin signal of the chip caused by larger grounding noise voltage in the existing ESD protection circuit.
In order to realize the purpose, the following technical scheme is adopted:
an ESD protection circuit of an IO pin of a chip comprises an internal circuit module of the chip, and the IO pin, a VDD port and a GND port which are connected with the internal circuit module of the chip; a protection diode, a first anti-static device and a second anti-static device are further connected between the VDD port and the GND port; and the common connecting end of the chip internal circuit module and the GND port or the common connecting end of the chip internal circuit module and the VDD port is connected with the IO pin through the first anti-static device and the second anti-static device in sequence.
Further, the first anti-static device is connected to a common connection end of the chip internal circuit module and the GND port; the first anti-static device adopts any one of the following devices: a diode and an N-type MOS tube; when the first anti-static device adopts a diode, the second anti-static device also adopts a diode; when the first anti-static device adopts an N-type MOS tube, the second anti-static device adopts an N-type MOS tube or a P-type MOS tube.
Furthermore, the first anti-static device and the second anti-static device both adopt diodes, and the N ends of the two diodes are connected; and the P end of the diode of the first anti-static device is connected with the GND port, and the P end of the diode of the second anti-static device is connected with the IO pin.
Furthermore, the first anti-static device adopts an N-type MOS tube, the second anti-static device adopts a P-type MOS tube, and the drain electrode of the N-type MOS tube is connected with the source electrode of the P-type MOS tube; the grid electrode of the N-type MOS tube of the first anti-static device is connected with the source electrode of the N-type MOS tube and then is connected to the GND port, the grid electrode of the P-type MOS tube of the second anti-static device is connected with the source electrode of the P-type MOS tube of the second anti-static device, and the drain electrode of the P-type MOS tube of the second anti-static device is connected with the IO port.
Furthermore, the first anti-static device and the second anti-static device both adopt N-type MOS tubes, and drain electrodes of the two N-type MOS tubes are connected; the grid electrode of the N-type MOS tube of the first anti-static device is connected with the source electrode thereof and then connected to a GND port, and the grid electrode of the N-type MOS tube of the second anti-static device and the source electrode thereof are both connected to an IO port.
Further, the first anti-static device is connected to a common connection end of the chip internal circuit module and the VDD port; the first anti-static device adopts any one of the following devices: a diode and a P-type MOS tube; when the first anti-static device adopts a diode, the second anti-static device also adopts a diode; when the first anti-static device adopts a P-type MOS tube, the second anti-static device adopts an N-type MOS tube or a P-type MOS tube.
Furthermore, the first anti-static device and the second anti-static device both adopt diodes, and the P ends of the two diodes are connected; the N end of the diode of the first anti-static device is connected with the VDD port, and the N end of the diode of the second anti-static device is connected with the IO pin.
Furthermore, the first anti-static device adopts a P-type MOS tube, the second anti-static device adopts an N-type MOS tube, and the drain electrode of the P-type MOS tube is connected with the source electrode of the N-type MOS tube; the grid electrode of the P-type MOS tube of the first anti-static device is connected with the source electrode of the P-type MOS tube and then connected to a VDD port, the grid electrode of the N-type MOS tube of the second anti-static device is connected with the source electrode of the N-type MOS tube of the second anti-static device, and the drain electrode of the N-type MOS tube of the second anti-static device is connected with an IO port.
Furthermore, the first anti-static device and the second anti-static device both adopt P-type MOS tubes, and drain electrodes of the two P-type MOS tubes are connected; the grid electrode of the P-type MOS tube of the first anti-static device is connected with the source electrode thereof and then connected to a VDD port, and the grid electrode of the P-type MOS tube of the second anti-static device and the source electrode thereof are both connected to an IO port.
Further, when the first and second anti-static devices both adopt MOS transistors, the gate of at least one of the MOS transistors is further connected in series with a resistor.
By adopting the scheme, the invention has the beneficial effects that:
at the public link of chip inner circuit module and GND port, or the public link of chip inner circuit module and VDD port, be connected with the IO pin through first antistatic device and second antistatic device in proper order, when GND port or VDD port produced the noise signal, only can see through first antistatic device and disturb the second antistatic device, and then can not disturb the IO pin, and then can effectual solution because of GND port or VDD port produce the problem of noise signal in order to disturb the IO pin, and simultaneously, multiple specific implementation circuit has been provided, can supply the user according to the user demand, choose for use by oneself, the commonality is strong.
Drawings
FIG. 1 is a diagram of a conventional ESD protection circuit in the prior art;
FIG. 2 is a diagram of an ESD current venting path when an IO pin applies positive voltage ESD to a GND port in the prior art;
FIG. 3 is a diagram of an ESD current discharge path when an IO pin applies a negative ESD voltage to a GND port in the prior art;
FIG. 4 is a diagram of an ESD current venting path when an IO pin applies positive ESD to a VDD port in the prior art;
FIG. 5 is a diagram of an ESD current venting path when an IO pin applies a negative ESD voltage to a VDD port in the prior art;
FIG. 6 is a circuit diagram of embodiment 1 of the present invention;
FIG. 7 is a circuit diagram of practical application of embodiment 1 of the present invention;
FIG. 8 is a circuit diagram of embodiment 2 of the present invention;
FIG. 9 is a circuit diagram of embodiment 3 of the present invention;
FIG. 10 is a circuit diagram according to embodiment 4 of the present invention;
FIG. 11 is a circuit diagram of embodiment 5 of the present invention;
FIG. 12 is a circuit diagram of practical application of embodiment 5 of the present invention;
FIG. 13 is a circuit diagram of embodiment 8 of the present invention;
wherein the figures identify the description:
1-a first anti-static device; 2-second antistatic means.
Detailed Description
The invention is described in detail below with reference to the figures and the specific embodiments.
Referring to fig. 6 to 13, the present invention provides an ESD protection circuit for an IO pin of a chip, including a chip internal circuit module, and an IO pin, a VDD port, and a GND port connected to the chip internal circuit module; a protection diode is connected between the VDD port and the GND port, and the device further comprises a first anti-static device 1 and a second anti-static device 2; and the common connecting end of the chip internal circuit module and the GND port or the common connecting end of the chip internal circuit module and the VDD port is connected with the IO pin through the first antistatic device 1 and the second antistatic device 2 in sequence.
Through the common connection end between the chip internal circuit module and the GND port, or the common connection end between the chip internal circuit module and the VDD port, the chip internal circuit module and the first and second anti-static devices 1 and 2 are connected with the IO pin in sequence, when the GND port or the VDD port generates a noise signal, the chip internal circuit module only can interfere the second anti-static device 2 through the first anti-static device 1, and then the IO pin can not be interfered, and then the problem that the noise signal is generated by the GND port or the VDD port to interfere the IO pin can be effectively solved
Aiming at a noise signal generated by a GND port, the first anti-static device 1 is connected to a common connecting end of a chip internal circuit module and the GND port; the first antistatic device 1 adopts any one of the following devices: a diode and an N-type MOS tube; when the first antistatic device 1 adopts a diode, the second antistatic device 2 also adopts a diode; when the first antistatic device 1 adopts an N-type MOS transistor, the second antistatic device 2 adopts an N-type MOS transistor or a P-type MOS transistor.
Example 1: as shown in fig. 6 and 7, the first and second anti-static devices 1 and 2 both employ diodes, and N ends of the two diodes are connected; the P end of the diode of the first anti-static device 1 is connected with the GND port, and the P end of the diode of the second anti-static device 2 is connected with the IO pin. In this embodiment, the diode of the first anti-static device 1 is Dn, and the diode of the second anti-static device 2 is Dp, and at this time, if the GND port generates the ground noise signal, only the NODE is interfered by Dn, thereby avoiding the interference to the IO pin.
Example 2: as shown in fig. 8, two diodes in embodiment 1 are replaced by an N-type MOS transistor and a P-type MOS transistor, that is, the first anti-static device 1 is an N-type MOS transistor, the second anti-static device 2 is a P-type MOS transistor, and the drain of the N-type MOS transistor is connected to the source of the P-type MOS transistor; the gate of the N-type MOS transistor of the first anti-static device 1 is connected to the source thereof and then connected to the GND port, the gate of the P-type MOS transistor of the second anti-static device 2 is connected to the source thereof, and the drain of the P-type MOS transistor of the second anti-static device 2 is connected to the IO port.
Example 3: as shown in fig. 9, the two diodes in embodiment 1 are replaced by two N-type MOS transistors, that is, the first anti-static device 1 and the second anti-static device 2 both use N-type MOS transistors, and the drains of the two N-type MOS transistors are connected; the gate and the source of the N-type MOS transistor of the first anti-static device 1 are connected and then connected to the GND port, and the gate and the source of the N-type MOS transistor of the second anti-static device 2 are both connected to the IO port.
Example 4: on the basis of the embodiments 2 and 3, the gate of at least one MOS transistor is further connected in series with a resistor, as shown in fig. 10 (a) in embodiment 2, the gates of the P-type MOS transistor and the N-type MOS transistor are respectively connected in series with a resistor, or the gate of the P-type MOS transistor is connected in series with a resistor, and the gate of the N-type MOS transistor is not connected in series with a resistor, or the gate of the N-type MOS transistor is connected in series with a resistor, and the gate of the P-type MOS transistor is not connected in series with a resistor; as shown in embodiment 3 with reference to part (b) of fig. 10, the gates of two N-type MOS transistors are connected in series with a resistor, or only the gate of one of the N-type MOS transistors may be connected in series with a resistor.
Aiming at a noise signal generated by a VDD port, the first anti-static device 1 is connected to a common connecting end of a chip internal circuit module and the VDD port; the first antistatic device 1 adopts any one of the following devices: a diode and a P-type MOS tube; when the first antistatic device 1 adopts a diode, the second antistatic device 2 also adopts a diode; when the first anti-static device 1 adopts a P-type MOS transistor, the second anti-static device 2 adopts an N-type MOS transistor or a P-type MOS transistor.
Example 5: as shown in fig. 11 to 12, the first and second anti-static devices 1 and 2 both employ diodes, and P ends of the two diodes are connected; the N end of the diode of the first anti-static device 1 is connected with a VDD port, and the N end of the diode of the second anti-static device 2 is connected with an IO pin. In this embodiment, the diode of the first anti-static device 1 is Dp, and the diode of the second anti-static device 2 is Dn, and at this time, if the VDD port generates the power connection noise signal, only Dn will be interfered by Dp, thereby avoiding the interference to the IO pin.
Example 6: correspondingly replacing the two diodes in the embodiment 5 with an N-type MOS transistor and a P-type MOS transistor, that is, the first anti-static device 1 adopts the P-type MOS transistor, the second anti-static device 2 adopts the N-type MOS transistor, and the drain electrode of the P-type MOS transistor is connected with the source electrode of the N-type MOS transistor; the gate of the P-type MOS transistor of the first anti-static device 1 is connected to the source thereof and then connected to the VDD port, the gate of the N-type MOS transistor of the second anti-static device 2 is connected to the source thereof, and the drain of the N-type MOS transistor of the second anti-static device 2 is connected to the IO port.
Example 7: correspondingly replacing the two diodes in the embodiment 5 with two P-type MOS transistors, that is, the first anti-static device 1 and the second anti-static device 2 both adopt P-type MOS transistors, and the drains of the two P-type MOS transistors are connected; the gate and the source of the P-type MOS transistor of the first anti-static device 1 are connected and then connected to the VDD port, and the gate and the source of the P-type MOS transistor of the second anti-static device 2 are both connected to the IO port.
Example 8: on the basis of the embodiments 6 and 7, the gate of at least one MOS transistor is further connected in series with a resistor, as shown in fig. 13 (c) in embodiment 6, the gates of the P-type MOS transistor and the N-type MOS transistor are respectively connected in series with a resistor, or the gate of the P-type MOS transistor is connected in series with a resistor, and the gate of the N-type MOS transistor is not connected in series with a resistor, or the gate of the N-type MOS transistor is connected in series with a resistor, and the gate of the P-type MOS transistor is not connected in series with a resistor; as shown in embodiment 7 with reference to part (d) of fig. 13, the gates of both P-type MOS transistors are connected in series with a resistor, or only the gate of one P-type MOS transistor may be connected in series with a resistor.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. An ESD protection circuit of an IO pin of a chip comprises an internal circuit module of the chip, and the IO pin, a VDD port and a GND port which are connected with the internal circuit module of the chip; a protection diode is connected between the VDD port and the GND port, and the device is characterized by further comprising a first anti-static device and a second anti-static device; and the common connecting end of the chip internal circuit module and the GND port or the common connecting end of the chip internal circuit module and the VDD port is connected with the IO pin through the first anti-static device and the second anti-static device in sequence.
2. The ESD protection circuit of the IO pin of the chip according to claim 1, wherein the first anti-static device is connected to a common connection end of the internal circuit module of the chip and the GND port; the first anti-static device adopts any one of the following devices: a diode and an N-type MOS tube; when the first anti-static device adopts a diode, the second anti-static device also adopts a diode; when the first anti-static device adopts an N-type MOS tube, the second anti-static device adopts an N-type MOS tube or a P-type MOS tube.
3. The ESD protection circuit of the IO pin of the chip according to claim 2, wherein the first and the second anti-static devices are diodes, and N ends of the two diodes are connected; and the P end of the diode of the first anti-static device is connected with the GND port, and the P end of the diode of the second anti-static device is connected with the IO pin.
4. The ESD protection circuit of the IO pin of the chip of claim 2, wherein the first anti-static device is an N-type MOS transistor, the second anti-static device is a P-type MOS transistor, and a drain of the N-type MOS transistor is connected to a source of the P-type MOS transistor; the grid electrode of the N-type MOS tube of the first anti-static device is connected with the source electrode of the N-type MOS tube and then is connected to the GND port, the grid electrode of the P-type MOS tube of the second anti-static device is connected with the source electrode of the P-type MOS tube of the second anti-static device, and the drain electrode of the P-type MOS tube of the second anti-static device is connected with the IO port.
5. The ESD protection circuit of the IO pin of the chip according to claim 2, wherein the first and the second anti-static devices are both N-type MOS transistors, and drains of the two N-type MOS transistors are connected; the grid electrode of the N-type MOS tube of the first anti-static device is connected with the source electrode thereof and then connected to a GND port, and the grid electrode of the N-type MOS tube of the second anti-static device and the source electrode thereof are both connected to an IO port.
6. The ESD protection circuit of the IO pin of the chip according to claim 1, wherein the first anti-static device is connected to a common connection end of the internal circuit module of the chip and the VDD port; the first anti-static device adopts any one of the following devices: a diode and a P-type MOS tube; when the first anti-static device adopts a diode, the second anti-static device also adopts a diode; when the first anti-static device adopts a P-type MOS tube, the second anti-static device adopts an N-type MOS tube or a P-type MOS tube.
7. The ESD protection circuit of the IO pin of the chip of claim 6, wherein the first and the second anti-static devices are diodes, and P ends of the two diodes are connected; the N end of the diode of the first anti-static device is connected with the VDD port, and the N end of the diode of the second anti-static device is connected with the IO pin.
8. The ESD protection circuit of the IO pin of the chip of claim 6, wherein the first anti-static device is a P-type MOS transistor, the second anti-static device is an N-type MOS transistor, and a drain of the P-type MOS transistor is connected to a source of the N-type MOS transistor; the grid electrode of the P-type MOS tube of the first anti-static device is connected with the source electrode of the P-type MOS tube and then connected to a VDD port, the grid electrode of the N-type MOS tube of the second anti-static device is connected with the source electrode of the N-type MOS tube of the second anti-static device, and the drain electrode of the N-type MOS tube of the second anti-static device is connected with an IO port.
9. The ESD protection circuit of the IO pin of the chip of claim 6, wherein the first and the second anti-static devices are P-type MOS transistors, and drains of the two P-type MOS transistors are connected; the grid electrode of the P-type MOS tube of the first anti-static device is connected with the source electrode thereof and then connected to a VDD port, and the grid electrode of the P-type MOS tube of the second anti-static device and the source electrode thereof are both connected to an IO port.
10. The ESD protection circuit for the IO pin of the chip according to claim 2 or 6, wherein when the first and the second anti-static devices are MOS transistors, the gate of at least one of the MOS transistors is further connected in series with a resistor.
CN202110648522.2A 2021-06-10 2021-06-10 ESD protection circuit of chip IO pin Pending CN113314519A (en)

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CN110400799A (en) * 2019-07-26 2019-11-01 珠海格力电器股份有限公司 A kind of electrostatic discharge protective circuit, conductor integrated circuit device and electronic equipment

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Application publication date: 20210827