CN113314454A - Interconnect structure and method of forming the same - Google Patents

Interconnect structure and method of forming the same Download PDF

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Publication number
CN113314454A
CN113314454A CN202010120829.0A CN202010120829A CN113314454A CN 113314454 A CN113314454 A CN 113314454A CN 202010120829 A CN202010120829 A CN 202010120829A CN 113314454 A CN113314454 A CN 113314454A
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Prior art keywords
layer
opening
barrier layer
metal
forming
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CN202010120829.0A
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Chinese (zh)
Inventor
于海龙
谭晶晶
荆学珍
雒建明
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202010120829.0A priority Critical patent/CN113314454A/en
Publication of CN113314454A publication Critical patent/CN113314454A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry

Abstract

The application discloses an interconnection structure and a forming method thereof, wherein the method comprises the following steps: providing a substrate, wherein the substrate comprises an active region; forming a dielectric layer on the substrate, wherein the dielectric layer is provided with an opening penetrating through the dielectric layer, and the opening exposes the surface of the active region; forming a first metal layer at the bottom of the opening; after a first metal layer is formed, passivating the top area in the first metal layer to form a first barrier layer; after the first barrier layer, carrying out annealing treatment to enable the first metal layer left at the bottom of the opening to react with the material on the surface of the active region to form a metal silicide layer; after the metal silicide layer is formed, forming a second barrier layer on the surface of the first barrier layer and on the side wall of the opening; and forming a second metal layer in the opening to fill the opening after forming the second barrier. The interconnect structure and the method of forming the same disclosed herein improve the performance of the interconnect structure.

Description

Interconnect structure and method of forming the same
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to an interconnect structure and a method for forming the same.
Background
With the development of semiconductor technology, the integration level of very large scale integrated circuit chips has reached the scale of billions or even billions of devices, and metal interconnection technology is widely used. For nodes of 10nm and below, reducing the contact resistance (Rc) of the interconnect structure is becoming increasingly important for improving device performance.
In the case of using tungsten (W) as the material of the conductive connection layer and titanium nitride (TiN) as the material of the diffusion suppression layer, the contact resistance of the entire interconnect structure should be the sum of the resistance of tungsten and the resistance of titanium nitride. It is well known that the larger the volume of the conductive connection layer, the lower its resistance. In order to enable the conductive connection layer to have a larger volume, it is generally considered to reduce the thickness of the titanium nitride layer in order to make more room for the conductive connection layer without changing the overall size of the device. However, if the thickness of the titanium nitride layer is excessively sacrificed, the remaining titanium nitride layer may not have achieved the effect of diffusion inhibition after titanium ions are combined with fluorine ions generated during the deposition of the conductive connection layer to become titanium fluoride gas.
Therefore, there is also a need for an improved interconnect structure formation method.
Disclosure of Invention
In view of the above-described shortcomings of the prior art, it is an object of the present application to provide an interconnect structure and a method of forming the same that improves the performance of the interconnect structure.
One aspect of the present application provides a method of forming an interconnect structure, including: providing a substrate, wherein the substrate comprises an active region; forming a dielectric layer on the substrate, wherein the dielectric layer is provided with an opening penetrating through the dielectric layer, and the opening exposes the surface of the active region; forming a first metal layer at the bottom of the opening; after the first metal layer is formed, passivating the top area in the first metal layer to form a first barrier layer; after the first barrier layer is formed, annealing treatment is carried out, so that the first metal layer left at the bottom of the opening reacts with the material on the surface of the active region to form a metal silicide layer; after the metal silicide layer is formed, forming a second barrier layer on the surface of the first barrier layer and on the side wall of the opening; and forming a second metal layer in the opening to fill the opening after forming the second barrier.
Optionally, the material of the first metal layer includes titanium, and the material of the first barrier layer and the material of the second barrier layer each include titanium nitride.
Optionally, before the passivation process, the thickness of the first metal layer is 100 to 160 angstroms.
Optionally, the first barrier layer has a thickness of 20 to 25 angstroms.
Optionally, the second barrier layer has a thickness of 10 to 40 angstroms.
Optionally, the passivation process comprises a nitrogen plasma process.
Optionally, the annealing treatment comprises a dynamic surface annealing treatment.
Optionally, a process of forming the first metal layer is a physical vapor deposition process.
Optionally, the process of forming the second barrier layer comprises an atomic layer deposition process.
The present application also provides an interconnect structure comprising: a substrate comprising an active region; a dielectric layer located on the substrate and having an opening through the dielectric layer, the opening being located on the active region; the metal silicide layer is positioned on the surface of the active region at the bottom of the opening; the first barrier layer is positioned on the surface of the metal silicide layer; the second barrier layer is positioned on the surface of the first barrier layer and the side wall of the opening, and the second barrier layer on the side wall of the opening is in contact with the dielectric layer; and the second metal layer is positioned on the surface of the second barrier layer and fills the opening.
Optionally, the metal silicide layer has a thickness of 75 to 140 angstroms.
Optionally, the first barrier layer has a thickness of 20 to 25 angstroms.
Optionally, the second barrier layer has a thickness of 10 to 40 angstroms.
Optionally, the material of the metal silicide layer includes titanium silicide, and the material of the first barrier layer and the second barrier layer includes titanium nitride.
The technical scheme of this application has following beneficial effect:
according to the technical scheme, the top area of the first metal layer is formed with the first barrier layer by passivating the surface of the first metal layer, and the first barrier layer is prevented from being formed on the side wall of the opening. And forming a second barrier layer on the side wall and the bottom of the opening. The total thickness of the first barrier layer and the second barrier layer at the bottom of the opening is larger than that of the second barrier layer at the side wall of the opening. Therefore, the superposed blocking effect of the first blocking layer and the second blocking layer at the bottom of the opening is better, so that in the process of forming the second metal layer, source gases for forming the second metal layer are prevented from passing through the first blocking layer and the second blocking layer to reach the metal silicide layer, and the metal silicide layer is prevented from being corroded. Secondly, because the thickness of the second barrier layer on the side wall of the opening is smaller, more space is made for forming the second metal layer (namely, the conductive connecting layer), so that the second metal layer can have smaller contact resistance and has better filling performance.
Because the attack of fluorine ion to the metal nitride layer mainly takes place in the opening bottom, consequently, the technical scheme of this application is guaranteeing to reduce the thickness of the metal nitride layer that is located the opening lateral wall as far as under the prerequisite that the metal nitride layer of opening bottom has sufficient thickness to make electrically conductive connecting layer can have bigger volume, thereby reduce contact resistance, improved interconnect's performance.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present disclosure, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:
FIGS. 1A to 1H are schematic structural diagrams illustrating a process of forming an interconnect structure;
FIG. 2 is a flow chart of a method of forming an interconnect structure according to an embodiment of the present application;
fig. 3A to 3H are schematic structural diagrams illustrating a process of forming an interconnect structure according to an embodiment of the present application.
Detailed Description
The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various local modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. Thus, the present disclosure is not to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical solution of the present application will be described in detail below with reference to the embodiments and the accompanying drawings.
As shown in fig. 1A to 1H, a method of forming an interconnect structure includes: providing a substrate 1, the substrate 1 comprising an active region 2; forming a dielectric layer 3 on a substrate 1, wherein the dielectric layer 3 is provided with an opening 4, and the opening 4 exposes the active region 2; forming a first metal layer 5 (e.g., titanium) on the bottom of the opening 4 and the surface of the dielectric layer 2; forming a first metal nitride layer 6 (e.g., titanium nitride) on the surface of the first metal layer 5 and the sidewalls of the opening 4; annealing treatment is carried out, so that the first metal layer 5 positioned at the bottom of the opening 4 reacts with the material on the surface of the active region 2 to form a metal silicide layer 7; forming a second metal nitride layer 8 (e.g., titanium nitride) on the surface of the first titanium nitride layer 6; forming a second metal layer 9 (e.g., tungsten) on the surface of the second titanium nitride layer 8 to fill the opening 4; a planarization process is performed to remove the excess first metal layer 5, first metal nitride layer 6, second metal nitride layer 8, and second metal layer 9.
When filling the opening with tungsten metal by chemical vapor deposition, fluorine may be usedTungsten carbide (WF)6) As source gas, it is mixed with hydrogen (H) gas under heat-assisted conditions2) Reduction reaction is carried out to generate a tungsten metal layer and Hydrogen Fluoride (HF). Both tungsten fluoride and hydrogen fluoride are highly corrosive and can etch the metal nitride layer to some extent and can damage the underlying metal silicide layer.
In the above method, the thicknesses of the metal nitride layers on the bottom and the sidewall of the opening 4 are substantially the same, and the corrosion of the tungsten fluoride and the hydrogen fluoride to the metal nitride layer at the bottom of the opening 4 is much greater than the corrosion to the metal nitride layer at the side of the opening 4, so that the thickness of the metal nitride layer at the sidewall of the opening 4 is wasted to a certain extent compared with the actual requirement, which limits the volume expansion of the second metal layer 9, is not favorable for reducing the contact resistance, and further affects the performance of the whole interconnect structure.
In order to solve the above problem, an embodiment of the present application provides an interconnect structure forming method, as shown in fig. 2, including the following steps:
step S11: providing a substrate, wherein the substrate comprises an active region;
step S12: forming a dielectric layer on the substrate, wherein the dielectric layer is provided with an opening penetrating through the dielectric layer, and the opening exposes the surface of the active region;
step S13: forming a first metal layer at the bottom of the opening;
step S14: after the first metal layer is formed, passivating the top area in the first metal layer to form a first barrier layer;
step S15: after the first barrier layer is formed, annealing treatment is carried out, so that the first metal layer left at the bottom of the opening reacts with the material on the surface of the active region to form a metal silicide layer;
step S16: after the metal silicide layer is formed, forming a second barrier layer on the surface of the first barrier layer and on the side wall of the opening;
step S17: after forming the second barrier, forming a second metal layer in the opening to fill the opening.
The above steps are described in detail with reference to fig. 3A to 3H. It should be noted that methods that perform the above and below steps in other orders also fall within the scope of the present disclosure.
As shown in fig. 3A, a substrate 100 is provided, the substrate 100 including an active region 200.
The material of the substrate 100 may be silicon (Si), germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or other materials, such as a III-V compound such as gallium arsenide. The material of the substrate 100 may be one of monocrystalline silicon, polycrystalline silicon, and amorphous silicon. The substrate 100 may also be a silicon-on-insulator structure or a silicon-on-epitaxial layer structure. In the substrate 100, a semiconductor device (not shown), such as a metal oxide semiconductor device having a gate, a source, and a drain, may be formed.
The material of the active region 200 may be silicide such as silicon phosphorus (SiP), silicon germanium (SiGe), etc. The active region 200 may be formed in the trench of the substrate 100 by ion implantation, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or the like. The trenches may be formed by various suitable etching processes.
As shown in fig. 3B, a dielectric layer 300 is formed on the substrate 100, the dielectric layer 300 having an opening 400 through the dielectric layer 300, the opening 400 exposing the surface of the active region 200.
The material of the dielectric layer 300 may be silicon oxide, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, or the like. In the present embodiment, the dielectric layer 300 may be silicon oxide (SiO)2). The dielectric layer 300 may be formed by physical vapor deposition, chemical vapor deposition, or the like.
The opening 400 may be formed by spin-coating a photoresist on the surface of the dielectric layer 300, forming an opening pattern in the photoresist after exposure and development processes, then etching to form the opening 400, introducing oxygen plasma after etching, and ashing to remove the remaining photoresist.
As shown in fig. 3C, a first metal layer 500 is formed at the bottom of the opening 400.
In the present embodiment, the first metal layer 500 is formed on both the bottom of the opening 400 and the surface of the dielectric layer 300.
In the present embodiment, the material of the first metal layer 500 may be titanium (Ti). The thickness of the first metal layer 500 may be 100 to 160 angstroms, preferably, 140 to 150 angstroms. The first metal layer 500 may be formed by a physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like process. In the present embodiment, the first metal layer 500 is formed by a physical vapor deposition process. In the present embodiment, the first metal layer 500 is not deposited or hardly formed on the sidewall of the opening 400. In some embodiments, the first metal layer 500 formed on the sidewall of the opening 400 is only 1% to 10% of the first metal layer 500 formed on the bottom of the opening 400 and the surface of the dielectric layer 300.
As shown in fig. 3D, after the first metal layer 500 is formed, a passivation process is performed on a top region in the first metal layer 500 to form a first barrier layer 600.
In the present embodiment, after the first metal layer 500 is formed, the surface of the first metal layer is treated by plasma containing nitrogen, so that a portion of the first metal layer 500 forms the first barrier layer 600. In this embodiment, the material of the first barrier layer 600 is titanium nitride (TiN). Glow discharge may be used to render the nitrogen inert in nature to the plasma environment, thereby promoting reaction with the titanium and changing a portion of the first metal layer 500 from titanium to titanium nitride. For example, the power of the glow discharge may be 3000 watts to 5000 watts, and the flow rate of the plasma may be 1000sccm to 3000 sccm. In the present embodiment, the first barrier layer 600 has a thickness of 20 to 25 angstroms.
Compared with the technical scheme of directly depositing the first metal layer in the opening, the first barrier layer formed by changing a part of the first metal layer through the nitrogen-containing plasma treatment only exists at the bottom of the opening and at the top of the dielectric layer, so that the first barrier layer is prevented from being formed on the side wall of the opening. In this way, because the thickness of the second barrier layer on the sidewall of the opening is smaller, more space is made for the subsequent formation of the second metal layer (i.e., the conductive connection layer), so that the second metal layer can have smaller contact resistance and has better filling performance.
As shown in fig. 3E, after the first barrier layer 600 is formed, an annealing process is performed to react the first metal layer 500 remaining at the bottom of the opening 400 with the material on the surface of the active region 200 to form a metal silicide layer 700.
In the present embodiment, the material of the metal silicide layer 700 is titanium silicide (TiSi). In this embodiment, the Annealing process may be a Dynamic Surface Annealing (DSA) process, DSA is capable of changing material properties at an atomic level, and Annealing a locally limited region may be completed in a short time. The annealing treatment may also be Rapid Thermal Processing (RTP), which can complete the steps of the annealing treatment in a shorter time. The thickness of the metal silicide layer 700 may be 75 to 140 angstroms.
As shown in fig. 3F, after the metal silicide layer 700 is formed, a second barrier layer 800 is formed on the surface of the first barrier layer 600 and on the sidewall of the opening 400.
In the present embodiment, after the metal silicide layer 700 is formed, the second barrier layer 800 is formed on the surface and the sidewall of the first barrier layer 600, the sidewall of the first metal layer 500 above the dielectric layer 300, and the sidewall of the opening 400.
In this embodiment, the material of the second barrier layer 800 is titanium nitride. The second barrier layer 800 may be formed by a physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like process. In the present embodiment, the second barrier layer 800 is formed by an atomic layer deposition process. The second barrier layer 800 has a thickness of 10 to 40 angstroms, for example, 15 angstroms.
As shown in fig. 3G, after forming the second barrier layer 800, a second metal layer 900 is formed in the opening 400 to fill the opening 400.
In the present embodiment, after the second barrier layer 800 is formed, a second metal layer 900 filling the opening 400 is formed on the surface of the second barrier layer 800.
In this embodiment, the material of the second metal layer 900 is tungsten (W). The second metal layer 900 may be formed by a physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like process.
When the opening 400 is filled with tungsten metal (e.g., using a chemical vapor deposition process), tungsten fluoride may be used as a source gas, and the tungsten fluoride may be subjected to a reduction reaction with hydrogen gas under a heat-assisted condition to form the second metal layer 900 and hydrogen fluoride. Both tungsten fluoride and hydrogen fluoride are highly corrosive and can corrode the first barrier layer 600 and the second barrier layer 800 and can cause damage to the metal silicide layer 700 thereunder.
In the present application, by avoiding the formation of the first barrier layer 600 on the sidewalls of the opening 400, the total thickness of the first barrier layer 600 and the second barrier layer 800 at the bottom of the opening 400 is greater than the thickness of the second barrier layer 800 on the sidewalls of the opening 400. In this way, the stacked barrier effect of the first barrier layer 600 and the second barrier layer 800 at the bottom of the opening 400 is better, so that during the process of forming the second metal layer 900, the source gas for forming the second metal layer 800 is prevented from etching through the first barrier layer 600 and the second barrier layer 800 to the metal silicide layer 700, thereby corroding the metal silicide layer 700.
In addition, tungsten fluoride and hydrogen fluoride corrode the barrier layer at the bottom of the opening 400 much more than the barrier layer at the side of the opening 400, so that reducing the total thickness of the barrier layer at the sidewall of the opening 400 does not affect the performance of the entire interconnect structure. This, however, also enables the second metal layer to have a larger volume, thereby reducing the contact resistance.
As shown in fig. 3H, after forming the second metal layer 900, a planarization process is performed to remove the first metal layer 500, the first barrier layer 600, the second barrier layer 800, and the second metal layer 900 over the dielectric layer 300 and to make the top surface of the second metal layer 900 flush with the top surface of the dielectric layer 300.
In this embodiment, the planarization process is Chemical-Mechanical Polishing (CMP).
Accordingly, the present application also provides an interconnect structure comprising: a substrate 100, the substrate 100 comprising an active region 200; a dielectric layer 300 on the substrate 100 and having an opening 400 penetrating the dielectric layer 300, the opening 400 being on the active region 200; a metal silicide layer 700 on the surface of the active region at the bottom of the opening 400; a first barrier layer 500 on the surface of the metal silicide layer 700; the second barrier layer 800 is positioned on the surface of the first barrier layer 600 and the side wall of the opening 400, and the second barrier layer 800 on the side wall of the opening 400 is in contact with the dielectric layer 300; and a second metal layer 900 located on the surface of the second barrier layer 800 and filling the opening 400.
The material of the substrate 100 may be silicon, germanium, silicon carbide, silicon-on-insulator, germanium-on-insulator, or other materials, such as a III-V compound such as gallium arsenide.
The material of the active region 200 may be silicide such as silicon phosphorus, silicon germanium, etc. The active region 200 may be formed in a trench of the substrate 100 by ion implantation, physical vapor deposition, chemical vapor deposition, or the like.
The material of the dielectric layer 300 may be silicon oxide, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, or the like. In the present embodiment, the dielectric layer 300 may be silicon oxide. The dielectric layer 300 may be formed by physical vapor deposition, chemical vapor deposition, or the like.
The opening 400 may be formed by spin-coating a photoresist on the surface of the dielectric layer 300, forming an opening pattern in the photoresist after exposure and development processes, then etching to form the opening 400, introducing oxygen plasma after etching, and ashing to remove the remaining photoresist.
The material of the first barrier layer 600 may include titanium nitride. In this example, glow discharge was used to render the nitrogen gas inert to the plasma environment, thereby promoting its reaction with the titanium and changing the pre-formed metal layer from titanium to titanium nitride. In the present embodiment, the first barrier layer 600 has a thickness of 20 to 25 angstroms.
The material of the metal silicide layer 700 may include titanium silicide. In the present embodiment, the metal silicide layer 700 is formed by performing a dynamic surface annealing process on a previously formed metal layer. In the present embodiment, the thickness of the metal silicide layer 700 may be 75 to 140 angstroms.
The material of the second barrier layer 800 may include titanium nitride. In the present embodiment, the second barrier layer 800 is formed by an atomic layer deposition process. In the present embodiment, the second barrier layer 800 has a thickness of 10 to 40 angstroms, for example, 15 angstroms.
The material of the second metal layer 900 may include tungsten. The second metal layer 900 may be formed by a physical vapor deposition, chemical vapor deposition, atomic layer deposition, or the like process.
In conclusion, upon reading the present detailed disclosure, those skilled in the art will appreciate that the foregoing detailed disclosure can be presented by way of example only, and not limitation. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, improvements, and modifications are intended to be suggested by this disclosure, and are within the spirit and scope of the exemplary embodiments of this disclosure.

Claims (14)

1. A method for forming an interconnect structure, comprising:
providing a substrate, wherein the substrate comprises an active region;
forming a dielectric layer on the substrate, wherein the dielectric layer is provided with an opening penetrating through the dielectric layer, and the opening exposes the surface of the active region;
forming a first metal layer at the bottom of the opening;
after the first metal layer is formed, passivating the top area in the first metal layer to form a first barrier layer;
after the first barrier layer is formed, annealing treatment is carried out, so that the first metal layer left at the bottom of the opening reacts with the material on the surface of the active region to form a metal silicide layer;
after the metal silicide layer is formed, forming a second barrier layer on the surface of the first barrier layer and on the side wall of the opening; and
after forming the second barrier, forming a second metal layer in the opening to fill the opening.
2. The method of claim 1, wherein the material of the first metal layer comprises titanium, and the material of the first barrier layer and the material of the second barrier layer each comprise titanium nitride.
3. The method of claim 1, wherein the first metal layer has a thickness of 100 to 160 angstroms prior to the passivating.
4. The method of claim 1, wherein the first barrier layer has a thickness of 20 to 25 angstroms.
5. The method of claim 1, wherein the second barrier layer has a thickness of 10 to 40 angstroms.
6. The method of claim 1, wherein the passivation process comprises a nitrogen plasma process.
7. The method of claim 1, wherein the annealing comprises a dynamic surface annealing.
8. The method of claim 1, wherein the process of forming the first metal layer is a physical vapor deposition process.
9. The method of claim 1, wherein the process of forming the second barrier layer comprises an atomic layer deposition process.
10. An interconnect structure, comprising:
a substrate comprising an active region;
a dielectric layer located on the substrate and having an opening through the dielectric layer, the opening being located on the active region;
the metal silicide layer is positioned on the surface of the active region at the bottom of the opening;
the first barrier layer is positioned on the surface of the metal silicide layer;
the second barrier layer is positioned on the surface of the first barrier layer and the side wall of the opening, and the second barrier layer on the side wall of the opening is in contact with the dielectric layer; and
and the second metal layer is positioned on the surface of the second barrier layer and fills the opening.
11. The interconnect structure of claim 10 wherein said metal silicide layer has a thickness of 75 to 140 angstroms.
12. The interconnect structure of claim 10 wherein said first barrier layer has a thickness of 20 to 25 angstroms.
13. The interconnect structure of claim 10 wherein said second barrier layer has a thickness of 10 to 40 angstroms.
14. The interconnect structure of claim 10 wherein the material of said metal silicide layer comprises titanium silicide and the material of said first barrier layer and said second barrier layer comprises titanium nitride.
CN202010120829.0A 2020-02-26 2020-02-26 Interconnect structure and method of forming the same Pending CN113314454A (en)

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