CN113314064B

CN113314064B - Display panel and display device

Info

Publication number: CN113314064B
Application number: CN202110602010.2A
Authority: CN
Inventors: 朱静
Original assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2021-05-31
Filing date: 2021-05-31
Publication date: 2023-01-10
Anticipated expiration: 2041-05-31
Also published as: CN113314064A

Abstract

The invention provides a display panel and a display device, wherein the display panel is provided with a display area and comprises a plurality of routing groups and at least one electronic device, the routing groups are positioned in the display area and are arranged along a first direction, each routing group comprises two first routing lines arranged along the first direction, each first routing line comprises a first main body part and a first bending part connected with the first main body part, the first bending part of any one first routing line in each routing group bends towards the other first routing line, a first accommodating area is formed between two adjacent first bending parts in two adjacent routing groups, and each electronic device is positioned in the corresponding first accommodating area; the scheme can reduce the number of electronic devices so as to reduce parasitic capacitance and improve the working reliability of the GOA circuit.

Description

Display panel and display device

Technical Field

The invention relates to the technical field of display, in particular to manufacturing of a display device, and particularly relates to a display panel and a display device.

Background

At present, in order to realize a narrow frame of a display panel, a large device in a GOA (Gate driver On Array) circuit is generally split into a plurality of sub-devices, and the sub-devices are respectively disposed in a plurality of sub-pixels.

For a high-resolution display panel, the larger number of sub-pixels results in a smaller size of each sub-pixel, i.e., the smaller size of each sub-device is required, so that more sub-devices need to be arranged to meet the performance of a corresponding large device; however, the parasitic capacitance of the large device itself and the parasitic capacitance between the large device and other lines are large due to more sub-devices, which reduces the reliability of the large device and other lines.

Therefore, it is necessary to provide a display panel and a display device which can improve the operational reliability of the GOA circuit and other circuits.

Disclosure of Invention

The embodiment of the invention provides a display panel and a display device, wherein each routing group of the display panel comprises two first routings which are arranged along a first direction, each first routing is arranged to comprise a first main body part and a first bending part connected with the first main body part, the first bending part of any first routing in each routing group is bent towards the other first routing, and a first accommodating area is formed between two adjacent first bending parts in two adjacent routing groups so as to arrange a corresponding electronic device; the problem of the more parasitic capacitance that causes of electron device in current display panel is great to the reliability of GOA circuit work that leads to is lower is solved.

An embodiment of the present invention provides a display panel, the display panel having a display area, the display panel including:

the wiring groups are positioned in the display area and are arranged along a first direction, and each wiring group comprises two first wirings arranged along the first direction;

at least one electronic device;

each first wire comprises a first main body part and a first bending part connected to the first main body part, the first bending part of any first wire in each wire group bends towards the other first wire, a first accommodating area is formed between two adjacent first bending parts in two adjacent wire groups, and each electronic device is located in the corresponding first accommodating area.

In one embodiment, each of the electronic devices includes a thin film transistor.

In one embodiment, the display panel includes:

a gate drive circuit comprising the at least one electronic device.

In one embodiment, the gate driving circuit includes:

the multi-stage grid driving units are arranged along a second direction, each grid driving unit comprises at least one electronic device, at least one electronic device in each grid driving unit is respectively positioned in at least one first accommodating area arranged along the first direction, and the second direction is different from the first direction.

In an embodiment, each of the gate driving units includes a plurality of the electronic devices, and the electronic devices in each of the gate driving units are connected.

In one embodiment, the display panel includes a plurality of clock lines and a plurality of gate lines in the display region, and each of the thin film transistors includes:

a gate portion to which a plurality of the gate portions of the plurality of thin film transistors are connected;

a plurality of source portions of the thin film transistors each connected to the corresponding clock line;

and a plurality of drain portions in the plurality of thin film transistors are connected to the corresponding gate lines.

In one embodiment, the display panel further includes:

the driving thin film transistors are located in the display area and arranged along the first direction, each driving thin film transistor is opposite to the corresponding thin film transistor or two first bending portions in the routing group, and the driving thin film transistors are connected with the corresponding gate lines.

In an embodiment, the first trace is a data line, the display panel further includes a plurality of sub-pixels, and each of the driving tfts includes:

a plurality of driving gate portions of the plurality of driving thin film transistors are connected to the corresponding gate lines;

a plurality of driving source electrode portions of the plurality of driving thin film transistors connected to the corresponding data lines, respectively;

and a plurality of driving drain portions of the plurality of driving thin film transistors are respectively connected to the corresponding sub-pixels.

In an embodiment, each of the routing groups further includes two second routing lines arranged along the first direction, and any one of the second routing lines in each of the routing groups is located on the first side of the corresponding first routing line;

each second wire comprises a second main body part and a second bending part connected to the second main body part, the second bending part of any second wire in each wire group bends towards the other second wire, a second accommodating area is formed between two adjacent second bending parts in two adjacent wire groups, each electronic device is located in the corresponding second accommodating area, and the second accommodating area intersects with the first accommodating area.

Embodiments of the present invention also provide a display device, which includes the display panel as described above.

The invention provides a display panel and a display device, wherein the display panel is provided with a display area, the display panel comprises a plurality of routing groups and at least one electronic device, the routing groups are positioned in the display area and are arranged along a first direction, each routing group comprises two first routing lines arranged along the first direction, each first routing line is arranged to comprise a first main body part and a first bending part connected to the first main body part, the first bending part of any one first routing line in each routing group is bent towards the other first routing line, a first accommodating area is formed between two adjacent first bending parts in two adjacent routing groups, each electronic device is positioned in the corresponding first accommodating area, the electronic devices with larger sizes can be accommodated, the number of the electronic devices is reduced, the parasitic capacitance can be further reduced, and the working reliability of a GOA circuit is improved.

Drawings

The invention is further illustrated by the following figures. It should be noted that the drawings in the following description are only intended to illustrate some embodiments of the invention, and that other drawings may be derived by those skilled in the art without inventive effort.

Fig. 1 is a schematic top view of a display panel according to an embodiment of the present invention;

fig. 2 is a schematic top view of a display panel according to another embodiment of the present invention;

fig. 3 is a circuit diagram of an embodiment of a gate driving unit of a display panel according to an embodiment of the invention.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It should be apparent that the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it is to be understood that the terms "away from", "left", "right", "up", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed in a particular orientation, and operate, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the drawings, elements having similar structures are denoted by the same reference numerals. Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein may be combined with other embodiments.

Embodiments of the present invention provide a display panel including, but not limited to, the following embodiments and combinations of the following embodiments.

In one embodiment, as shown in fig. 1, the display panel 100 has a display area 01, and the display panel 100 includes: a plurality of routing groups 20, the routing groups 20 being located in the display area 01 and arranged along a first direction 02, each routing group 20 including two first routings 201 arranged along the first direction 02; at least one electronic device 30; each of the first traces 201 includes a first main body 2011 and a first bending portion 2012 connected to the first main body 2011, the first bending portion 2012 of any one of the first traces 201 in each of the trace groups 20 is bent toward another one of the first traces 201, a first receiving area 03 is formed between two adjacent first bending portions 2012 in two adjacent trace groups 20, and each of the electronic devices 30 is located in the corresponding first receiving area 03.

Specifically, as shown in fig. 1, a plurality of routing groups 20 arranged in the first direction 02 and a plurality of first traces 201 on the same side in the plurality of routing groups 20 may be arranged in parallel in the first direction 02, a plurality of first main bodies 2011 may extend in a direction perpendicular to the first direction 02, an included angle between each first bending portion 2012 and the corresponding first main body 2011 may be an obtuse angle, and further, the first main body 2011 and the first bending portion 2012 in two first traces 201 in each routing group 20 may form a funnel shape, where the shapes of the plurality of first bending portions 2012 may be systematic or different, and the first bending portion 2012 may include at least one straight line segment or at least one curved line segment. Further, each of the first traces 201 may further include a first connection portion 2013, each of the first connection portions 2013 is connected to the corresponding first bending portion 2012, and a plurality of the first connection portions 2013 may be disposed in parallel with the plurality of the first body portions 2011; still further, each of the first traces 201 may further include a first external expansion portion 2014, the first external expansion portion 2014 is connected to the corresponding first connection portion 2013, a first pixel region 07 is formed between two adjacent first external expansion portions 2014 in two adjacent trace groups 20, and the first pixel region 07 is used for setting sub-pixels.

In one embodiment, as shown in fig. 1, each of the electronic devices 30 includes a thin film transistor 301. The thin film transistor 301 is one of the types of field effect transistors, and may be prepared by sequentially depositing different layers of thin films on a substrate, where the different layers of thin films may include, but are not limited to, a semiconductor active layer, a dielectric layer, and a metal electrode layer. Specifically, the thin film transistor 301 may be an N-type transistor or a P-type transistor, the thin film transistor 301 may be a top gate structure or a bottom gate structure, and the constituent material of the thin film transistor 301 may include, but is not limited to, hydrogenated amorphous silicon, polysilicon, an organic semiconductor material, or a metal oxide.

In one embodiment, as shown in fig. 2, the display panel 100 includes: a gate drive circuit comprising the at least one electronic device 30. Specifically, the display panel 100 further includes a non-display area 04, the non-display area 04 may be disposed around the display area 01, the gate driving circuit may include another portion 40 located in the non-display area 04, the another portion 40 may be located on at least one side of the display area 01, here, taking the example that the another portion 40 is located on the left side of the display area 01 as an example, the gate driving circuit may be connected to a plurality of pixel units located in the display area 01, and the display area 01 may present a corresponding picture by controlling light emitting conditions of the pixel units. It is understood that the gate driving circuit further includes, but is not limited to, at least one thin film transistor 301, and lines, a signal source, and the signal source inputs corresponding electrical signals to the plurality of pixel units through the gate driving circuit for displaying images.

In one embodiment, as shown in fig. 2, the gate driving circuit includes: the gate driving units 401 are arranged in multiple stages along a second direction 05, each gate driving unit 401 includes at least one electronic device 30, at least one electronic device in each gate driving unit 401 is respectively located in at least one first accommodating area 03 arranged along the first direction 02, and the second direction 05 is different from the first direction 02. Specifically, the gate driving circuit may be, but is not limited to, a GOA circuit, and the gate driving circuit is described as a GOA circuit, that is, the gate driving circuit includes multiple stages of gate driving units 401 arranged in cascade, and an output signal of the previous stage or multiple stages of gate driving units 401 may be connected to the current stage, the next stage, or multiple stages of gate driving units 401 as an input signal, so as to implement level transmission of signals. It is understood that when the display panel 100 and the display area 01 are rectangular, the second direction 05 may be perpendicular to the first direction 02, for example, a plurality of the routing groups 20 may be arranged in rows, a plurality of stages of the gate driving units 401 may be arranged in columns, and further, the display area 01 may be provided with a plurality of the routing groups 20 and at least one column of the gate driving units 401.

As shown in fig. 3, an nth gate driving unit 401 is taken as an example for description, where the nth gate driving unit 401 includes an initialization module 405, an inversion module 402, a pull-down module 403, and a pass-through module 404, and the specific analysis is as follows:

specifically, the initialization module 405 includes a thin film transistor T11, a gate and a source of the thin film transistor T11 are loaded with an (N-3) th-stage start signal ST (N-3) and a high voltage signal VDD, respectively, and a drain of the thin film transistor T11 is connected to a node Q (N) of the present stage; wherein, when the (N-3) th stage start signal is at a corresponding high level, the thin film transistor T11 may be turned on such that the potential of the node Q (N) is charged to a potential equal to the high voltage signal VDD;

specifically, the inverter module 402 includes a thin film transistor T51, a thin film transistor T53, a thin film transistor T54, and a thin film transistor T52, the gate and the source of the thin film transistor T51 and the source of the thin film transistor T53 are all connected to the high voltage signal VDD, the gate of the thin film transistor T53 and the drain of the thin film transistor T52 are all connected to the drain of the thin film transistor T51, the gate of the thin film transistor T54 and the gate of the thin film transistor T52 are all connected to the node Q (N) of the current stage, the drain of the thin film transistor T54 and the drain of the thin film transistor T53 are all connected to the node P (N) of the current stage, the source of the thin film transistor T54 and the source of the thin film transistor T52 are all connected to the first low voltage signal VSSQ, the pull-down module 403 includes a thin film transistor T42 and a thin film transistor T32, the gate of the thin film transistor T42 and the gate of the thin film transistor T32 are all connected to the node P (N) of the current stage, the source and the drain of the thin film transistor T42 and the source of the low voltage signal VSSQ (sg) are respectively connected to the second low voltage signal sg 32); it is understood that the thin film transistor T51 and the thin film transistor T53 are turned on, and further, when the node Q (N) is at a corresponding low level, the thin film transistor T54 and the thin film transistor T52 are turned off, the node P (N) of the present stage is loaded with the high voltage signal VDD, which causes the thin film transistor T42 and the thin film transistor T32 to be turned on, so that the potential of the node Q (N) of the present stage and the gate signal G (N) of the present stage are pulled down to be equal to the first low voltage signal VSSQ and the second low voltage signal VSSG, respectively, and conversely, when the node Q (N) of the present stage is at a corresponding high level, the thin film transistor T54 and the thin film transistor T52 are turned on, the node P (N) of the present stage is loaded with the first low voltage signal VSSQ, which causes the thin film transistor T42 and the thin film transistor T32 to be turned off, i.e., the potential of the node Q (N) of the present stage and the gate signal G (N) are not pulled down.

Specifically, the stage transmission module 404 includes a capacitor Cb, a thin film transistor T22, a thin film transistor T21, a thin film transistor T41, and a thin film transistor T31, where a gate of the thin film transistor T22 and a gate of the thin film transistor T21 are both connected to the node Q (N) of the present stage, a source of the thin film transistor T22 and a source of the thin film transistor T21 are both connected to a clock signal CK, a drain of the thin film transistor T22 and a drain of the thin film transistor T21 output a start signal ST (N) of the present stage and a gate signal G (N) of the present stage, respectively, and when the node Q (N) of the present stage is at a corresponding high potential, the start signal ST (N) of the present stage and the gate signal G (N) of the present stage both change with a change of the clock signal CK, and the capacitor Cb maintains a potential of the node Q (N) of the present stage and further raises a potential of the node Q (N) of the present stage by a capacitive coupling effect; the gate of the thin film transistor T41 and the gate of the thin film transistor T31 are both connected to an (N + 3) th-stage start signal ST (N + 3), the source of the thin film transistor T41 and the source of the thin film transistor T31 are respectively connected to the first low-voltage signal VSSQ and the second low-voltage signal VSSG, the drain of the thin film transistor T41 and the drain of the thin film transistor T31 are respectively connected to the node Q (N) of the present stage and the gate signal G (N) of the present stage, and when the (N + 3) th-stage start signal ST (N + 3) is at a corresponding high potential, the potential of the node Q (N) of the present stage and the gate signal G (N) of the present stage are respectively pulled down to be equal to the first low-voltage signal VSSG and the second low-voltage signal VSSG, that is, the start signal ST (N) of the present stage may control whether or not to pull down the potential of the node Q (N-3) of the (N-3) th stage and the gate signal G (N-3) of the (N-3) th stage.

In one embodiment, as shown in fig. 1 and fig. 2, each of the gate driving units 401 includes a plurality of the electronic devices 30, and the electronic devices 30 in each of the gate driving units 401 are connected. Specifically, each of the pixel units includes a plurality of sub-pixels, the display area 01 may include a plurality of sub-pixel regions respectively corresponding to the plurality of sub-pixels, and the plurality of electronic devices 30 in each of the gate driving units 401 may be included in the thin film transistors T21 in the gate driving units 401, it can be understood that the thin film transistors T21 in each of the gate driving units 401 have a larger size, and in order to reduce the area of the non-display area 04 of the display panel 100 to improve the screen occupation ratio, as can be seen from fig. 2 and 3, the thin film transistors T21 may be configured to include a corresponding plurality of thin film transistors 301, so that the thin film transistors T21 are distributed in the display area 01. Specifically, for example, the channel width of the thin film transistor T21 is 25000 micrometers, and if the thin film transistor 301 with a channel width of 10 micrometers can be accommodated in each pixel unit, the thin film transistor T21 needs to be configured to include 2500 thin film transistors 301, that is, the thin film transistor T21 needs to occupy 2500 sub-pixel regions. It can be understood that when the thin film transistor T21 needs more thin film transistors 301, the parasitic capacitances in the plurality of thin film transistors 301 and between the plurality of thin film transistors 301 and the lines in the display area 01 are all larger, which reduces the reliability of the operation of the gate driving unit 401.

It should be noted that, as shown in fig. 1, in the above embodiment, the first bent portion 2012 of any one of the first traces 201 in each of the trace groups 20 is bent toward the other first trace 201, and a first receiving area 03 is formed between two adjacent first bent portions 2012 in two adjacent trace groups 20, it is understood that, since the two corresponding first bent portions 2012 forming the first receiving area 03 are bent toward a direction away from the first receiving area 03, at least the size of the first receiving area 03 in the direction parallel to the first direction 02 is increased, that is, the size of each thin film transistor 301 in the direction parallel to the first direction 02 is increased, and further, for each thin film transistor T21, the number of thin film transistors 301 included in the thin film transistor T21 may be decreased, for example, as shown in table 1, on the basis that the channel width of the thin film transistor T21 is 25000 micrometers, the above embodiment may achieve that the width of the thin film transistor 301 may be increased from 10 micrometers to 35 micrometers, that is, that the number of the thin film transistors included in the thin film transistors T21 is decreased from 2500 to 2500, and that the number of the corresponding transistors T21 is decreased from 10 micrometers. As can be seen from the above analysis, the above embodiment can reduce the parasitic capacitance in the thin film transistors 301 and between the thin film transistors 301 and the lines in the display area 01, so as to improve the reliability of the operation of the gate driving unit 401.

TABLE 1

In one embodiment, as shown in fig. 1, the display panel 100 includes a plurality of clock lines 501 and a plurality of gate lines 502 in the display area 01, and each of the thin film transistors 301 includes: a gate portion 3011 to which the gate portions 3011 of the thin film transistors 301 are connected; a source portion 3012, each of the source portions 3012 of the thin film transistors 301 being connected to the corresponding clock line 501; and a drain portion 3013, wherein the drain portions 3013 of the thin film transistors 301 are connected to the corresponding gate lines 502. Specifically, a plurality of clock lines 501 and a plurality of gate lines 502 may be arranged along the second direction 05, and each clock line 501 and each gate line 502 may extend along the first direction 02. The gate portions 3011, the clock lines 501 and the gate lines 502 may be disposed at the same layer, and the routing group 20, the source portions 3012 and the drain portions 3013 may be disposed at the same layer.

Specifically, as shown in fig. 1, the gate portions 3011 of the thin film transistors 301 arranged along the first direction 02 may extend towards two ends so that two ends of each gate portion 3011 are respectively disposed in contact with two adjacent gate portions 3011, that is, the gate portions 3011 arranged along the first direction 02 may extend along a direction parallel to the first direction 02, so that the gate portions 3011 of the thin film transistors 301 arranged along the first direction 02 are connected, that is, each gate portion 3011 includes a gate main body and a gate connecting body located at two sides of the gate main body, where the gate connecting bodies of the gate portions 3011 intersect with the first routing line 201 to form a first external capacitor. Further, each of the thin film transistors 301 further includes an active portion 3014 on the corresponding gate body, and a projection of the active portion 3014 on the corresponding gate body does not exceed a boundary of the gate body.

Specifically, as shown in fig. 1, the source portions 3012 of the thin film transistors 301 arranged in the first direction 02 may extend towards both ends to exceed the corresponding active portion 3014 and the corresponding gate portion 3011, wherein an internal parasitic capacitance is formed between each of two portions of the source portion 3012 exceeding the corresponding active portion 3014 and the corresponding gate portion 3011, further, the clock line 501 may include a plurality of clock line segments, a corresponding clock line segment is disposed between two adjacent source portions 3012 arranged in the first direction 02, each clock line segment connects two corresponding adjacent source portions 3012 and transmits a clock signal, and similarly, a second external trace parasitic capacitance is formed at an intersection of the plurality of clock line segments and the first external trace 201. Specifically, the drain portions 3013 of the thin film transistors 301 arranged along the first direction 02 may extend towards one end to exceed the corresponding active portion 3014 and the corresponding gate portion 3011, and further, a portion of each drain portion 3013 that exceeds the corresponding gate portion 3011 is connected to the corresponding gate portion 3011.

It can be understood that, as shown in table 1, based on the channel width of the thin film transistor T21 being 25000 micrometers, according to the analysis above, the above embodiment can achieve that the number of the thin film transistors 301 included in the thin film transistor T21 is reduced from 2500 to 714, and correspondingly, the number of the internal parasitic capacitors in the thin film transistor T21 can be reduced from 5000 to 1428, that is, the number of the internal parasitic capacitors in the thin film transistor T21 is reduced to 0.2857 times, similarly, since before the improvement, the first routing lines 201 and the thin film transistors 301 are in one-to-one correspondence, as shown in fig. 1, after the improvement, two corresponding first routing lines 201 are respectively disposed on two sides of each thin film transistor 301, that is, the number of the second external capacitors in the thin film transistor T21 can be reduced from 2500 to 1428, that is, that the second external parasitic capacitors in the thin film transistor T21 are reduced to 0.5712 times, so as to improve the reliability of the operation of the gate driving unit 401.

In an embodiment, as shown in fig. 1, each of the routing line groups 20 further includes two second routing lines 202 arranged along the first direction 02, and any one of the second routing lines 202 in each of the routing line groups 20 is located at a first side of the corresponding first routing line 201; each of the second traces 202 includes a second main body portion 2021 and a second curved portion 2022 connected to the second main body portion 2021, the second curved portion 2022 of any one of the second traces 202 in each of the routing groups 20 is curved toward the other second trace 202, a second accommodating area 06 is formed between two adjacent second curved portions 2022 in two adjacent routing groups 20, each of the electronic devices 30 is located in the corresponding second accommodating area 06, and the second accommodating area 06 intersects with the first accommodating area 03.

Taking the relative position relationship in fig. 1 as an example, the first side may be understood as a left side or a right side, that is, each of the routing line groups 20 may sequentially include the second routing line 202, the first routing line 201, the second routing line 202 and the first routing line 201 along the first direction 02, or each of the routing line groups 20 may sequentially include the first routing line 201, the second routing line 202, the first routing line 201 and the second routing line 202 along the first direction 02. The shape of each second trace 202 of each routing group 20 may be the same as or different from the shape of the corresponding first trace 201, and further, the second trace 202 and the first trace 201 on the same side in each routing group 20 may be disposed in parallel. It can be understood that, since any one of the second traces 202 in each of the trace groups 20 is located on the first side of the corresponding first trace 201, that is, the corresponding second accommodating area 06 can be offset to the left or right relative to the corresponding first accommodating area 03, that is, the two areas intersect with each other, further, each of the electronic devices 30 is located in an area where the corresponding second accommodating area 06 intersects with the corresponding first accommodating area 03.

It can be understood that, as shown in table 1, based on that the channel width of the thin film transistor T21 is 25000 micrometers, according to the above analysis, the above embodiment can achieve that the number of the second external parasitic capacitors in the thin film transistor T21 is reduced from 2500 to 1428, that is, the number of the second external parasitic capacitors in the thin film transistor T21 is reduced to 0.5712 times, and similarly, when each of the routing line groups 20 further includes two second routing lines 202, that is, the intersections of a plurality of clock line segments and the second routing lines 202 also form the second external parasitic capacitors, so that the above embodiment can achieve that the number of the second external parasitic capacitors in the thin film transistor T21 is reduced from 5000 to 2856, that is, the number of the second external parasitic capacitors in the thin film transistor T21 is reduced to 0.5712 times, and the operational reliability of the gate driving unit 401 is improved.

In one embodiment, as shown in fig. 1, the display panel 100 further includes: a plurality of driving tfts 60, the driving tfts 60 are located in the display area 01 and are arranged along the first direction 02, each of the driving tfts 60 is disposed opposite to the corresponding tft 301 or the two first bending portions 2012 of the routing group 20, and the driving tfts 60 are connected to the corresponding gate line 502. It is understood from the above analysis that, in the first direction 02, the plurality of routing groups 20 and the plurality of first receiving areas 03 are alternately arranged, further, the plurality of first bending portions 2012 and the plurality of first receiving areas 03 in the plurality of routing groups 20 are alternately arranged, specifically, the corresponding thin film transistors 301 may be disposed on the upper side of the first bending portions 2012, and the corresponding thin film transistors 301 may be disposed on the upper side of the thin film transistors 301, or it is understood that, in the first direction 02, the plurality of first main body portions 2011 and the plurality of driving thin film transistors 60 are alternately arranged.

In an embodiment, as shown in fig. 1, the first trace 201 is a data line, the display panel 100 further includes a plurality of sub-pixels 70, and each of the driving thin film transistors 60 includes: a plurality of driving gate portions 601 of the plurality of driving thin film transistors 60, each of the plurality of driving gate portions 601 being connected to a corresponding one of the gate lines 502; a plurality of driving source parts 602, wherein the plurality of driving source parts 602 in the plurality of driving thin film transistors 60 are respectively connected to the corresponding data lines 201; and a driving drain portion 603, wherein each of the driving drain portions 603 of the driving thin film transistors 60 is connected to the corresponding sub-pixel 70.

Specifically, as shown in fig. 1, a plurality of the sub-pixels 70 and a plurality of the driving tfts 60 are in one-to-one correspondence, and each of the sub-pixels 70 may be located on a side of the corresponding driving tft 60 far away from the corresponding first main body 2011. It should be noted that, in combination with the above analysis, the first pixel region 07 is formed between two adjacent first outward-extending portions 2014 in two adjacent routing line groups 20, and further, the first pixel region 07 is also formed between two adjacent first outward-extending portions 2014 in each routing line group 20. Specifically, for example, fig. 1 illustrates an nth row arrangement unit, a plurality of first outward-extending portions 2014 in the nth row arrangement unit may be respectively connected to a plurality of first connecting portions 2013 in the (n + 1) th row arrangement unit, and each of the first pixel regions 07 in the nth row arrangement unit may be provided with a corresponding one of the sub-pixels 70 and a corresponding one of the driving tfts 60 in the (n + 1) th row arrangement unit, i.e., a plurality of sub-pixels 70 connected to a plurality of the driving tfts 60 in the nth row arrangement unit may be respectively located in a plurality of the first pixel regions 07 in the (n-1) th row arrangement unit.

Specifically, as shown in fig. 1, the gate line 502 includes a plurality of gate line segments, each of the gate line segments is located between two adjacent driving gate portions 601 and connected to the two adjacent driving gate portions 601, it can be understood that a plurality of gate portions 3011 located in the same row are all connected to the corresponding gate line 502 to connect the corresponding plurality of driving gate portions 601, wherein the plurality of driving gate portions 601 and the plurality of sub-pixels 70 may also be disposed at the same layer as the plurality of gate lines 502. Further, each of the driving thin film transistors 60 further includes a driving active portion 604 on the corresponding driving gate portion 601, and a projection of the driving active portion 604 on the corresponding driving gate portion 601 does not exceed a boundary of the driving gate portion 601.

Specifically, as shown in fig. 1, each of the plurality of driving source parts 602 of the plurality of driving thin film transistors 60 arranged along the first direction 02 may extend to one end to extend beyond the corresponding driving active part 604 and the corresponding driving gate part 601 to be connected to the corresponding data line 201, wherein the extending direction of each driving source part 602 depends on the relative position of each driving source part 602 and the corresponding data line 201. Similarly, the driving drain portions 603 of the driving tfts 60 arranged along the first direction 02 may extend towards one end to exceed the corresponding driving active portion 604 and the corresponding driving gate portion 601 so as to be connected to the corresponding sub-pixels 70, for example, each driving drain portion 603 of the n-th row arrangement unit may extend upwards to the corresponding first pixel region 07 of the n-th row arrangement unit so as to be connected to the corresponding sub-pixel 70 of the n-th row arrangement unit. The plurality of driving source portions 602 and the plurality of driving drain portions 603 may be provided in the same layer as the plurality of wiring groups 20.

Embodiments of the present invention also provide a display device, which includes the display panel as described in any one of the above.

The invention provides a display panel and a display device, the display panel is provided with a display area, the display panel comprises a plurality of routing groups and at least one electronic device, the routing groups are positioned in the display area and are arranged along a first direction, each routing group comprises two first routing wires arranged along the first direction, each first routing wire is arranged to comprise a first main body part and a first bending part connected to the first main body part, the first bending part of any one first routing wire in each routing group is bent towards the other first routing wire, a first accommodating area is formed between two adjacent first bending parts in two adjacent routing groups, each electronic device is positioned in the corresponding first accommodating area, the electronic devices with larger sizes can be accommodated, the number of the electronic devices is reduced, the parasitic capacitance is further reduced, and the working reliability of a GOA circuit is improved.

The display panel and the display device provided by the embodiment of the invention are described in detail, and the principle and the embodiment of the invention are explained by applying a specific example, and the description of the embodiment is only used for helping to understand the technical scheme and the core idea of the invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A display panel having a display area, the display panel comprising:

at least one electronic device;

each first wire comprises a first main body part and a first bending part connected to the first main body part, the first bending part of any first wire in each wire group bends towards the other first wire, a first accommodating area is formed between two adjacent first bending parts in two adjacent wire groups, and each electronic device is located in the corresponding first accommodating area;

each routing line group further comprises two second routing lines arranged along the first direction, and any one second routing line in each routing line group is positioned on the first side of the corresponding first routing line;

each second wire comprises a second main body part and a second bending part connected to the second main body part, the second bending part of any second wire in each wire group bends towards the other second wire, a second accommodating area is formed between two adjacent second bending parts in two adjacent wire groups, each electronic device is located in the corresponding second accommodating area, and the second accommodating areas are intersected with the first accommodating areas.

2. The display panel according to claim 1, wherein each of the electronic devices comprises a thin film transistor.

3. The display panel according to claim 2, characterized in that the display panel comprises:

a gate drive circuit comprising the at least one electronic device.

4. The display panel according to claim 3, wherein the gate driving circuit comprises:

5. The display panel according to claim 4, wherein each of the gate driving units comprises a plurality of the electronic devices, and the plurality of the electronic devices in each of the gate driving units are connected.

6. The display panel according to claim 5, wherein the display panel comprises a plurality of clock lines and a plurality of gate lines in the display area, and each of the thin film transistors comprises:

7. The display panel according to claim 6, wherein the display panel further comprises:

8. The display panel according to claim 7, wherein the first traces are data lines, the display panel further includes a plurality of sub-pixels, and each of the driving tfts includes:

and a plurality of driving drain portions of the plurality of driving thin film transistors respectively connected to the corresponding sub-pixels.

9. A display device characterized in that it comprises a display panel according to any one of claims 1 to 8.