CN113311606A

CN113311606A - Substrate for display device and display device

Info

Publication number: CN113311606A
Application number: CN202110578924.XA
Authority: CN
Inventors: 王颜彬; 徐飞; 洪俊; 李京勇; 杨盛际; 罗美建
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Priority date: 2021-05-26
Filing date: 2021-05-26
Publication date: 2021-08-27
Anticipated expiration: 2041-05-26
Also published as: CN113311606B

Abstract

The embodiment of the disclosure provides a substrate for a display device and the display device thereof, which relate to the technical field of display and aim to reduce the reject ratio of the display device. The substrate for the display device comprises binding pins, a test electrode, a first conductive pattern and a second conductive pattern, wherein the binding pins comprise a plurality of first pins and second pins, the first pins comprise a first target pin and a second target pin which are adjacently arranged, and a pressure difference exists between a first voltage signal transmitted by the first target pin and a second voltage signal transmitted by the second target pin; the second pin is in a floating state; gaps are reserved between the test electrodes and the corresponding binding pins; at least one first conductive pattern covers the first target pin and the corresponding test electrode, or covers the second target pin and the corresponding test electrode; the second conductive pattern covers at least a portion of the second lead, and has a gap with the corresponding test electrode. The present disclosure is for making a display device.

Description

Substrate for display device and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a substrate for a display device and a display device thereof.

Background

With the rapid development of display technologies, display devices have gradually spread throughout the lives of people. Currently, in the manufacturing process of a display device, a high temperature and high humidity reliability test is required. However, the display device in the related art often has a problem of black screen after a high temperature and high humidity reliability test, and the defective rate of the display device is high.

Disclosure of Invention

The present disclosure provides a substrate for a display device and a display device thereof, so as to reduce the fraction defective of the display device.

In one aspect, a substrate for a display device is provided. The substrate for a display device includes a substrate, a plurality of bonding pins, a plurality of test electrodes, a plurality of first conductive patterns, and at least one second conductive pattern. The plurality of binding pins are arranged on the substrate; the plurality of binding pins comprise a plurality of first pins and at least one second pin, the plurality of first pins comprise a first target pin and a second target pin which are adjacently arranged, the first target pin is configured to transmit a first voltage signal, the second target pin is configured to transmit a second voltage signal, and a voltage difference exists between the first voltage signal and the second voltage signal; the second pin is configured to be in a floating state. The plurality of test electrodes are arranged on the substrate; each test electrode corresponds to one binding pin, and a gap is formed between each test electrode and the corresponding binding pin. At least one first conductive pattern covers the first target pin and the test electrode corresponding to the first target pin, or covers the second target pin and the test electrode corresponding to the second target pin. The second conductive pattern at least covers a part of the second pin, and a gap is formed between the test electrodes corresponding to the second pin.

In some embodiments, the first target pin is configured to transmit a supply voltage signal and the second target pin is configured to transmit a reference voltage signal.

In some embodiments, the first target lead and the corresponding test electrode, and the second target lead and the corresponding test electrode, which are adjacently disposed, are covered by the first conductive pattern.

In some embodiments, other pins of the plurality of first pins except the first target pin and the second target pin, and corresponding test electrodes are covered by the first conductive pattern.

In some embodiments, the plurality of bonding pins are aligned in a first direction, and the plurality of test electrodes are aligned in the first direction; each binding pin and the corresponding test electrode are arranged in a line along a second direction, and the second direction is approximately perpendicular to the first direction.

In some embodiments, the at least one second pin is disposed on at least one of two opposite sides of the plurality of first pins along the first direction.

In some embodiments, the substrate for a display device includes a plurality of second pins symmetrically disposed on two opposite sides of the first pins along the first direction.

In some embodiments, the length of the gap between the bonding pin and its corresponding test electrode along the second direction is 1.5 μm to 2.5 μm.

In some embodiments, a side of the second pin near the test electrode is not covered by the second conductive pattern.

The substrate for a display device provided by the present disclosure includes a first target pin, a test electrode corresponding to the first target pin, a second target pin, and a test electrode corresponding to the second target pin, at least one of which is covered by a first conductive pattern. Under the condition, in a high-temperature high-pressure reliability test, the target pin covered by the first conductive pattern in the first target pin and the second target pin cannot be in contact with an external organic matter and water oxygen, namely, the target pin covered by the first conductive pattern cannot be corroded and diffused to the periphery, so that the risk of micro short circuit between two adjacent target pins can be reduced, and the reject ratio of the display device is reduced.

In addition, the second conductive pattern at least covers the part of the second pin, so that the corrosion diffusion of the second pin to the periphery can be reduced, and a gap is formed between the second conductive pattern and the test electrode corresponding to the second pin, so that in the binding process, the pressing position of the binding pressure head can be accurately identified through the gap, and the binding pressure head is prevented from pressing the test electrode, and further, a functional circuit below the test electrode is prevented from being damaged.

In yet another aspect, a display device is provided. The display device comprises the substrate for the display device and the driving integrated circuit, wherein the driving integrated circuit is electrically connected with the plurality of binding pins and the plurality of testing electrodes of the substrate for the display device.

Compared with the prior art, the beneficial effects of the display device provided by the embodiment of the disclosure are the same as those of the substrate for a display device provided by any one of the embodiments, and are not repeated herein.

Drawings

In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to the drawings. Furthermore, the drawings in the following description may be regarded as schematic diagrams, and do not limit the actual size of products, the actual flow of methods, the actual timing of signals, and the like, involved in the embodiments of the present disclosure.

FIG. 1 is a block diagram of a display device according to some embodiments;

FIG. 2 is a schematic diagram of a basic structure of a display device according to some embodiments;

FIG. 3 is an exploded view of a display device according to some embodiments;

FIG. 4 is a cross-sectional view at I-I' of the display panel of FIG. 1 as an electroluminescent display panel;

FIG. 5 is a cross-sectional view taken along line I-I' of the display device shown in FIG. 1 when the display panel is a liquid crystal display panel;

FIG. 6 is a block diagram of a substrate for a display device according to some embodiments;

FIG. 7 is a partially enlarged view of a substrate for a display device according to the related art, the substrate including bonding pins and testing electrodes;

FIG. 8 is a partially enlarged view of a bonding pin and a test electrode of another substrate for a display device in the related art;

FIG. 9 is an enlarged view of a portion of a substrate for a display device at the bonding pins and test electrodes, in accordance with some embodiments;

FIG. 10 is an enlarged view of a portion of another substrate for a display device with bonding pins and test electrodes according to some embodiments;

FIG. 11 is an enlarged view of a portion of a substrate for a display device where bonding pins and test electrodes are located, according to some embodiments;

FIG. 12 is a diagram illustrating the ESD analysis results of the target area of the bonding pad and the test electrode in the related art;

FIG. 13 is a graph of results of ESD analysis of a target area of a bond pin and a test electrode, according to some embodiments;

FIG. 14A is a cross-sectional view of the substrate M-M' for a display device shown in FIG. 11;

fig. 14B is a cross-sectional view of the substrate N-N' for a display device shown in fig. 11.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.

Unless the context requires otherwise, throughout the description and the claims, the term "comprise" and its other forms, such as the third person's singular form "comprising" and the present participle form "comprising" are to be interpreted in an open, inclusive sense, i.e. as "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, expressions of "connected" and "electrically connected," along with their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, the term "electrically connected" may be used in describing some embodiments to indicate that two or more components are in direct electrical contact. The term "electrically connected," however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

The use of "adapted to" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values may in practice be based on additional conditions or values beyond those stated.

As used herein, "about," "approximately," or "approximately" includes the stated values as well as average values that are within an acceptable range of deviation for the particular value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system).

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

As shown in fig. 1, some embodiments of the present disclosure provide a display device 100, and the display device 100 may be a television, a mobile phone, a computer, a notebook computer, a tablet computer, a Personal Digital Assistant (PDA), a vehicle-mounted computer, or the like.

Among them, the Display device 100 may be a Liquid Crystal Display (LCD); the display device 100 may also be an electroluminescent display device or a photoluminescent display device. In the case that the display device 100 is an electroluminescent display device, the electroluminescent display device may be an Organic Light-Emitting display device (OLED) or a Quantum Dot electroluminescent display device (QLED). In the case where the display device 100 is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

As shown in fig. 2, the display device 100 includes a display panel 1, a frame 2, a cover 3, and other electronic components such as a circuit board 4. In the case where the display device 100 is a liquid crystal display device, the display device 100 further includes a backlight assembly configured to provide light required for displaying a picture to the display panel 1. The backlight assembly is not illustrated in fig. 2.

The longitudinal section of the frame 2 is U-shaped, the cover plate 3 is arranged on the opening side of the frame 2, the display panel 1, the circuit board 4 and other electronic accessories are arranged in the frame 2, and the circuit board 4 is bound and connected with the display panel 1.

In some embodiments, as shown in fig. 3, the display panel 1 has a display area AA and a peripheral area BB disposed on at least one side of the display area AA, and fig. 3 illustrates the display area AA surrounded by the peripheral area BB.

Here, the display area AA is an area where an image is displayed, and the display area AA is configured to set the sub-pixels P. The peripheral area BB is an area where no image is displayed, and the peripheral area BB may be configured to arrange various signal lines required for displaying a screen; the peripheral region BB may also be configured to arrange a gate driving circuit that outputs a scanning signal to the sub-pixels P of the display region AA, a source driving circuit that outputs a data signal to the sub-pixels P of the display region AA, and the like.

In some embodiments, the display panel 1 is an electroluminescent display panel, and as shown in fig. 4, the electroluminescent display panel includes a display substrate 11 and an encapsulation layer 12 for encapsulating the display substrate 11.

Here, the sealing layer 12 may be a sealing film or a sealing substrate.

As shown in fig. 4, each Sub-pixel of the above-described display substrate 11 includes a light emitting device and a pixel driving circuit provided on a first substrate Sub1, and the pixel driving circuit includes a plurality of thin film transistors 111. The thin film transistor 111 includes an active layer, a source electrode, a drain electrode, a gate electrode, and a gate insulating layer, the source electrode and the drain electrode being in contact with the active layer, respectively. The light emitting device includes an anode 112, a light emitting function layer 113, and a cathode 114, the anode 112 is electrically connected to a source or a drain of the thin film transistor 111 which is a driving transistor among the plurality of thin film transistors 111, and the anode 112 and the drain of the thin film transistor 111 are electrically connected as illustrated in fig. 4.

The display substrate 11 further includes a pixel defining layer 115, the pixel defining layer 115 including a plurality of opening regions, one light emitting device being disposed in one of the opening regions.

In some embodiments, the light emitting function layer 113 includes only a light emitting layer. In other embodiments, the light emitting function layer 113 includes at least one of an Electron Transport Layer (ETL), an Electron Injection Layer (EIL), a Hole Transport Layer (HTL), and a Hole Injection Layer (HIL), in addition to the light emitting layer.

In some embodiments, as shown in fig. 4, the display substrate 11 further includes a planarization layer 116 disposed between the thin film transistor 111 and the anode 112.

In some embodiments, as shown in fig. 4, the display substrate 11 further includes a first protection layer 117, and the first protection layer 117 is disposed on a side of the cathode 114 facing away from the first substrate Sub 1.

In some embodiments, the display panel 1 is a liquid crystal display panel, and as shown in fig. 5, the liquid crystal display panel includes an array substrate 13 and a pair of cell substrates 14 which are oppositely disposed, and a liquid crystal layer 15 disposed between the array substrate 13 and the pair of cell substrates 14.

Each Sub-pixel of the array substrate 13 includes a thin film transistor 111 and a pixel electrode 131 on a first substrate Sub 1. The pixel electrode 131 is electrically connected to the source or drain of the thin film transistor 111, and fig. 5 illustrates the pixel electrode 131 and the drain of the thin film transistor 111 as being electrically connected.

In some embodiments, as shown in fig. 5, the array substrate 13 further includes a common electrode 132, and the common electrode 132 is disposed on the first substrate Sub 1.

Illustratively, the pixel electrode 131 and the common electrode 132 may be disposed at the same layer, in which case, the pixel electrode 131 and the common electrode 132 are each a comb-tooth structure including a plurality of strip-shaped sub-electrodes.

Exemplarily, the pixel electrode 131 and the common electrode 132 may also be disposed at different layers, in which case, as shown in fig. 5, the first insulating layer 133 is disposed between the pixel electrode 131 and the common electrode 132.

Further, in the case where the common electrode 132 is provided between the thin film transistor 111 and the pixel electrode 131, as shown in fig. 5, a second insulating layer 134 is provided between the common electrode 132 and the thin film transistor 111.

In other embodiments, the pair of cell substrates 14 includes a second substrate Sub2 and a common electrode 132, and the common electrode 132 is disposed on the second substrate Sub 2.

As shown in fig. 5, the liquid crystal display panel further includes a color filter layer CF and a black matrix pattern BM. The color filter layer CF at least comprises a red photoresist unit arranged in the red sub-pixel, a green photoresist unit arranged in the green sub-pixel and a blue photoresist unit arranged in the blue sub-pixel. The black matrix pattern BM is configured to separate light emitted from different sub-pixels, and has an effect of reducing reflected light generated after external ambient light enters the inside of the liquid crystal display panel.

As shown in fig. 5, the liquid crystal display panel further includes an upper polarizer 16 disposed on the opposite-to-cell substrate 14 side away from the liquid crystal layer 15, and a lower polarizer 17 disposed on the array substrate 13 side away from the liquid crystal layer 15.

Some embodiments of the present disclosure provide a substrate 1000 for a display device, and the substrate 1000 for a display device may be applied to the display device 100 described in any of the above embodiments.

In the case where the display device 100 is a liquid crystal display device, referring to fig. 5, the substrate 1000 for a display device provided by the embodiment of the present disclosure may be a liquid crystal display panel; the array substrate 13 in the liquid crystal display panel may be used.

In the case where the display device 100 is an electroluminescent display device, referring to fig. 4, the substrate 1000 for a display device provided by the embodiment of the present disclosure may be an electroluminescent display panel; or may be the display substrate 11 in an electroluminescent display panel.

It can be understood that, referring to fig. 3 and 6, the substrate 1000 for a display device has a display area AA and a peripheral area BB located at least on one side of the display area AA, the peripheral area BB includes a bonding area CC, the bonding area CC is provided with a plurality of bonding pins 1100, and the circuit board 4 and the substrate 1000 for a display device are bonded and connected through the plurality of bonding pins 1100.

It is understood that after the source and drain electrodes in the substrate 1000 for a display device are manufactured, each circuit in the substrate 1000 for a display device needs to be inspected to determine whether each circuit in the substrate 1000 for a display device has a problem of short circuit or open circuit.

Based on this, in some embodiments, as shown in fig. 6, the substrate 1000 for display further includes a plurality of test electrodes 1200 disposed in the bonding region CC, and each test electrode 1200 is electrically connected to one bonding pin 1100. In this way, a series of driving signals, such as a pixel driving signal, a GOA driving signal, etc., may be input through the test electrodes 1200 by the test equipment to output a scan signal and a light emitting signal to the subpixels P of the display area AA.

Since the test electrodes 1200 are only used to inspect each circuit without performing a bonding process, connection traces of a functional circuit and the functional circuit may be disposed under the test electrodes 1200. However, since the bonding process is performed on the bonding pin 1100, the functional circuit and the connection trace cannot be disposed below the bonding pin 1100, so as to prevent the functional circuit from being damaged by pressure.

In view of this, in some embodiments, a side of the test electrode 1200 close to the substrate Sub (i.e., the first substrate Sub1) is provided with a functional circuit, which may be a source driver circuit 1500 (see fig. 14A and 14B), which is beneficial to the narrow frame design of the display device 100.

In some related art, referring to fig. 7 and 8, a significant step is left between the test electrode 1200 and the bonding pin 1100, the step having a length D1 of about 2 μm; the bonding pin 1100 is provided with a conductive pattern 1300 ', and the conductive pattern 1300' covers the bonding pin 1100, so that only one side of the bonding pin 1100 near the test electrode 1200 is exposed.

However, the display device 100 in the related art often has a problem of a black screen after a high temperature and high humidity reliability test.

At this time, electrostatic discharge (ESD) analysis is performed on the plurality of test electrodes 1200 and the plurality of bonding pins 1100, and it is found that active element aluminum (see table 1) appears at a cross (see a square in fig. 12) between the AVEE pin and the test electrode 1200 corresponding thereto and between the Verf1 pin and the test electrode 1200 corresponding thereto included in the plurality of bonding pins 1100 in the related art, so that a micro short circuit occurs on the AVEE pin and the Verf1 pin, which causes the voltage of the Verf1 pin to be pulled out of a preset range, thereby causing a black screen of the display device 100.

The AVEE pin is configured to transmit a power supply voltage to a drive Integrated Circuit (IC), the Verf1 pin is configured to transmit a reference voltage to the drive IC, and the AVEE pin and the Verf1 pin are adjacently arranged.

TABLE 1

Element(s)	Line type	Apparent concentration	k ratio	Wt％	Wt％Sifma	Standard sample label
							C	K line system	111.35	1.11354	79.93	0.66	C Vit
O	K line system	23.76	0.07995	7.29	0.3	SiO₂
							Al	K line system	1.98	0.01422	0.89	0.18	Al₂O₃
Si	K line system	8.2	0.06494	3.97	0.29	SiO₂
							Cl	K line system	13.71	0.11985	7.92	0.6	NaCl

Each element has a characteristic position which can represent the element, and the K line system refers to the characteristic position corresponding to each element; the apparent concentration refers to the intensity ratio of the target element in the measured sample to the target element in the standard sample; the K ratio refers to the linear energy of the K line; wt% refers to the mass percentage of the element; wt% Sifma means the deviation of the mass percentage content of the element; the standard sample label refers to the substance to which the element should belong, which is obtained by comparing the result of the test with the substance provided by the national standardization organization; CVit refers to an element containing carbon.

Based on this, some embodiments of the present disclosure provide a substrate 1000 for a display device, as shown in fig. 6, 9 and 10, the substrate 1000 for a display device including a substrate Sub, a plurality of bonding pins 1100, a plurality of test electrodes 1200, a plurality of first conductive patterns 1300 and at least one second conductive pattern 1400. Here, the substrate Sub is the first substrate Sub1 described above regardless of whether the display device substrate 1000 is used for a liquid crystal display device or an electroluminescence display device.

As shown in fig. 6 and 9, a plurality of bonding pins 1100 are disposed on a substrate Sub, the plurality of bonding pins 1100 includes a plurality of first pins 1110 and at least one second pin 1120, the plurality of first pins 1110 includes a first target pin 1111 and a second target pin 1112 disposed adjacent to each other, and the first target pin 1111 is configured to transmit a first voltage signal; the second target pin 1112 is configured to transmit a second voltage signal; a voltage difference is formed between the first voltage signal and the second voltage signal; the second pin 1120 is configured in a floating state, i.e., the second pin 1120 is not connected to any circuit.

With continued reference to fig. 6 and 9, a plurality of test electrodes 1200 are disposed on the substrate Sub, each test electrode 1200 corresponds to one of the bonding pins 1100, and a gap is formed between the test electrode 1200 and the corresponding bonding pin 1100.

Here, one binding pin 1100 for each test electrode 1200 means that the test electrode 1200 and its corresponding binding pin 1100 are configured to transmit the same signal. For example, the test electrode 1200 corresponding to the first target pin 1111, is also configured to transmit a first voltage signal; a test electrode 1200 corresponding to the second target pin 1112, also configured to transmit a second voltage signal; the test electrodes 1200 corresponding to the second pins 1120 are also configured in a floating state, i.e., the test electrodes 1200 corresponding to the second pins 1120 are not connected to any circuit.

As shown in fig. 9 and 10, at least one first conductive pattern 1300 covers a first target lead 1111 and a test electrode 1200 corresponding to the first target lead 1111, or covers a second target lead 1112 and a test electrode 1200 corresponding to the second target lead 1112.

Referring to fig. 9 and 10, the second conductive pattern 1400 covers at least a portion of the second leads 1120, and there is a gap between the test electrodes 1200 corresponding to the second leads 1120.

As can be seen from the above description, in the substrate 1000 for a display device according to some embodiments of the present disclosure, at least one of the first target pin 1111 and the test electrode 1200 corresponding to the first target pin 1111, and the second target pin 1112 and the test electrode 1200 corresponding to the second target pin 1112 is covered by the first conductive pattern 1300. In this case, in the high temperature and high pressure reliability test, the target pin covered by the first conductive pattern 1300 in the first target pin 1111 and the second target pin 1112 cannot contact with the external organic matter and the water and oxygen, that is, the target pin covered by the first conductive pattern 1300 does not corrode and diffuse to the surroundings, so that the risk of micro short circuit between two adjacent target pins can be reduced, and the defect rate of the display device 100 can be reduced.

In addition, the second conductive pattern 1400 covers at least a portion of the second lead 1120, so that corrosion diffusion of the second lead 1120 to the surroundings can be reduced, and a gap is formed between the second conductive pattern 1400 and the test electrode 1200 corresponding to the second lead 1120, so that in the binding process, the pressing position of the binding pressure head can be accurately identified through the gap, and the binding pressure head is prevented from pressing the test electrode 1200, thereby preventing the functional circuit below the test electrode 1200 from being damaged.

Here, in order to ensure that the plurality of bonding pins 1100 can form reliable bonding with the circuit board 4 and ensure good conductive effect, in some embodiments, the materials of the bonding pins 1100 and the test electrode 1200 are both made of a metal material with high activity, such as aluminum.

Here, in order to ensure conductivity of the first conductive pattern 1300 and the second conductive pattern 1400 and reduce the risk of diffusion of atoms on the first conductive pattern 1300 and the second conductive pattern 1400, in some embodiments, a less active metal, such as Indium Tin Oxides (ITO), is used as a material of the first conductive pattern 1300 and the second conductive pattern 1400.

Fig. 14A is a cross-sectional view of the display device substrate M-M 'shown in fig. 11, and fig. 14B is a cross-sectional view of the display device substrate N-N' shown in fig. 11. In some embodiments, referring to fig. 14A and 14B, the substrate 1000 for a display device further includes a functional circuit, a first insulating layer 1600, and a second insulating layer 1700. Here, the functional circuit may be the source driver circuit 1500.

Illustratively, the functional circuit is arranged on the substrate Sub, the first insulating layer 1600 is arranged on the side of the functional circuit, which faces away from the substrate Sub, and the first insulating layer 1600 is reserved with a setting position of the bonding pin 1100; the first insulating layer 1700 is disposed on a side of the first insulating layer 1600 facing away from the substrate Sub, a setting position of the test electrode 1200 and a setting position of the bonding pin 1100 are reserved, and the bonding pin 1100 is disposed in the reserved setting position corresponding to the test electrode 1200.

Here, the bonding pin 1100 may be fabricated separately after the functional circuit and each insulating layer are fabricated, or may be fabricated with the same material as other metal layers in the substrate 1000 for a display device, for example, the same material as the same layer of the source or the drain, which is not limited in this disclosure.

In some embodiments, referring to fig. 9 and 10, the first target pin 1111 is configured to transmit a power supply voltage signal and the second target pin 1112 is configured to transmit a reference voltage signal. In this way, at least one of the first target lead 1111 and the test electrode 1200 corresponding to the first target lead 1111, and the second target lead 1112 and the test electrode 1200 corresponding to the second target lead 1112 is covered by the first conductive pattern 1300.

Illustratively, the first target lead 1111 and the test electrode 1200 corresponding to the first target lead 1111 are covered by the first conductive pattern 1300. At this time, the first target lead 1111 and the test electrode 1200 corresponding to the first target lead 1111 cannot contact with external organic substances and water and oxygen, and the first target lead 1111 and the aluminum atoms on the test electrode 1200 corresponding to the first target lead 1111 cannot be corroded and diffused to the surroundings; meanwhile, the material of the first conductive pattern 1300 is indium tin oxide, which has low activity, and the indium tin oxide of the first conductive pattern 1300 hardly corrodes and diffuses around or diffuses very little, so that the risk of a micro short circuit occurring between the first target pin 1111 and the second target pin 1112 can be reduced, and the risk of a black screen occurring after the high temperature and high humidity reliability test of the display device 100 is reduced.

In some embodiments, as shown in fig. 9 and 10, the first target lead 1111 and the corresponding test electrode 1200, and the second target lead 1112 and the corresponding test electrode 1200, which are adjacently disposed, are covered by the first conductive pattern 1300.

At this time, the first target lead 1111 and the test electrode 1200 corresponding to the first target lead 111 are covered by one first conductive pattern 1300, and the second target lead 1112 and the test electrode 1200 corresponding to the second target lead 1112 are covered by the other first conductive pattern 1300. In this case, the first target lead 1111 and the aluminum atoms on the test electrode 1200 corresponding to the first target lead 1111 cannot be corroded and diffused to the surroundings; the second target lead 1112 and the aluminum atoms on the test electrode 1200 corresponding to the second target lead 1112 cannot be corroded and diffused to the periphery; meanwhile, the material of the first conductive pattern 1300 is indium tin oxide, which has lower activity, and the indium tin oxide of the first conductive pattern 1300 hardly corrodes and diffuses around or diffuses very little, so that the risk of micro short circuit between the first target pin 1111 and the second target pin 1112 can be further reduced, and the defect rate of the display device 100 can be reduced.

In some embodiments, the other pins of the plurality of first pins 1110 except for the first target pin 1111 and the second target pin 1112, and the corresponding test electrodes 1200 are covered by the first conductive pattern 1300. That is, each of the first leads 1110 and the test electrode 1200 corresponding to the first lead 1110 are covered by one of the first conductive patterns 1300. At this time, aluminum atoms on any two adjacent first leads 1110 of the plurality of first leads 1110 and the test electrode 1200 corresponding to the first leads 1110 cannot be corroded and diffused to the periphery, and the ito of the first conductive pattern 1300 hardly corrodes and diffuses to the periphery or diffuses to a small extent, so that the risk of micro-short between any two adjacent first leads 1110 can be reduced, and the defect rate of the display device 100 can be reduced.

In some embodiments, as shown in fig. 6 and 9, the plurality of bonding pins 1100 are aligned in a first direction X, and the plurality of test electrodes 1200 are aligned in the first direction X; each bonding pin 1100 is aligned with its corresponding test electrode 1200 along a second direction Y that is substantially perpendicular to the first direction X.

Here, the direction of the first direction X is not particularly limited. Illustratively, the first direction X is approximately parallel to the boundary of the substrate 1000 for a display device near the circuit board 4.

On this basis, along the second direction Y, the length D2 of the gap between the bonding pin 1100 and the corresponding test electrode 1200 is 1.5 μm to 2.5 μm; illustratively, the length D2 of the gap between the bonding pin 1100 and its corresponding test electrode 1200 is any one of 1.5 μm, 2 μm, and 2.5 μm.

Thus, the space occupied by the bonding pins 1100 and the test electrodes 1200 on the substrate Sub as a whole can be reduced, which is advantageous for the narrow frame design of the substrate 1000 for a display device. In addition, the substrate 1000 for a display device may be manufactured by bonding the leads 1100 and the test electrodes 1200 using a conventional process.

In some embodiments, as shown in fig. 9 and 10, a side of the second pin 1120 close to the test electrode 1200 is not covered by the second conductive pattern 1400, i.e., a side of the second pin 1120 close to the test electrode 1200 is exposed. In this way, in the process of manufacturing the second conductive pattern 1400 by using the sputtering process, the used mask can completely cover the test electrode 1200 and the gap between the test electrode 1200 and the bonding pin 1100, so that the material for manufacturing the second conductive pattern 1400 is prevented from being sputtered into the gap between the test electrode 1200 and the bonding pin 1100, and the pressing position of the bonding pressure head can be accurately identified in the subsequent bonding process.

Here, except that one side of the second pin 1120 close to the test electrode 1200 is not covered by the second conductive pattern 1400, the other sides of the second pin 1120 are covered by the second conductive pattern 1400.

In some embodiments, as shown in fig. 10 and 11, the at least one second pin 1120 is disposed on at least one of two opposite sides of the plurality of first pins 1110 along the first direction X. In this way, the first pins 1110 are distributed in a concentrated manner, and the second pins 1120 are distributed in a concentrated manner, so that the process difficulty is reduced, and the production and the manufacture are facilitated.

In some embodiments, as shown in fig. 10 and 11, the substrate 1000 for a display device includes a plurality of second pins 1120, and the plurality of second pins 1120 are symmetrically disposed on two opposite sides of the plurality of first pins 1110 along the first direction X. In this case, in the subsequent binding process, the reference regions (gaps between the second leads 1120 and the corresponding test electrodes 1200) for identifying the bonding positions of the binding indenters are located at opposite sides of the plurality of first leads 1110 in the first direction X, which can improve the accuracy of identifying the bonding positions of the binding indenters.

For example, as shown in fig. 11, the substrate 1000 for a display device includes 4 second pins 1120, and each two second pins 1120 are symmetrically disposed on two opposite sides of the first pins 1110 along the first direction X. The press-fit position of the binding pressure head is identified on each side through the gaps between the two second pins 1120 and the corresponding test electrodes 1200, so that the risk of identification errors can be reduced, and the identification accuracy is improved; in addition, the processes of the symmetrically arranged second pins 1120 are consistent, which is beneficial to the subsequent impedance monitoring.

At this time, the cross intersection (see the square frame in fig. 13) between the first target pin 1111 and the test electrode 1200 corresponding to the second target pin 1112 is subjected to ESD analysis, and the analysis result is shown in table 2.

Wherein the first target pin 1111 is configured to transmit a power supply voltage signal, and the second target pin 1112 is configured to transmit a reference voltage signal.

TABLE 2

Element(s)	Line type	Apparent concentration	k ratio	Wt％	Wt％Sifma	Standard sample label
							C	K line system	134.32	1.3432	81.88	0.53	C Vit
O	K line system	39.84	0.13406	12.11	0.34	SiO₂
							Si	K line system	7	0.05548	3.45	0.27	SiO₂
Cl	K line system	4.35	0.03804	2.56	0.41	NaCl

Some embodiments of the present disclosure provide a display device 100, and referring to fig. 1, 3 and 6, the display device 100 includes a substrate 1000 for a display device of any of the above embodiments and a driving integrated circuit electrically connected to a plurality of bonding pins 1100 and a plurality of test electrodes 1200 of the substrate 100 for a display device.

Compared with the prior art, the beneficial effects of the display device 100 provided by the embodiment of the present disclosure are the same as the beneficial effects of the substrate 1000 for a display device provided by any of the above embodiments, and are not repeated herein.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art will appreciate that changes or substitutions within the technical scope of the present disclosure are included in the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A substrate for a display device, comprising:

a substrate;

a plurality of bonding pins disposed on the substrate; the plurality of binding pins comprise a plurality of first pins and at least one second pin, the plurality of first pins comprise a first target pin and a second target pin which are adjacently arranged, the first target pin is configured to transmit a first voltage signal, the second target pin is configured to transmit a second voltage signal, and a voltage difference exists between the first voltage signal and the second voltage signal; the second pin is configured to be in a floating state;

a plurality of test electrodes disposed on the substrate; each test electrode corresponds to one binding pin, and a gap is formed between each test electrode and the corresponding binding pin;

a plurality of first conductive patterns, at least one first conductive pattern covering the first target pin and a test electrode corresponding to the first target pin, or covering the second target pin and a test electrode corresponding to the second target pin;

and the second conductive pattern at least covers part of the second pin, and a gap is reserved between the test electrodes corresponding to the second pin.

2. The substrate according to claim 1, wherein the first target pin is configured to transmit a power supply voltage signal, and the second target pin is configured to transmit a reference voltage signal.

3. The substrate according to claim 1, wherein a first target lead and a corresponding test electrode, and a second target lead and a corresponding test electrode, which are disposed adjacent to each other, are covered with the first conductive pattern.

4. The substrate according to claim 1, wherein the other pins of the plurality of first pins except the first target pin and the second target pin, and the corresponding test electrodes are covered with the first conductive pattern.

5. The substrate according to claim 1, wherein the plurality of bonding pins are aligned in a first direction, and the plurality of test electrodes are aligned in the first direction;

each binding pin and the corresponding test electrode are arranged in a line along a second direction, and the second direction is approximately perpendicular to the first direction.

6. The substrate according to claim 5, wherein the at least one second lead is provided on at least one of two opposite sides of the plurality of first leads along the first direction.

7. The substrate according to claim 5, wherein the substrate comprises a plurality of second pins symmetrically disposed on two opposite sides of the first pins along the first direction.

8. The substrate according to any one of claims 5 to 7, wherein a length of a gap between the bonding pin and the corresponding test electrode in the second direction is 1.5 μm to 2.5 μm.

9. The substrate according to claim 1, wherein a side of the second pin near the test electrode is not covered with the second conductive pattern.

10. A display device, comprising:

a substrate for a display device according to any one of claims 1 to 9;

and a driving integrated circuit electrically connected to the plurality of bonding pins and the plurality of test electrodes of the substrate for a display device.