CN113311606B

CN113311606B - Substrate for display device and display device thereof

Info

Publication number: CN113311606B
Application number: CN202110578924.XA
Authority: CN
Inventors: 王颜彬; 徐飞; 洪俊; 李京勇; 杨盛际; 罗美建
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Priority date: 2021-05-26
Filing date: 2021-05-26
Publication date: 2023-06-20
Anticipated expiration: 2041-05-26
Also published as: CN113311606A

Abstract

The embodiment of the disclosure provides a substrate for a display device and the display device thereof, and relates to the technical field of display so as to reduce the reject ratio of the display device. The substrate for the display device comprises binding pins, a test electrode, a first conductive pattern and a second conductive pattern, wherein the binding pins comprise a plurality of first pins and second pins, the first pins comprise a first target pin and a second target pin which are adjacently arranged, and a pressure difference exists between a first voltage signal transmitted by the first target pin and a second voltage signal transmitted by the second target pin; the second pin is in a floating state; gaps are reserved between the test electrodes and the corresponding binding pins; at least one first conductive pattern covers the first target pin and the corresponding test electrode, or covers the second target pin and the corresponding test electrode; the second conductive pattern at least covers part of the second pin, and a gap is arranged between the second conductive pattern and the corresponding test electrode. The present disclosure is used to fabricate a display device.

Description

Substrate for display device and display device thereof

Technical Field

The disclosure relates to the field of display technology, and in particular relates to a substrate for a display device and the display device thereof.

Background

With the rapid development of display technology, display devices have been gradually spread throughout the life of people. Currently, in the process of manufacturing a display device, a high-temperature high-humidity reliability test is required. However, after the high-temperature high-humidity reliability test, the display device in the related art often has the problem of black screen, and the reject ratio of the display device is high.

Disclosure of Invention

The present disclosure provides a substrate for a display device and a display device thereof, so as to reduce the defective rate of the display device.

In one aspect, a substrate for a display device is provided. The substrate for a display device includes a substrate, a plurality of bonding pins, a plurality of test electrodes, a plurality of first conductive patterns, and at least one second conductive pattern. The binding pins are arranged on the substrate; the plurality of binding pins comprise a plurality of first pins and at least one second pin, the plurality of first pins comprise a first target pin and a second target pin which are adjacently arranged, the first target pin is configured to transmit a first voltage signal, the second target pin is configured to transmit a second voltage signal, and a voltage difference exists between the first voltage signal and the second voltage signal; the second pin is configured to be in a floating state. The plurality of test electrodes are arranged on the substrate; each test electrode corresponds to one binding pin, and a gap is reserved between the test electrode and the corresponding binding pin. At least one first conductive pattern covers the first target pin and a test electrode corresponding to the first target pin, or covers the second target pin and a test electrode corresponding to the second target pin. The second conductive pattern at least covers part of the second pin, and a gap is arranged between the test electrodes corresponding to the second pin.

In some embodiments, the first target pin is configured to transmit a supply voltage signal and the second target pin is configured to transmit a reference voltage signal.

In some embodiments, the first target pin and the corresponding test electrode, and the second target pin and the corresponding test electrode, which are adjacently disposed, are covered by the first conductive pattern.

In some embodiments, other pins of the plurality of first pins, except for the first target pin and the second target pin, and corresponding test electrodes are covered by the first conductive pattern.

In some embodiments, the plurality of bonding pins are aligned along a first direction, and the plurality of test electrodes are aligned along the first direction; each binding pin and the corresponding test electrode are arranged in a row along a second direction, and the second direction is approximately perpendicular to the first direction.

In some embodiments, the at least one second pin is disposed on at least one of opposite sides of the plurality of first pins along the first direction.

In some embodiments, the substrate for a display device includes a plurality of second pins symmetrically disposed on opposite sides of the plurality of first pins along the first direction.

In some embodiments, the length of the gap between the bonding pins and their corresponding test electrodes is 1.5 μm to 2.5 μm along the second direction.

In some embodiments, a side of the second pin near the test electrode is not covered by the second conductive pattern.

The display device substrate provided by the disclosure comprises a first target pin, a test electrode corresponding to the first target pin, a second target pin and a test electrode corresponding to the second target pin, wherein at least one of the first target pin and the test electrode corresponding to the first target pin is covered by a first conductive pattern. In this case, in the high-temperature high-pressure reliability test, the target pins covered by the first conductive pattern of the first target pins and the second target pins cannot be in contact with external organic matters and water oxygen, i.e., the target pins covered by the first conductive pattern cannot corrode and spread to the surrounding, so that the risk of micro short circuit between two adjacent target pins can be reduced, and the reject ratio of the display device is reduced.

In addition, the second conductive pattern at least covers the part of the second pin, so that corrosion diffusion of the second pin to the periphery can be reduced, and a gap is formed between the second conductive pattern and the test electrode corresponding to the second pin, so that the pressing position of the binding pressure head can be accurately identified through the gap in the binding process, the binding pressure head is prevented from pressing the test electrode, and further, the functional circuit below the test electrode is damaged.

In yet another aspect, a display device is provided. The display device comprises the substrate for the display device and the drive integrated circuit according to any of the embodiments, wherein the drive integrated circuit is electrically connected with a plurality of binding pins and a plurality of test electrodes of the substrate for the display device.

Compared with the prior art, the display device provided by the embodiment of the present disclosure has the same beneficial effects as the substrate for a display device provided by any one of the embodiments, and will not be described herein.

Drawings

In order to more clearly illustrate the technical solutions of the present disclosure, the drawings that need to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings may be obtained according to these drawings to those of ordinary skill in the art. Furthermore, the drawings in the following description may be regarded as schematic diagrams, not limiting the actual size of the products, the actual flow of the methods, the actual timing of the signals, etc. according to the embodiments of the present disclosure.

FIG. 1 is a block diagram of a display device according to some embodiments;

fig. 2 is a schematic diagram of a basic structure of a display device according to some embodiments;

FIG. 3 is an exploded view of a display device according to some embodiments;

FIG. 4 is a cross-sectional view of the display panel of FIG. 1 at I-I' when the display panel is an electroluminescent display panel;

FIG. 5 is a cross-sectional view of the display device of FIG. 1 at I-I' when the display panel is a liquid crystal display panel;

fig. 6 is a structural view of a substrate for a display device according to some embodiments;

FIG. 7 is a partial enlarged view of a binding pin and a test electrode of a substrate for a display device according to the related art;

FIG. 8 is a partial enlarged view of a binding pin and a test electrode of another substrate for a display device according to the related art;

FIG. 9 is an enlarged view of a portion of a bonding pin and test electrode of a substrate for a display device according to some embodiments;

FIG. 10 is an enlarged view of a portion of a bonding pin and test electrode of another substrate for a display device according to some embodiments;

FIG. 11 is an enlarged view of a portion of a bonding pin and test electrode of yet another substrate for a display device according to some embodiments;

FIG. 12 is a graph showing the results of ESD analysis performed on a target area of a bonding pad and a test electrode in the related art;

FIG. 13 is a graph of results of an ESD analysis performed on a binding pin and a target area of a test electrode, according to some embodiments;

fig. 14A is a cross-sectional view of the display device substrate M-M' shown in fig. 11;

fig. 14B is a cross-sectional view of the display device substrate N-N' shown in fig. 11.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by one of ordinary skill in the art based on the embodiments provided by the present disclosure are within the scope of the present disclosure.

Throughout the specification and claims, unless the context requires otherwise, the word "comprise" and its other forms such as the third person referring to the singular form "comprise" and the present word "comprising" are to be construed as open, inclusive meaning, i.e. as "comprising, but not limited to. In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", "some examples", "and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present disclosure, unless otherwise indicated, the meaning of "a plurality" is two or more.

In describing some embodiments, expressions of "connected" and "electrically connected" and derivatives thereof may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, the term "electrically connected" may be used in describing some embodiments to indicate that two or more elements are in direct electrical contact. However, the term "electrically connected" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the disclosure herein.

The use of "adapted" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" one or more of the stated conditions or values may be based on additional conditions or beyond the stated values in practice.

As used herein, "about," "approximately" or "approximately" includes the stated values as well as average values within an acceptable deviation range of the particular values as determined by one of ordinary skill in the art in view of the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system).

Exemplary embodiments are described herein with reference to cross-sectional and/or plan views as idealized exemplary figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

As shown in fig. 1, some embodiments of the present disclosure provide a display device 100, where the display device 100 may be a television, a mobile phone, a computer, a notebook computer, a tablet computer, a personal digital assistant (Personal Digital Assistant, abbreviated as PDA), a vehicle computer, or the like.

The display device 100 may be a liquid crystal display device (Liquid Crystal Display, LCD for short); the display device 100 may also be an electroluminescent display device or a photoluminescent display device. In the case where the display device 100 is an electroluminescent display device, the electroluminescent display device may be an Organic Light-Emitting Diode (OLED) or a quantum dot electroluminescent display device (Quantum Dot Light Emitting Diodes, QLED). In the case where the display device 100 is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

As shown in fig. 2, the display device 100 includes other electronic components such as a display panel 1, a frame 2, a cover plate 3, and a circuit board 4. In the case where the display device 100 is a liquid crystal display device, the display device 100 further includes a backlight assembly configured to provide light required for displaying a picture to the display panel 1. The backlight assembly is not illustrated in fig. 2.

The longitudinal section of the frame 2 is U-shaped, the cover plate 3 is disposed at the opening side of the frame 2, the display panel 1, the circuit board 4 and other electronic accessories are disposed in the frame 2, and the circuit board 4 is connected with the display panel 1 in a binding manner.

In some embodiments, as shown in fig. 3, the display panel 1 has a display area AA and a peripheral area BB located on at least one side of the display area AA, and fig. 3 is schematically shown by taking the peripheral area BB surrounding the display area AA as an example.

Here, the display area AA is an area where an image is displayed, and the display area AA is configured to set the subpixels P. The peripheral area BB is an area where an image is not displayed, and the peripheral area BB may be configured to arrange various signal lines necessary for displaying a screen; the peripheral region BB may also be configured to arrange a gate driving circuit that outputs a scanning signal to the sub-pixels P of the display region AA, a source driving circuit that outputs a data signal to the sub-pixels P of the display region AA, and the like.

In some embodiments, the display panel 1 is an electroluminescent display panel, as shown in fig. 4, which includes a display substrate 11 and an encapsulation layer 12 for encapsulating the display substrate 11.

Here, the encapsulation layer 12 may be an encapsulation film or an encapsulation substrate.

As shown in fig. 4, each of the Sub-pixels of the display substrate 11 described above includes a light emitting device and a pixel driving circuit, which include a plurality of thin film transistors 111, disposed on the first substrate Sub1. The thin film transistor 111 includes an active layer, a source electrode, a drain electrode, a gate electrode, and a gate insulating layer, and the source electrode and the drain electrode are respectively in contact with the active layer. The light emitting device includes an anode 112, a light emitting function layer 113, and a cathode 114, and the anode 112 is electrically connected to a source or a drain of the thin film transistor 111 as a driving transistor among the plurality of thin film transistors 111, which is illustrated in fig. 4 by the electrical connection of the anode 112 and the drain of the thin film transistor 111.

The display substrate 11 further includes a pixel defining layer 115, and the pixel defining layer 115 includes a plurality of opening regions in which one light emitting device is disposed.

In some embodiments, the light emitting functional layer 113 includes only a light emitting layer. In other embodiments, the light emitting functional layer 113 includes at least one of an electron transport layer (election transporting layer, ETL for short), an electron injection layer (election injection layer, EIL for short), a hole transport layer (hole transporting layer, HTL for short), and a hole injection layer (hole injection layer, HIL for short) in addition to the light emitting layer.

In some embodiments, as shown in fig. 4, the display substrate 11 further includes a planarization layer 116 disposed between the thin film transistor 111 and the anode 112.

In some embodiments, as shown in fig. 4, the display substrate 11 further includes a first protection layer 117, and the first protection layer 117 is disposed on a side of the cathode 114 facing away from the first substrate Sub1.

In some embodiments, the display panel 1 is a liquid crystal display panel, as shown in fig. 5, and the liquid crystal display panel includes an array substrate 13 and a counter substrate 14 disposed opposite to each other, and a liquid crystal layer 15 disposed between the array substrate 13 and the counter substrate 14.

Each subpixel of the array substrate 13 includes a thin film transistor 111 and a pixel electrode 131 on the first substrate Sub1. The pixel electrode 131 is electrically connected to the source or drain of the thin film transistor 111, and the pixel electrode 131 is electrically connected to the drain of the thin film transistor 111 in fig. 5.

In some embodiments, as shown in fig. 5, the array substrate 13 further includes a common electrode 132, and the common electrode 132 is disposed on the first substrate Sub1.

Illustratively, the pixel electrode 131 and the common electrode 132 may be disposed at the same layer, in which case the pixel electrode 131 and the common electrode 132 are each of a comb-tooth structure including a plurality of stripe-shaped sub-electrodes.

The pixel electrode 131 and the common electrode 132 may be exemplarily provided at different layers, in which case, as shown in fig. 5, a first insulating layer 133 is provided between the pixel electrode 131 and the common electrode 132.

In addition, in the case where the common electrode 132 is provided between the thin film transistor 111 and the pixel electrode 131, as shown in fig. 5, a second insulating layer 134 is provided between the common electrode 132 and the thin film transistor 111.

In other embodiments, the counter substrate 14 includes a second substrate Sub2 and a common electrode 132, and the common electrode 132 is disposed on the second substrate Sub 2.

As shown in fig. 5, the liquid crystal display panel further includes a color filter layer CF and a black matrix pattern BM. The color filter layer CF at least includes a red photoresist unit disposed in the red subpixel, a green photoresist unit disposed in the green subpixel, and a blue photoresist unit disposed in the blue subpixel. The black matrix pattern BM is configured to space light emitted from different sub-pixels and has a function of reducing reflected light generated after external ambient light enters the inside of the liquid crystal display panel.

As shown in fig. 5, the liquid crystal display panel further includes an upper polarizer 16 disposed on a side of the opposite case substrate 14 away from the liquid crystal layer 15, and a lower polarizer 17 disposed on a side of the array substrate 13 away from the liquid crystal layer 15.

Some embodiments of the present disclosure provide a substrate 1000 for a display device, and the substrate 1000 for a display device may be applied to the display device 100 described in any of the above embodiments.

In the case where the display device 100 is a liquid crystal display device, referring to fig. 5, the substrate 1000 for a display device provided in the embodiment of the present disclosure may be a liquid crystal display panel; the array substrate 13 in the liquid crystal display panel may be used.

In the case where the display device 100 is an electroluminescent display device, referring to fig. 4, the substrate 1000 for a display device provided in the embodiment of the present disclosure may be an electroluminescent display panel; or may be the display substrate 11 in an electroluminescent display panel.

As can be understood, referring to fig. 3 and 6, the display device substrate 1000 has a display area AA and a peripheral area BB located at least one side of the display area AA, the peripheral area BB including a bonding area CC, the bonding area CC being provided with a plurality of bonding pins 1100, and the circuit board 4 is bonded to the display device substrate 1000 through the plurality of bonding pins 1100.

It will be appreciated that after the source and drain electrodes in the display device substrate 1000 are fabricated, each circuit in the display device substrate 1000 needs to be inspected to determine whether each circuit in the display device substrate 1000 has a problem of short or open circuit.

Based on this, in some embodiments, as shown in fig. 6, the display substrate 1000 further includes a plurality of test electrodes 1200 disposed at the bonding areas CC, and each test electrode 1200 is electrically connected to one bonding pin 1100. In this way, a series of driving signals such as a pixel driving signal, a GOA driving signal, etc. may be inputted through the test electrode 1200 by using the test device to output a scan signal and a light emitting signal to the sub-pixels P of the display area AA.

Since the test electrode 1200 is used only for inspecting each circuit without performing a binding process, connection wirings of the functional circuits and the functional circuits can be disposed under the test electrode 1200. However, the binding pin 1100 cannot be provided with the functional circuit and the connection wire under the binding pin 1100 due to the subsequent binding process, so that the functional circuit is prevented from being crushed.

Based on this, in some embodiments, the test electrode 1200 is provided with a functional circuit on a side close to the substrate Sub (i.e. the first substrate Sub 1), and the functional circuit may be a source driving circuit 1500 (see fig. 14A and 14B), which facilitates the narrow frame design of the display device 100.

In some related art, referring to fig. 7 and 8, a significant step is left between the test electrode 1200 and the bonding pin 1100, the step having a length D1 of about 2 μm; the bonding pad 1100 is provided with a conductive pattern 1300 ', and the conductive pattern 1300' is covered on the bonding pad 1100, so that only one side of the bonding pad 1100 close to the test electrode 1200 is exposed.

However, the display device 100 in the related art often has a problem of black screen after the high temperature and high humidity reliability test.

At this time, the electrostatic discharge (Electro static discharge, abbreviated as ESD) analysis is performed at the plurality of test electrodes 1200 and the plurality of bonding pins 1100, and it is found that the intersections between the AVEE pins and their corresponding test electrodes 1200 and the Verf1 pins and their corresponding test electrodes 1200 (see the boxes in fig. 12) included in the plurality of bonding pins 1100 in the related art are where active elemental aluminum is present (see table 1 for analysis results), so that micro-short circuits occur at the AVEE pins and the Verf1 pins, resulting in the voltage of the Verf1 pins being pulled out of the preset range, thereby causing a black screen of the display device 100.

Wherein the AVEE pin is configured to transmit a power supply voltage to a driving integrated circuit (Integrated circuit, abbreviated as IC), the Verf1 pin is configured to transmit a reference voltage to the driving IC, and the AVEE pin AVEE and the Verf1 pin are disposed adjacently.

TABLE 1

Element(s)	Line type	Apparent concentration	k ratio of	Wt％	Wt％Sifma	Standard sample label
							C	K-wire system	111.35	1.11354	79.93	0.66	C Vit
O	K-wire system	23.76	0.07995	7.29	0.3	SiO ₂
							Al	K-wire system	1.98	0.01422	0.89	0.18	Al ₂ O ₃
Si	K-wire system	8.2	0.06494	3.97	0.29	SiO ₂
							Cl	K-wire system	13.71	0.11985	7.92	0.6	NaCl

Wherein, each element has a characteristic position which can represent the element, and the K line refers to the characteristic position corresponding to each element; the apparent concentration refers to the intensity ratio of the target element in the sample to be measured to the target element in the standard sample; the K ratio refers to the linear energy of the K line; wt% refers to the mass percentage of elements; wt% Sifma refers to the deviation of the mass percentage content of the element; the standard sample label refers to what substance the obtained element should belong to according to the test result and comparing substances provided by national standards organization; CVit refers to a carbon-containing element.

Based on this, some embodiments of the present disclosure provide a substrate 1000 for a display device, as shown in fig. 6, 9 and 10, the substrate 1000 for a display device including a substrate Sub, a plurality of bonding pins 1100, a plurality of test electrodes 1200, a plurality of first conductive patterns 1300 and at least one second conductive pattern 1400. The substrate Sub is the first substrate Sub1, regardless of whether the display device substrate 1000 is used for a liquid crystal display device or an electroluminescent display device.

As shown in fig. 6 and 9, a plurality of bonding pins 1100 are disposed on a substrate Sub, the plurality of bonding pins 1100 include a plurality of first pins 1110 and at least one second pin 1120, the plurality of first pins 1110 include a first target pin 1111 and a second target pin 1112 disposed adjacently, and the first target pin 1111 is configured to transmit a first voltage signal; the second target pin 1112 is configured to transmit a second voltage signal; a voltage difference is arranged between the first voltage signal and the second voltage signal; the second pin 1120 is configured in a floating state, i.e., the second pin 1120 is not connected to any circuit.

With continued reference to fig. 6 and 9, a plurality of test electrodes 1200 are disposed on the substrate Sub, each test electrode 1200 corresponds to one bonding pin 1100, and a gap is formed between the test electrode 1200 and the corresponding bonding pin 1100.

Here, each test electrode 1200 corresponds to one bonding pin 1100, meaning that the test electrode 1200 and its corresponding bonding pin 1100 are configured to transmit the same signal. For example, the test electrode 1200 corresponding to the first target pin 1111 is also configured to transmit a first voltage signal; a test electrode 1200 corresponding to the second target pin 1112, also configured to transmit a second voltage signal; the test electrode 1200 corresponding to the second pin 1120 is also configured in a floating state, i.e., the test electrode 1200 corresponding to the second pin 1120 is not connected to any circuit.

As shown in fig. 9 and 10, at least one first conductive pattern 1300 covers a first target pin 1111 and a test electrode 1200 corresponding to the first target pin 1111, or covers a second target pin 1112 and a test electrode 1200 corresponding to the second target pin 1112.

With continued reference to fig. 9 and 10, the second conductive pattern 1400 covers at least a portion of the second lead 1120, and has a gap between the test electrodes 1200 corresponding to the second lead 1120.

As can be seen from the above description, some embodiments of the present disclosure provide a substrate 1000 for a display device, which includes at least one of a first target lead 1111 and a test electrode 1200 corresponding to the first target lead 1111, and a second target lead 1112 and a test electrode 1200 corresponding to the second target lead 1112, which are covered by a first conductive pattern 1300. In this case, in the high temperature and high pressure reliability test, the target pins covered by the first conductive pattern 1300 of the first target pins 1111 and the second target pins 1112 cannot be contacted with the external organic matters and the water oxygen, i.e., the target pins covered by the first conductive pattern 1300 cannot be corroded and spread to the surrounding, so that the risk of micro short circuit between two adjacent target pins can be reduced, and the reject ratio of the display device 100 can be reduced.

In addition, the second conductive pattern 1400 at least covers the second lead 1120, so that the corrosion diffusion of the second lead 1120 to the periphery can be reduced, and a gap is formed between the second conductive pattern 1400 and the test electrode 1200 corresponding to the second lead 1120, so that the pressing position of the binding press head can be accurately identified through the gap in the binding process, the binding press head is prevented from pressing the test electrode 1200, and further the functional circuit below the test electrode 1200 is damaged.

Here, in order to ensure that the plurality of bonding pins 1100 and the circuit board 4 can form a reliable bond and ensure a good conductive effect, in some embodiments, the bonding pins 1100 and the test electrodes 1200 are made of a metal material with relatively high activity, such as aluminum.

Here, in order to secure conductivity of the first conductive pattern 1300 and the second conductive pattern 1400 and reduce the risk of atomic diffusion on the first conductive pattern 1300 and the second conductive pattern 1400, in some embodiments, a material of the first conductive pattern 1300 and the second conductive pattern 1400 employs a less reactive metal, for example, indium tin oxide (Indium tin oxides, abbreviated as ITO).

Fig. 14A is a cross-sectional view of the display device substrate M-M 'shown in fig. 11, and fig. 14B is a cross-sectional view of the display device substrate N-N' shown in fig. 11. In some embodiments, referring to fig. 14A and 14B, the substrate 1000 for a display device further includes a functional circuit, a first insulating layer 1600, and a second insulating layer 1700. Here, the functional circuit may be the source driving circuit 1500.

Illustratively, the functional circuitry is disposed on the substrate Sub, the first insulating layer 1600 is disposed on a side of the functional circuitry facing away from the substrate Sub, and the first insulating layer 1600 is reserved with the set bits of the bonding pins 1100; the first insulating layer 1700 is disposed on a side of the first insulating layer 1600 facing away from the substrate Sub, where a set bit of the test electrode 1200 and a set bit of the bonding pin 1100 are reserved, and the bonding pin 1100 and the test electrode 1200 are correspondingly disposed in the reserved set bit.

Here, the bonding pins 1100 may be formed separately after the functional circuits and the insulating layers are formed, but may also be formed of the same material as other metal layers in the substrate 1000 for a display device, for example, the source electrode or the drain electrode, which is not limited in this disclosure.

In some embodiments, referring to fig. 9 and 10, the first target pin 1111 is configured to transmit a supply voltage signal and the second target pin 1112 is configured to transmit a reference voltage signal. In this way, at least one of the first target lead 1111 and the test electrode 1200 corresponding to the first target lead 1111, and the second target lead 1112 and the test electrode 1200 corresponding to the second target lead 1112 is covered with the first conductive pattern 1300.

Illustratively, the first target pins 1111 and the test electrodes 1200 corresponding to the first target pins 1111 are covered by the first conductive patterns 1300. At this time, the first target pins 1111 and the test electrodes 1200 corresponding to the first target pins 1111 cannot be in contact with external organics and water oxygen, and aluminum atoms on the first target pins 1111 and the test electrodes 1200 corresponding to the first target pins 1111 cannot be corroded and diffused to the surrounding; meanwhile, the material of the first conductive pattern 1300 is indium tin oxide, and the activity of the indium tin oxide is low, the indium tin oxide of the first conductive pattern 1300 can hardly corrode and diffuse to the surrounding or diffuse very little, so that the risk of micro-short circuit of the first target pin 1111 and the second target pin 1112 can be reduced, and the risk of black screen of the display device 100 after the high-temperature high-humidity reliability test is reduced.

In some embodiments, as shown in fig. 9 and 10, the first target pins 1111 and the corresponding test electrodes 1200, and the second target pins 1112 and the corresponding test electrodes 1200, which are adjacently disposed, are covered by the first conductive patterns 1300.

At this time, the first target pins 1111 and the test electrodes 1200 corresponding to the first target pins 111 are covered with one first conductive pattern 1300, and the second target pins 1112 and the test electrodes 1200 corresponding to the second target pins 1112 are covered with the other first conductive pattern 1300. In this way, the first target lead 1111 and the aluminum atoms on the test electrode 1200 corresponding to the first target lead 1111 cannot be corroded and diffused to the surrounding; the second target lead 1112 and the aluminum atoms on the test electrode 1200 corresponding to the second target lead 1112 cannot be corrosive-diffused to the surroundings; meanwhile, the material of the first conductive pattern 1300 is indium tin oxide, which has low activity, and the indium tin oxide of the first conductive pattern 1300 hardly corrodes or diffuses to the surrounding, so that the risk of micro-short circuit between the first target lead 1111 and the second target lead 1112 can be further reduced, and the reject ratio of the display device 100 is reduced.

In some embodiments, other pins of the plurality of first pins 1110, except for the first target pin 1111 and the second target pin 1112, and the corresponding test electrodes 1200, are covered by the first conductive pattern 1300. That is, each of the first pins 1110 and the test electrodes 1200 corresponding to the first pins 1110 are covered with one first conductive pattern 1300. At this time, the aluminum atoms on the test electrode 1200 corresponding to the first leads 1110 of any two adjacent first leads 1110 among the plurality of first leads 1110 cannot be diffused by corrosion to the surrounding, and the indium tin oxide of the first conductive pattern 1300 hardly diffuses or diffuses little by corrosion to the surrounding, so that the risk of micro-short circuit between any two adjacent first leads 1110 can be reduced, and the defective rate of the display device 100 can be reduced.

In some embodiments, as shown in fig. 6 and 9, a plurality of bonding pins 1100 are aligned along a first direction X, and a plurality of test electrodes 1200 are aligned along the first direction X; each bonding pin 1100 is aligned with its corresponding test electrode 1200 along a second direction Y that is substantially perpendicular to the first direction X.

Here, the direction of the first direction X is not particularly limited. Illustratively, the first direction X is approximately parallel to a boundary of the display device substrate 1000 near the circuit board 4.

On this basis, along the second direction Y, the length D2 of the gap between the bonding pin 1100 and its corresponding test electrode 1200 is 1.5 μm to 2.5 μm; illustratively, the length D2 of the gap between the bonding pin 1100 and its corresponding test electrode 1200 is any one of 1.5 μm, 2 μm, and 2.5 μm.

In this way, the space occupation of the whole binding pins 1100 and the test electrodes 1200 on the substrate Sub can be reduced, which is beneficial to the narrow frame design of the substrate 1000 for the display device. In addition, the substrate 1000 for a display device can be provided with the bonding pins 1100 and the test electrodes 1200 by using the existing process, so as to facilitate production and manufacturing.

In some embodiments, as shown in fig. 9 and 10, a side of the second pin 1120 near the test electrode 1200 is not covered by the second conductive pattern 1400, i.e., a side of the second pin 1120 near the test electrode 1200 is exposed. In this way, in the process of manufacturing the second conductive pattern 1400 by adopting the sputtering process, the used mask plate can completely cover the test electrode 1200 and the gap between the test electrode 1200 and the bonding pin 1100, so that the material for manufacturing the second conductive pattern 1400 is prevented from being sputtered into the gap between the test electrode 1200 and the bonding pin 1100, and the pressing position of the bonding pressure head can be accurately identified in the subsequent bonding process.

Here, except for a side of the second pin 1120 near the test electrode 1200 which is not covered by the second conductive pattern 1400, the other sides of the second pin 1120 are covered by the second conductive pattern 1400.

In some embodiments, as shown in fig. 10 and 11, at least one second pin 1120 is disposed on at least one of opposite sides of the plurality of first pins 1110 along the first direction X. In this way, the plurality of first pins 1110 are distributed in a centralized manner, and the plurality of second pins 1120 are distributed in a centralized manner, so that the process difficulty is reduced, and the production and the manufacturing are facilitated.

In some embodiments, as shown in fig. 10 and 11, the substrate 1000 for a display device includes a plurality of second pins 1120, and the plurality of second pins 1120 are symmetrically disposed on opposite sides of the plurality of first pins 1110 along the first direction X. In this case, in the subsequent bonding process, the reference regions (gaps between the second pins 1120 and the corresponding test electrodes 1200) identifying the bonding positions of the bonding heads are located at opposite sides of the plurality of first pins 1110 in the first direction X, so that the accuracy of identifying the bonding positions of the bonding heads can be improved.

As shown in fig. 11, the substrate 1000 for a display device includes 4 second pins 1120, and each two second pins 1120 are symmetrically disposed on opposite sides of the plurality of first pins 1110 along the first direction X. Each side recognizes the pressing position of the binding pressure head through the gap between the two second pins 1120 and the corresponding test electrodes 1200, so that the risk of recognition errors can be reduced, and the recognition accuracy is improved; in addition, the second pins 1120 are disposed symmetrically and have the same process, which is beneficial to the subsequent monitoring of impedance.

At this time, ESD analysis is performed on the cross (see the box in fig. 13) between the first target lead 1111 and the test electrode 1200 corresponding to the first target lead 1111 and the cross (see the box in fig. 13) between the second target lead 1112 and the test electrode 1200 corresponding to the second target lead 1112, and the analysis result is shown in table 2, and no aluminum atom is present at the cross, so that micro short circuit is not generated between the first target lead 1111 and the second target lead 1112.

Wherein the first target pin 1111 is configured to transmit a supply voltage signal and the second target pin 1112 is configured to transmit a reference voltage signal.

TABLE 2

Element(s)	Line type	Apparent concentration	k ratio of	Wt％	Wt％Sifma	Standard sample label
							C	K-wire system	134.32	1.3432	81.88	0.53	C Vit
O	K-wire system	39.84	0.13406	12.11	0.34	SiO ₂
							Si	K-wire system	7	0.05548	3.45	0.27	SiO ₂
Cl	K-wire system	4.35	0.03804	2.56	0.41	NaCl

Some embodiments of the present disclosure provide a display device 100, referring to fig. 1, 3 and 6, the display device 100 includes the substrate 1000 for a display device of any of the above embodiments and a driving integrated circuit electrically connected with the plurality of bonding pins 1100 and the plurality of test electrodes 1200 of the substrate 100 for a display device.

Compared to the prior art, the display device 100 provided in the embodiment of the present disclosure has the same beneficial effects as the substrate 1000 for a display device provided in any of the embodiments described above, and will not be described herein.

The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art who is skilled in the art will recognize that changes or substitutions are within the technical scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A substrate for a display device, comprising:

a substrate;

the binding pins are arranged on the substrate; the plurality of binding pins comprise a plurality of first pins and at least one second pin, the plurality of first pins comprise a first target pin and a second target pin which are adjacently arranged, the first target pin is configured to transmit a first voltage signal, the second target pin is configured to transmit a second voltage signal, and a voltage difference exists between the first voltage signal and the second voltage signal; the second pin is configured to be in a floating state;

a plurality of test electrodes disposed on the substrate; each test electrode corresponds to one binding pin, and a gap is reserved between the test electrode and the corresponding binding pin;

a plurality of first conductive patterns, at least one first conductive pattern covering the first target pin and the test electrode corresponding to the first target pin, or covering the second target pin and the test electrode corresponding to the second target pin;

and at least one second conductive pattern which at least covers part of the second pin and has a gap between the test electrodes corresponding to the second pin.

2. The substrate for a display device according to claim 1, wherein the first target pin is configured to transmit a power supply voltage signal and the second target pin is configured to transmit a reference voltage signal.

3. The substrate for a display device according to claim 1, wherein the first target pins and the corresponding test electrodes, which are adjacently disposed, and the second target pins and the corresponding test electrodes are covered with the first conductive patterns.

4. The substrate for a display device according to claim 1, wherein the other pins except the first target pin and the second target pin among the plurality of first pins, and the corresponding test electrodes are covered with the first conductive pattern.

5. The substrate for a display device according to claim 1, wherein the plurality of bonding pins are aligned in a first direction, and the plurality of test electrodes are aligned in the first direction;

each binding pin and the corresponding test electrode are arranged in a row along a second direction, and the second direction is approximately perpendicular to the first direction.

6. The substrate for a display device according to claim 5, wherein the at least one second pin is provided on at least one of opposite sides of the plurality of first pins in the first direction.

7. The substrate for a display device according to claim 5, wherein the substrate for a display device comprises a plurality of second pins symmetrically disposed on opposite sides of the plurality of first pins in the first direction.

8. The substrate for a display device according to any one of claims 5 to 7, wherein a length of a gap between the bonding pin and the corresponding test electrode is 1.5 μm to 2.5 μm in the second direction.

9. The substrate for a display device according to claim 1, wherein a side of the second lead near the test electrode is not covered with the second conductive pattern.

10. A display device, comprising:

the substrate for a display device according to any one of claims 1 to 9;

and the driving integrated circuit is electrically connected with the plurality of binding pins and the plurality of test electrodes of the substrate for the display device.