CN113311211B - Layout connection method for improving power supply voltage detection accuracy - Google Patents
Layout connection method for improving power supply voltage detection accuracy Download PDFInfo
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- CN113311211B CN113311211B CN202010121068.0A CN202010121068A CN113311211B CN 113311211 B CN113311211 B CN 113311211B CN 202010121068 A CN202010121068 A CN 202010121068A CN 113311211 B CN113311211 B CN 113311211B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/0084—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring voltage only
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0416—Connectors, terminals
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/40—Testing power supplies
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Abstract
A layout connection method for improving the detection accuracy of the power supply voltage is characterized in that the parallel arrangement of external inlets of a power supply voltage end Vdd and/or the parallel arrangement of external inlets of a ground end Vss are carried out on the ignored wiring resistance in the power supply voltage detection circuit layout, so that the error detection caused by voltage drop of the turning current generated by the turning of a comparator CMP on the wiring resistance can be avoided, and the accurate detection of the power supply voltage Vdd is ensured.
Description
Technical Field
The invention relates to a layout connection technology for detecting the power supply voltage of a chip, in particular to a layout connection method for improving the detection accuracy of the power supply voltage.
Background
As shown in fig. 1, the circuit for accurately detecting the power supply voltage generally includes a voltage divider resistor R1 and R2 for dividing the power supply voltage Vdd to a positive input terminal (+) of the accurate comparator CMP, and a voltage Vdd (R2/(r1+r2)), and an accurate voltage reference Vref to a negative input terminal (-) of the accurate comparator CMP. When the power supply voltage Vdd reaches Vref (1+r1/R2), the output voltage Vout changes, thereby realizing accurate detection of the power supply voltage Vdd. However, the circuit for accurately detecting the power supply voltage shown in fig. 1 is only a schematic circuit diagram, and is not an actual connection condition corresponding to the layout. The link resistance and its effects are typically ignored in the layout actual link design. The inventor finds that the actual connection condition of the layout corresponding to fig. 1 is the situation shown in fig. 2 and 3 in actual work. Fig. 2 is a schematic diagram of a layout source-side interconnect circuit in the prior art based on fig. 1. Fig. 3 is a schematic diagram of a layout ground-side interconnect circuit in the prior art based on fig. 1. As shown in fig. 2, in the layout, there is a certain connection resistance Rvdd between the power supply voltage Vdd and the internal circuit. When the supply voltage Vdd rises to approximately Vref (1+r1/R2), the forward input (+) voltage of the comparator CMP approaches Vref, and the comparator CMP is ready to change the output voltage Vout from 0V to Vdd, the current of the comparator CMP increases from the quiescent current to the inversion current Icmp (the comparator CMP is often followed by some driving-capable inverters, etc., the Icmp current is larger), and the presence of Rvdd generates a voltage drop Rvdd (ir1+icmp) across the resistor (Icmp is generally much larger than the current Ir1 in the voltage dividing resistor R1, and Ir1 is ignored). The power supply voltage Vdd2 of the internal circuit is Vdd-Rvdd, vdd2 is not equal to Vdd, and thus the power supply voltage Vdd is erroneously detected. As the supply voltage increases, icmp increases, and the voltage across Rvdd increases, resulting in negative feedback from Rvdd, R1, R2, vref and comparator CMP, such that Vdd2 voltage is maintained at Vref (1+r1/R2). Until the supply voltage Vdd rises enough to provide the maximum flip current icmp_max, the comparator CMP output voltage Vout changes from 0V to Vdd, the comparator current returns to quiescent current, and the detection of the supply voltage Vdd is completed. However, the detected supply voltage is not Vref (1+R1/R2) as originally designed, but is greater than Rvdd by Icmp_max. For example rvdd=100 ohm, ivdd_max=1 mA, i.e. a voltage of 100mV more. As shown in fig. 3, similarly, there is a certain connection resistance Rvss between the ground voltage Vss and the internal circuit in the layout. When the power supply voltage Vdd approaches Vref (1+r1/R2), the current of the comparator CMP increases from the quiescent current to the inversion current Icmp, and a voltage drop rvss_icmp is generated on Rvss, and the internal circuit ground voltage Vss2 is not equal to Vss, which may have an error of rvss_icmp_max. The inventors believe that if the parallel arrangement of the external inlets of the power supply voltage terminal Vdd and/or the parallel arrangement of the external inlets of the ground terminal Vss are performed for the wiring resistance that is ignored in the power supply voltage detection circuit layout, erroneous detection caused by voltage drop of the inverting current generated when the comparator CMP inverts on the wire resistance can be avoided, thereby being beneficial to ensuring accurate detection of the power supply voltage Vdd. In view of this, the present inventors have completed the present invention.
Disclosure of Invention
Aiming at the defects or shortcomings in the prior art, the invention provides a layout connection method for improving the detection accuracy of the power supply voltage, which is beneficial to ensuring the accurate detection of the power supply voltage Vdd by carrying out parallel arrangement of external inlets of the power supply voltage terminal Vdd and/or parallel arrangement of external inlets of the ground terminal Vss on the wiring resistor ignored in the power supply voltage detection circuit layout, so that the error detection caused by voltage drop of the turning current generated by the comparator CMP when the comparator CMP turns over can be avoided.
The technical scheme of the invention is as follows:
a layout connection method for improving the detection accuracy of a power supply voltage is characterized in that parallel arrangement of external inlets of a power supply voltage terminal Vdd and/or parallel arrangement of external inlets of a ground terminal Vss are carried out on a wiring resistor which is ignored in a power supply voltage detection circuit layout, so that error detection caused by voltage drop of an overturning current Icmp generated on the wiring resistor when a comparator overturns is avoided, and accurate detection of the power supply voltage Vdd is realized.
The connecting resistor comprises a power supply pin connecting resistor Rvdd from a power supply pin of the comparator to an external inlet of the power supply voltage terminal Vdd, and an R1 power supply connecting resistor Rvdd 1 from the external inlet of the power supply voltage terminal Vdd to the first voltage dividing resistor R1, wherein a positive input end of the comparator is connected with an intermediate node of the first voltage dividing resistor R1 and the second voltage dividing resistor R2, a negative input end of the comparator is connected with a reference voltage terminal Vref, and an output end of the comparator is connected with an output voltage terminal Vout.
Rvddr1＜＜R1。
The connection resistor comprises a ground pin connection resistor rvsss from the ground pin of the comparator to the external inlet of the ground terminal Vss, and an R2 ground terminal connection resistor Rvssr2 from the external inlet of the ground terminal Vss to the second voltage dividing resistor R2.
Rvssr2＜＜R2。
The connecting resistor comprises a power supply pin connecting resistor Rvdd from a power supply pin of the comparator to an external inlet of the power supply voltage terminal Vdd, and an R1 power supply connecting resistor Rvdd 1 from the external inlet of the power supply voltage terminal Vdd to a first voltage dividing resistor R1, wherein a positive input end of the comparator is connected with an intermediate node of the first voltage dividing resistor R1 and a second voltage dividing resistor R2, a negative input end of the comparator is connected with a reference voltage terminal Vref, an output end of the comparator is connected with an output voltage terminal Vout, the connecting resistor comprises a ground pin connecting resistor Rvss from a ground pin of the comparator to an external inlet of the ground terminal Vss, and R2 ground terminal connecting resistors Rvssr2, rvddr1 < R1, rvdsr 2 < R2, and a positive input end voltage of the comparator is=vdd (R2/(R1+R2)), vdd=Vss 1+R2.
The invention has the following technical effects: in the layout, a power line of R1 and a ground line of R2 are independently connected to external Vdd and Vss inlets and are not connected with circuits such as a comparator with turning current. In this way, the power line of R1 has a certain wiring resistance Rvddr1, but as long as the resistance is far smaller than R1 and the ground resistance Rvssr2 of R2 is far smaller than R2, the forward voltage of the comparator is still Vdd (R2/(r1+r2)), and the voltage is not affected by the flip current when the comparator is flipped, so that the power voltage Vref (1+r1/R2) can be accurately detected.
Compared with the prior art that the voltage dividing resistor of the power supply is connected with circuits such as a comparator with overturning current, and the like, the detected power supply voltage has the error of the product of the overturning current and the line resistance, so that the power supply voltage detection is inaccurate.
Drawings
Fig. 1 is a schematic diagram of a circuit structure for accurately detecting a power supply voltage in the prior art. In fig. 1, a positive input terminal (+) of a comparator CMP (accurate comparator) is connected to a power supply voltage terminal Vdd through a first resistor R1, a negative input terminal (-) of the CMP is connected to a reference voltage terminal Vref (accurate voltage reference or reference voltage) through a second resistor R2, an output terminal of the CMP is an output voltage terminal Vout, a power supply pin of the CMP is connected to the power supply voltage terminal Vdd, a ground pin of the CMP is connected to the ground terminal Vss, R1 and R2 are voltage dividing resistors, and an input voltage VCMP (+) of the CMP (+) is=vdd (R2/(r1+r2)), so that when Vdd reaches Vref (1+r1/R2), vout changes, thereby realizing accurate detection of the power supply voltage.
Fig. 2 is a schematic diagram of a layout source-side interconnect circuit in the prior art based on fig. 1. In fig. 2, R1 and the power pin of CMP are connected to Vdd after forming a connection node, which generates a source terminal connection resistor Rvdd between the connection node and Vdd, the voltage drop generated by the current (ir1+icmp) flowing through Rvdd on Rvdd is Rvdd (ir1+icmp), ir1 is the current flowing through the voltage dividing resistor R1, and Icmp is the current flowing into the power pin of CMP. Since Icmp > Ir1, the internal circuit supply voltage Vdd2 (i.e., the connection node voltage or the detected supply voltage) =vdd-Rvdd Icmp, and therefore Vdd2 +..
Fig. 3 is a schematic diagram of a layout ground-side interconnect circuit in the prior art based on fig. 1. Similar to fig. 2, the internal circuit ground voltage Vss2 in fig. 3 is not equal to Vss, and there is an error in Rvss icmp_max. In fig. 3, the voltage dividing resistor R2 and the ground leg of CMP are connected to Vss after forming a connection node, so that Rvss generates a ground connection resistor Rvss between the connection nodes (Vss 2) and Vss, and a voltage drop generated by the current Icmp flowing through Rvss on Rvss is rvss×icmp.
Fig. 4 is a schematic diagram of a circuit structure corresponding to a layout connection method for improving the accuracy of power supply voltage detection. In fig. 4, the voltage dividing resistor R1 and the power pin of CMP are each independently connected to the external inlet of the power voltage terminal Vdd, and the voltage dividing resistor R2 and the leg of CMP are each independently connected to the external inlet of the ground terminal Vss. Thus, although there are the R1 power supply connection resistor Rvddr1 and the R2 ground connection resistor Rvssr2, rvddr1 < R1, rvssr2 < R2), the input voltage VCMP (+) of CMP (+) is not affected by the flip current when the comparator CMP is flipped (R2/(R1+R2)), and the power supply voltage Vdd can be accurately detected as Vref (1+R1/R2).
The reference numerals are listed below: vdd-supply voltage or supply voltage terminal; vss-ground or ground voltage; vout-output voltage terminal or output voltage; vref—reference voltage terminal or reference voltage or precision voltage reference or reference voltage; a CMP-comparator; the Icmp-comparator toggles the current or current flowing into the CMP power pin; ir 1-a first resistive current; vdd 2-internal circuit supply voltage; vss 2-internal circuit ground voltage; r1 is a first resistor (or a first voltage dividing resistor); r2-a second resistor (or a second voltage divider resistor); rvdd-source terminal or power pin connection resistor; rvss-ground or foot link resistance; rvdd 1-R1 power supply wiring resistance; rvssr2-R2 ground connects the resistor.
Detailed Description
The invention will be described with reference to the accompanying drawings (fig. 1-4).
Fig. 4 is a schematic diagram of a circuit structure corresponding to a layout connection method for improving the accuracy of power supply voltage detection. The inventors have also made an analysis of the related art technology with reference to fig. 1 to 3 in order to correctly understand the inventive point of the present invention. As shown in fig. 4, in a layout connection method for improving the accuracy of power supply voltage detection, parallel arrangement of external inlets of a power supply voltage terminal Vdd and/or parallel arrangement of external inlets of a ground terminal Vss are performed on a wire resistor (for example, a source terminal wire resistor Rvdd or a ground terminal wire resistor Rvss in fig. 2 to 3) which is ignored in a power supply voltage detection circuit layout, so as to avoid error detection caused by voltage drop of a flip current Icmp generated when a comparator CMP is flipped, thereby realizing accurate detection of the power supply voltage Vdd. The connecting resistor comprises a power supply pin connecting resistor Rvdd from a power supply pin of the comparator CMP to an external inlet of the power supply voltage terminal Vdd, and an R1 power supply connecting resistor Rvdd 1 from the external inlet of the power supply voltage terminal Vdd to the first voltage dividing resistor R1, wherein a positive input terminal (+) of the comparator CMP is connected with an intermediate node of the first voltage dividing resistor R1 and the second voltage dividing resistor R2, a negative input terminal (-) of the comparator CMP is connected with a reference voltage terminal Vref, and an output terminal of the comparator CMP is connected with an output voltage terminal Vout. Rvddr1 < R1. The connection resistor includes a ground connection resistor rvsss from a ground of the comparator CMP to an external inlet of the ground Vss, and an R2 ground connection resistor Rvssr2 from the external inlet of the ground Vss to the second voltage dividing resistor R2.Rvssr2 < R2), the positive input voltage of the comparator=vdd (R2/(r1+r2)), vdd=vref (1+r1/R2). In fig. 4, the voltage dividing resistor R1 and the power pin of CMP are each independently connected to the external inlet of the power voltage terminal Vdd, and the voltage dividing resistor R2 and the leg of CMP are each independently connected to the external inlet of the ground terminal Vss. Thus, although there are the R1 power supply connection resistor Rvddr1 and the R2 ground connection resistor Rvssr2, rvddr1 < R1, rvssr2 < R2), the input voltage VCMP (+) of CMP (+) is not affected by the flip current when the comparator CMP is flipped (R2/(R1+R2)), and the power supply voltage Vdd can be accurately detected as Vref (1+R1/R2). Therefore, when the power supply voltage Vdd reaches Vref (1+r1/R2), the output voltage Vout changes, and accurate detection of the power supply voltage Vdd is truly realized.
It is noted that the above description is helpful for a person skilled in the art to understand the present invention, but does not limit the scope of the present invention. Any and all such equivalent substitutions, modifications and/or deletions as may be made without departing from the spirit and scope of the invention.
Claims (4)
1. A layout connection method for improving the detection accuracy of the power supply voltage is characterized in that the parallel arrangement of the external inlets of a power supply voltage end Vdd is carried out on the ignored wiring resistor in the power supply voltage detection circuit layout, and the parallel arrangement of the external inlets of a ground end Vss is carried out, so that the error detection caused by the voltage drop of the overturning current Icmp generated when a comparator overturns on the wiring resistor is avoided, and the accurate detection of the power supply voltage Vdd is realized;
the connecting resistor comprises a power supply pin connecting resistor Rvdd from a power supply pin of the comparator to an external inlet of the power supply voltage terminal Vdd, and an R1 power supply connecting resistor Rvdd 1 from the external inlet of the power supply voltage terminal Vdd to a first voltage dividing resistor R1, wherein a positive input end of the comparator is connected with an intermediate node of the first voltage dividing resistor R1 and a second voltage dividing resistor R2, a negative input end of the comparator is connected with a reference voltage terminal Vref, and an output end of the comparator is connected with an output voltage terminal Vout;
the connection resistor comprises a ground pin connection resistor rvsss from the ground pin of the comparator to the external inlet of the ground terminal Vss, and an R2 ground terminal connection resistor Rvssr2 from the external inlet of the ground terminal Vss to the second voltage dividing resistor R2.
2. The layout connection method for improving the detection accuracy of a power supply voltage according to claim 1, wherein Rvddr1 < R1.
3. The layout connection method for improving the detection accuracy of the power supply voltage according to claim 1, wherein Rvssr2 < R2.
4. The layout connection method for improving the detection accuracy of a power supply voltage according to claim 1, wherein Rvddr1 < R1 and Rvssr2 < R2, the positive input terminal voltage of the comparator=vdd (R2/(r1+r2)), vdd=vref (1+r1/R2).
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| CN202010121068.0A CN113311211B (en) | 2020-02-26 | 2020-02-26 | Layout connection method for improving power supply voltage detection accuracy |
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| CN202010121068.0A CN113311211B (en) | 2020-02-26 | 2020-02-26 | Layout connection method for improving power supply voltage detection accuracy |
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| CN113311211B true CN113311211B (en) | 2023-05-30 |
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| JPH09243673A (en) * | 1996-03-05 | 1997-09-19 | Nippon Telegr & Teleph Corp <Ntt> | Signal level detection circuit |
| JP2000341095A (en) * | 1999-05-27 | 2000-12-08 | Ntt Data Corp | Comparator circuit |
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| JP2013036744A (en) * | 2011-08-03 | 2013-02-21 | Fuji Electric Co Ltd | Power supply voltage detection circuit |
| CN103605395A (en) * | 2013-10-30 | 2014-02-26 | 徐州市恒源电器有限公司 | Self-compensating line loss circuit |
| JP2014062825A (en) * | 2012-09-21 | 2014-04-10 | Asahi Kasei Electronics Co Ltd | Voltage detection circuit, and voltage detection method |
| CN104280590A (en) * | 2013-07-12 | 2015-01-14 | 上海华虹宏力半导体制造有限公司 | Voltage detection circuit applied to quick disconnection of power source |
| CN105892553A (en) * | 2016-05-06 | 2016-08-24 | 芯原微电子(上海)有限公司 | Power supply voltage electrification detection circuit and achieving method for electrification detection |
| CN107515328A (en) * | 2016-06-15 | 2017-12-26 | 中芯国际集成电路制造(上海)有限公司 | The detection circuit and detection method of voltage generating unit |
| CN109861674A (en) * | 2019-04-09 | 2019-06-07 | 深圳市万微微电子技术有限公司 | A kind of realization circuit of high-precision absolute voltage comparator |
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2020
- 2020-02-26 CN CN202010121068.0A patent/CN113311211B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09243673A (en) * | 1996-03-05 | 1997-09-19 | Nippon Telegr & Teleph Corp <Ntt> | Signal level detection circuit |
| JP2000341095A (en) * | 1999-05-27 | 2000-12-08 | Ntt Data Corp | Comparator circuit |
| CN2483732Y (en) * | 2001-06-04 | 2002-03-27 | 深圳市科陆电子科技股份有限公司 | Current and voltage conversion device with low temp. coefficient |
| JP2013036744A (en) * | 2011-08-03 | 2013-02-21 | Fuji Electric Co Ltd | Power supply voltage detection circuit |
| JP2014062825A (en) * | 2012-09-21 | 2014-04-10 | Asahi Kasei Electronics Co Ltd | Voltage detection circuit, and voltage detection method |
| CN104280590A (en) * | 2013-07-12 | 2015-01-14 | 上海华虹宏力半导体制造有限公司 | Voltage detection circuit applied to quick disconnection of power source |
| CN103605395A (en) * | 2013-10-30 | 2014-02-26 | 徐州市恒源电器有限公司 | Self-compensating line loss circuit |
| CN105892553A (en) * | 2016-05-06 | 2016-08-24 | 芯原微电子(上海)有限公司 | Power supply voltage electrification detection circuit and achieving method for electrification detection |
| CN107515328A (en) * | 2016-06-15 | 2017-12-26 | 中芯国际集成电路制造(上海)有限公司 | The detection circuit and detection method of voltage generating unit |
| CN109861674A (en) * | 2019-04-09 | 2019-06-07 | 深圳市万微微电子技术有限公司 | A kind of realization circuit of high-precision absolute voltage comparator |
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| CN113311211A (en) | 2021-08-27 |
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