CN113300679B - Digital predistortion circuit, digital predistortion coefficient acquisition method and related device - Google Patents
Digital predistortion circuit, digital predistortion coefficient acquisition method and related device Download PDFInfo
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Abstract
The application discloses a digital predistortion circuit, a digital predistortion coefficient acquisition method and a related device, wherein the circuit comprises: the digital predistortion DPD module, the power amplifier, the signal recovery circuit and the band-limited DPD coefficient extraction circuit, wherein an output signal of the DPD module is input to the power amplifier, an output signal of the power amplifier is input to the signal recovery circuit, an output signal of the signal recovery circuit is input to the band-limited DPD coefficient extraction circuit, and an output signal of the band-limited DPD coefficient extraction circuit is input to the DPD module; and the band-limited DPD coefficient extraction circuit is used for determining the DPD coefficient according to the output signal of the signal recovery circuit and the first input signal, wherein the first input signal comprises the input signal of the DPD module or the output signal of the DPD module, the DPD coefficient can be extracted through the band-limited DPD coefficient extraction circuit, the bandwidth during DPD coefficient extraction is reduced, and the power consumption during DPD coefficient extraction is reduced.
Description
Technical Field
The present disclosure relates to the field of communications, and in particular, to a digital predistortion circuit, a digital predistortion coefficient acquisition method, and a related apparatus.
Background
With the rapid development of 5G technology, the frequency band of the signal is expanded to millimeter waves, and when the signal is transmitted, nonlinear distortion of the in-band signal is caused due to the fact that the power amplifier works in a nonlinear region, and when the nonlinear distortion of the in-band signal is solved, digital predistortion processing is usually performed on the signal to adjust the nonlinear distortion of the in-band signal. In the existing Digital predistortion system (DPD), the feedback channel of the system generally needs more than 5 times of bandwidth of the output signal of the power amplifier to restore the signal, and when the DPD coefficient is extracted, more than 5 times of bandwidth of the output signal of the power amplifier is generally consumed, resulting in larger power consumption when the DPD coefficient is extracted.
Disclosure of Invention
The embodiment of the application provides a digital predistortion circuit, a digital predistortion coefficient acquisition method and a related device, which can extract a DPD coefficient through a band-limited DPD coefficient extraction circuit, and reduce the bandwidth when the DPD coefficient is extracted, thereby reducing the power consumption when the DPD coefficient is extracted.
In a first aspect, embodiments of the present application provide a digital predistortion circuit comprising: a digital predistortion DPD module, a power amplifier, a signal recovery circuit and a band limited DPD coefficient extraction circuit, wherein,
The output signal of the digital predistortion DPD module is input to a power amplifier, the output signal of the power amplifier is input to a signal recovery circuit, the output signal of the signal recovery circuit is input to a band-limited DPD coefficient extraction circuit, and the output signal of the band-limited DPD coefficient extraction circuit is input to the digital predistortion DPD module;
and the band-limited DPD coefficient extraction circuit is used for determining the DPD coefficient according to the output signal of the signal recovery circuit and a first input signal, wherein the first input signal comprises an input signal of the digital predistortion DPD module or an output signal of the digital predistortion DPD module.
In the embodiment of the application, the band-limited DPD coefficient extraction circuit performs DPD coefficient extraction according to the output signal of the signal recovery circuit, the input signal of the digital predistortion DPD module and the output signal of the digital predistortion DPD module, so that compared with the conventional scheme in which the DPD coefficient is extracted by using more than 5 times of the bandwidth of the output signal of the power amplifier, the band-limited DPD coefficient extraction circuit is capable of performing band-limited DPD coefficient extraction, and therefore the power consumption during DPD coefficient extraction can be reduced.
With reference to the first aspect, in one possible implementation manner, the signal recovery circuit includes a multiplier, a spread spectrum signal generator, a pre-band limiting filter, and a signal restorer, where,
The input signal of the multiplier comprises the output signal of the power amplifier and the output signal of the spread spectrum signal generator, the output signal of the multiplier is input to the pre-band-limit filter, the output signal of the pre-band-limit filter is input to the signal restorer, and the output signal of the signal restorer is input to the band-limit DPD coefficient extraction circuit.
In this example, the spread spectrum signal may be filtered by the pre-band-limiting filter to obtain a filtered band-limited signal, and when the signal restorer adopts the band-limited signal to restore the signal, it is not necessary to restore the signal by several times of the bandwidth of the output signal of the power amplifier, so that the energy consumption during signal restoration is reduced.
With reference to the first aspect, in a possible implementation manner, the circuit further includes an analog-to-digital converter, and the output signal of the pre-band-limiting filter is input to the signal restorer through the analog-to-digital converter.
With reference to the first aspect, in one possible implementation manner, the band-limited DPD coefficient extracting circuit includes an adder and a band-limited DPD coefficient extractor, where,
the input signal of the adder comprises an output signal of the digital predistortion DPD module and a first output signal of the band-limited DPD coefficient extractor, the output signal of the adder is input to the band-limited DPD coefficient extractor, a second output signal of the band-limited DPD coefficient extractor is input to the digital predistortion DPD module, and an output signal of the signal restorer is input to the band-limited DPD coefficient extractor;
And the band-limited DPD coefficient extractor is used for determining the DPD coefficient according to the output signal of the adder and the output signal of the signal restorer.
With reference to the first aspect, in one possible implementation manner, the band-limited DPD coefficient extracting circuit includes an adder and a band-limited DPD coefficient extractor, where,
the input signal of the adder comprises the input signal of the digital predistortion DPD module and the output signal of the signal restorer, the output signal of the adder is input to the band-limit DPD coefficient extractor, and the output signal of the band-limit DPD coefficient extractor is input to the digital predistortion DPD module;
and the band-limited DPD coefficient extractor is used for determining the DPD coefficient according to the output signal of the adder.
With reference to the first aspect, in one possible implementation manner, the analog-to-digital converter includes a low-speed analog-to-digital converter.
In the example, by adopting the low-speed analog-to-digital converter, compared with the prior art that the signal is sampled by adopting the high-speed analog-to-digital converter, the difficulty in circuit realization can be reduced, and meanwhile, the energy consumption required in sampling can be reduced.
With reference to the first aspect, in one possible implementation manner, the pre-band-limiting filter includes a low-pass filter, a high-pass filter, or a band-pass filter.
With reference to the first aspect, in one possible implementation manner, the circuit further includes a coupler, and an output signal of the power amplifier is input to the signal recovery circuit through the coupler.
In this example, when the output signal of the power amplifier is input to the signal recovery circuit through the coupler, part of energy can be coupled to the signal recovery circuit, so that signal coupling can be performed according to the requirement of the signal recovery circuit, and the practicability of the digital predistortion circuit is improved.
With reference to the first aspect, in one possible implementation manner, the circuit further includes a digital-to-analog converter, and the output signal of the digital predistortion DPD module is input to the power amplifier through the digital-to-analog converter.
In a second aspect, an embodiment of the present application provides a method for obtaining a digital predistortion coefficient, which is characterized in that the method is applied to a digital predistortion circuit, the circuit includes a digital predistortion DPD module, a power amplifier, a signal recovery circuit and a band-limited DPD coefficient extraction circuit, and the method includes:
the digital predistortion DPD module carries out nonlinear correction on the input signal to obtain an output signal of the digital predistortion DPD module;
amplifying the output signal of the digital predistortion DPD module by a power amplifier to obtain an output signal of the power amplifier;
the signal recovery signal circuit recovers the output signal of the power amplifier to obtain the output signal of the signal recovery signal circuit;
The band-limited DPD coefficient extraction circuit determines a DPD coefficient according to an output signal of the signal recovery signal circuit and a first input signal, and inputs the output signal including the DPD coefficient to the digital predistortion DPD module, the first input signal including an input signal of the digital predistortion DPD module or an output signal of the digital predistortion DPD module.
With reference to the second aspect, in one possible implementation manner, the signal recovery circuit includes a multiplier, a spread spectrum signal generator, a pre-band limiting filter, and a signal recovery unit, the signal recovery signal circuit recovers an output signal of the power amplifier to obtain an output signal of the signal recovery signal circuit includes:
the multiplier performs multiplication operation on the output signal of the power amplifier and the output signal of the spread spectrum signal generator to obtain an output signal of the multiplier;
the pre-band limiting filter filters the output signal of the multiplier to obtain a narrow-band signal;
the signal restorer restores according to the narrowband signal to obtain a restored signal, and inputs the restored signal to the band-limited DPD coefficient extraction circuit.
With reference to the second aspect, in one possible implementation manner, the circuit further includes an analog-to-digital converter, and the analog-to-digital converter performs analog-to-digital conversion on the narrowband signal to obtain a digital signal, and inputs the digital signal to the signal restorer.
With reference to the second aspect, in one possible implementation manner, the band-limited DPD coefficient extracting circuit includes an adder and a band-limited DPD coefficient extractor, the first input signal is an output signal of the digital predistortion DPD module, and determining the DPD coefficient by the band-limited DPD coefficient extracting circuit according to the output signal of the signal recovering circuit and the first input signal includes:
the adder performs addition operation according to the output signal of the digital predistortion DPD module and the first output signal of the band-limited DPD coefficient extractor to obtain an output signal of the adder;
a band-limited DPD coefficient extractor determines DPD coefficients from the output signal of the adder and the output signal of the signal restorer.
With reference to the second aspect, in one possible implementation manner, the band-limited DPD coefficient extracting circuit includes an adder and a band-limited DPD coefficient extractor, the first input signal is an input signal of the digital predistortion DPD module, and the band-limited DPD coefficient extracting circuit determines a DPD coefficient according to an output signal of the signal recovering circuit and the first input signal, and includes:
the adder performs addition operation according to the input signal of the digital predistortion DPD module and the first output signal of the band-limited DPD coefficient extractor to obtain an output signal of the adder;
A band-limited DPD coefficient extractor determines DPD coefficients from the output signal of the adder.
With reference to the second aspect, in one possible implementation manner, the analog-to-digital converter includes a low-speed analog-to-digital converter.
With reference to the second aspect, in one possible implementation manner, the pre-band-limiting filter includes a low-pass filter, a high-pass filter, or a band-pass filter.
With reference to the second aspect, in one possible implementation manner, the circuit further includes a coupler, and an output signal of the power amplifier is input to the signal recovery circuit through the coupler.
With reference to the second aspect, in one possible implementation manner, the circuit further includes a digital-to-analog converter, and the output signal of the digital predistortion DPD module is input to the power amplifier through the digital-to-analog converter.
In a third aspect, embodiments of the present application provide a transmitter comprising an antenna and a digital predistortion circuit as in any of the first aspects above.
In a fourth aspect, embodiments of the present application provide a chip system including a processor for supporting a digital predistortion circuit to implement a method as in any of the second aspects.
In a fifth aspect, embodiments of the present application provide a computer readable storage medium, wherein the computer readable storage medium stores a computer program comprising program instructions that, when executed by a processor, cause the processor to perform a method according to any of the second aspects.
These and other aspects of the present application will be more readily apparent from the following description of the embodiments.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a digital predistortion circuit according to an embodiment of the present application;
FIG. 2A is a schematic diagram of another digital predistortion circuit in accordance with an embodiment of the present application;
FIG. 2B is a schematic diagram of another digital predistortion circuit according to an embodiment of the present application;
FIG. 3A is a schematic diagram of another digital predistortion circuit according to an embodiment of the present application;
FIG. 3B is a schematic diagram of another digital predistortion circuit according to an embodiment of the present application;
FIG. 4A is a schematic diagram of another digital predistortion circuit according to an embodiment of the present application;
FIG. 4B is a schematic diagram of another digital predistortion circuit according to an embodiment of the present application;
Fig. 5 is a schematic flow chart of a method for obtaining a digital predistortion coefficient according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of a chip system according to the present application.
Detailed Description
Embodiments of the present application are described below with reference to the accompanying drawings.
The specific structure of the digital predistortion circuit is described in detail below. The digital predistortion circuit provided by the application aims at solving the problem that the power consumption of the digital predistortion circuit is large because the bandwidth of an output signal of a power amplifier is required to be several times when DPD coefficients are extracted in the existing scheme, and DPD coefficients are extracted through a band-limited DPD coefficient extraction circuit in the digital predistortion circuit without the need of several times of the bandwidth of the output signal of the power amplifier so as to reduce the power consumption of the digital predistortion circuit.
Fig. 1 is a schematic structural diagram of a digital predistortion circuit according to an embodiment of the present application. As shown in fig. 1, the digital predistortion circuit includes: a digital predistortion DPD module 110, a power amplifier PA120, a signal recovery circuit 130 and a band limited DPD coefficient extraction circuit 140, wherein,
the output signal of the digital predistortion DPD module 110 is input to the power amplifier PA120, the output signal of the power amplifier PA120 is input to the signal recovery circuit 130, the output signal of the signal recovery circuit 130 is input to the band-limited DPD coefficient extraction circuit 140, and the output signal of the band-limited DPD coefficient extraction circuit 140 is input to the digital predistortion DPD module 110;
The band-limited DPD coefficient extracting circuit 140 is configured to determine a DPD coefficient according to the output signal of the signal restoring circuit 130 and a first input signal, where the first input signal includes an input signal of the digital predistortion DPD module 110 or an output signal of the digital predistortion DPD module 110.
The signal recovery circuit 130 is configured to perform signal recovery according to the output signal of the power amplifier, so as to obtain a recovered signal, where the recovered signal is a digital signal.
After receiving the DPD coefficients output by the band-limited DPD coefficient extracting circuit 140, the digital predistortion DPD module 110 completes nonlinear predistortion in the digital domain.
The above-described signal recovery circuit 130 and band-limited DPD coefficient extraction circuit 140 may also be referred to as a feedback channel.
In one possible embodiment, as shown in fig. 2A, the signal recovery circuit 130 includes a multiplier 131, a spread spectrum signal generator 132, a pre-band limiting filter 133, and a signal restorer 134, wherein,
the input signal of the multiplier 131 includes the output signal of the power amplifier PA120 and the output signal of the spread spectrum signal generator 132, the output signal of the multiplier 131 is input to the pre-band-limit filter 133, the output signal of the pre-band-limit filter 133 is input to the signal restorer 134, and the output signal of the signal restorer 134 is input to the band-limit DPD coefficient extraction circuit 140.
A multiplier 131 for mixing an output signal of the power amplifier and an output signal of the spread spectrum signal generator to obtain a spread spectrum signal;
the pre-band limiting filter 133 is configured to filter the spread spectrum signal output by the multiplier 131 to obtain a narrowband signal with a preset bandwidth. The preset bandwidth can be set according to the performance requirement when the DPD coefficient is extracted, for example, when the performance requirement is precision, the precision can be understood as the accuracy, the larger the preset bandwidth is, the higher the precision is, and the smaller the preset bandwidth is, the lower the precision is. The narrowband signal is a sub-segment of the spread-spectrum wideband signal in the frequency domain, the sub-segment spectrum reflecting the information characteristic of the output signal of the power amplifier PA 120.
The signal recovery circuit 134 is configured to perform signal recovery on the narrowband signal output by the pre-band limiting filter 133, so as to obtain a recovered signal, where the recovered signal is a digital signal.
In one possible embodiment, the pre-band-limiting filter comprises a low-pass filter, a high-pass filter, or a band-pass filter.
In one possible embodiment, the power amplifier may be a digital power amplifier or an analog power amplifier, and if the power amplifier is a digital power amplifier, the signal recovery circuit recovers the digital signal, and if the power amplifier is an analog power amplifier, the signal recovery circuit recovers the analog signal.
When the power amplifier is an analog power amplifier, the digital predistortion circuit may further include an analog-to-digital converter, and the output signal of the pre-band-limited filter is input to the signal restorer through the analog-to-digital converter, which may specifically be: the analog-to-digital converter is used for performing analog-to-digital conversion on the output signal of the pre-band-limit filter to obtain an analog signal, and inputting the analog signal to the signal restorer. The analog-to-digital converter may be a low-speed analog-to-digital converter, which may be understood as a lower sampling rate analog-to-digital converter. The low-speed analog-to-digital converter is adopted to carry out analog-to-digital conversion on the signal, and then the signal can be sampled at a lower sampling rate, so that the adoption of multiple times of the bandwidth of the output signal of the power amplifier is not needed, the energy consumption is reduced, the implementation difficulty is reduced, and the practicability is improved.
The digital predistortion circuit may further comprise a digital-to-analog converter for converting the output signal of the digital predistortion DPD module to an analog signal and inputting the analog signal to the power amplifier. The above-mentioned digital-to-analog converter and the setting manner of the analog-to-digital converter can be seen from fig. 2B, in fig. 2B, the input signal of the digital-to-analog converter 150 is the output signal of the DPD module 110, and the output signal of the digital-to-analog converter 150 is input to the power amplifier PA120; the input signal of the analog-to-digital converter 135 is the output signal of the pre-band-limit filter 133, and the output signal of the analog-to-digital converter 135 is input to the signal restorer 134.
In one possible embodiment, the output signal of the spread spectrum signal generator 132 may also be output to the signal restorer 134 for restoration by the signal restorer 134. The signal restorer can restore the signal according to the input signal by a signal restoration algorithm or a frequency spectrum extrapolation algorithm in the compressed sensing algorithm, and the like, so as to obtain the restored signal.
In one possible embodiment, as shown in fig. 3A, the band limited DPD coefficient extraction circuit 140 includes an adder 141 and a band limited DPD coefficient extractor 142, where,
the input signal of the adder 141 includes the output signal of the digital predistortion DPD module 110 and the first output signal of the band-limited DPD coefficient extractor 142, the output signal of the adder 141 is input to the band-limited DPD coefficient extractor 142, the second output signal of the band-limited DPD coefficient extractor 142 is input to the digital predistortion DPD module 110, and the output signal of the signal restorer 130 is input to the band-limited DPD coefficient extractor 142;
a band-limited DPD coefficient extractor 142 for determining DPD coefficients from the output signal of the adder 141 and the output signal of the signal restorer 130.
In one possible embodiment, as shown in fig. 3B, the band limited DPD coefficient extraction circuit 140 includes an adder 141 and a band limited DPD coefficient extractor 142, where,
The input signal of the adder 141 includes the input signal of the digital predistortion DPD module 110 and the output signal of the signal restorer 130, the output signal of the adder 141 is input to the band-limited DPD coefficient extractor 142, and the output signal of the band-limited DPD coefficient extractor 142 is input to the digital predistortion DPD module 110;
a band-limited DPD coefficient extractor 142 for determining DPD coefficients from the output signal of the adder 141.
In one possible embodiment, as shown in fig. 4A and 4B, the digital predistortion circuit further includes a coupler 160, and the output signal of the PA120 is input to the signal recovery circuit 130 through the coupler 160, specifically, the output signal of the PA120 is coupled to the coupling port according to a preset ratio, which is: the output signal of the power amplifier PA120 couples part of the energy to the signal recovery circuit 130.
The modules or circuits included in the signal recovery circuit and the band-limited DPD coefficient extraction circuit in the above embodiments may be divided into other forms, and are merely illustrated herein, for example, the spread spectrum signal generator in the signal recovery circuit may be a sub-device in the band-limited DPD coefficient extraction circuit, and when the spread spectrum signal generator is a sub-device in the band-limited DPD coefficient extraction circuit, it cannot be a sub-device in the signal recovery circuit.
Referring to fig. 5, fig. 5 provides a flowchart of a digital predistortion coefficient acquisition method. As shown in fig. 5, the digital predistortion coefficient acquisition method is applied to a digital predistortion circuit, which is a circuit shown in any one of the embodiments of fig. 1 to 4B and includes a digital predistortion DPD module, a power amplifier, a signal recovery circuit and a band limited DPD coefficient extraction circuit, and includes the steps of:
s510, the digital predistortion DPD module carries out nonlinear correction on the input signal to obtain an output signal of the digital predistortion DPD module.
When the digital predistortion DPD module corrects an input signal, the input signal needs to be corrected by the DPD coefficient, that is, after the digital predistortion circuit determines the DPD coefficient, the input signal is corrected in a nonlinear manner.
S502, amplifying the output signal of the digital predistortion DPD module by the power amplifier to obtain an output signal of the power amplifier.
The power amplifier may operate in a nonlinear region when amplifying the output signal of the digital predistortion DPD module.
The power amplifier may be an analog power amplifier or a digital power amplifier.
S503, the signal recovery signal circuit recovers the output signal of the power amplifier to obtain the output signal of the signal recovery signal circuit.
The output signal of the signal recovery circuit comprises a digital signal.
S504, a band-limited DPD coefficient extraction circuit determines a DPD coefficient according to an output signal of a signal recovery circuit and a first input signal, wherein the first input signal comprises an input signal of the digital predistortion DPD module or an output signal of the digital predistortion DPD module, and the output signal comprising the DPD coefficient is input to the digital predistortion DPD module.
After receiving the DPD coefficient, the digital predistortion DPD module corrects the input signal according to the DPD coefficient to obtain a corrected signal, and the nonlinear distortion of the corrected signal is lower than the nonlinear distortion of the output signal amplified by the power amplifier.
In one possible embodiment, the signal recovery circuit includes a multiplier, a spread spectrum signal generator, a pre-band limiting filter and a signal restorer, when the signal recovery signal circuit restores the output signal of the power amplifier to obtain the output signal of the signal recovery signal circuit, the following method may be specifically adopted:
a1, multiplying the output signal of the power amplifier and the output signal of the spread spectrum signal generator by a multiplier to obtain the output signal of the multiplier;
The output signal of the power amplifier and the output signal of the spread spectrum signal generator are multiplied to obtain the output signal of the multiplier, which may also become to mix the output signal of the power amplifier. The output signal of the multiplier is a broadband signal.
A2, filtering the output signal of the multiplier by a pre-band-limit filter to obtain a narrow-band signal;
the bandwidth of the narrowband signal can be set according to the performance requirement when the DPD coefficient is extracted, for example, when the performance requirement is precision, the precision can be understood as the precision, the larger the preset bandwidth is, the higher the precision is, and the smaller the preset bandwidth is, the lower the precision is.
And A3, the signal restorer restores according to the narrowband signal to obtain a restored signal, and the restored signal is input to the band-limit DPD coefficient extraction circuit.
The signal restorer can restore the signal according to the input signal by a signal restoration algorithm or a frequency spectrum extrapolation algorithm in the compressed sensing algorithm, and the like, so as to obtain the restored signal.
In a possible embodiment, the circuit further comprises an analog-to-digital converter that analog-to-digital converts the narrowband signal to obtain a digital signal and inputs the digital signal to the signal restorer.
In one possible embodiment, the band-limited DPD coefficient extracting circuit includes an adder and a band-limited DPD coefficient extractor, and when the first input signal is an output signal of the digitally pre-distorted DPD module, the method for determining the DPD coefficients may be:
b1, an adder performs addition operation according to an output signal of the digital predistortion DPD module and a first output signal of the band limit DPD coefficient extractor to obtain an output signal of the adder;
b2, a band-limited DPD coefficient extractor determines the DPD coefficient according to the output signal of the adder and the output signal of the signal restorer.
When the band-limited DPD coefficient extractor root determines the DPD coefficients, the DPD coefficients may be determined by an algorithm according to a preset nonlinear model. For example, a power amplifier is modeled with a polynomial, and the mathematical model is as follows:
wherein the method comprises the steps of ， a km Is the DPD coefficient (which may also be referred to as a non-linearity parameter), K is the non-linearity, K is the order of the non-linearity upon which the power amplifier is modeled, M is the memory depth value, and M is the maximum value of the memory depth of the power amplifier model.
In one possible embodiment, the band-limited DPD coefficient extracting circuit includes an adder and a band-limited DPD coefficient extractor, the first input signal is an input signal of a digital predistortion DPD module, and the method of determining DPD coefficients includes:
C1, an adder performs addition operation according to an input signal of the digital predistortion DPD module and a first output signal of the band limit DPD coefficient extractor to obtain an output signal of the adder;
and C2, determining the DPD coefficients by a band-limited DPD coefficient extractor according to the output signal of the adder.
When determining the DPD coefficient according to the output signal of the adder, the error value between the input signals of the first output signal digital predistortion DPD module of the band-limited DPD coefficient extractor may be specifically the value corresponding to the minimization. The error minimization may be determined based on different requirements, which may correspond to different error minimization values.
In one possible embodiment, the analog-to-digital converter comprises a low-speed analog-to-digital converter.
In one possible embodiment, the pre-band-limiting filter comprises a low-pass filter, a high-pass filter, or a band-pass filter.
In one possible embodiment, the digital predistortion circuit further comprises a coupler through which the output signal of the power amplifier is input to the signal recovery circuit.
In one possible embodiment, the circuit further comprises a digital-to-analog converter through which the output signal of the digital predistortion DPD module is input to the power amplifier.
The specific circuit structure of the digital predistortion circuit in the above method is referred to the circuit shown in any one of the embodiments of fig. 1 to 4B in the foregoing embodiments, and will not be described herein.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a chip system provided in the present application. As shown in fig. 6, the chip system 600 may include: a processor 610, and one or more interfaces 620 coupled to the processor 610. Exemplary:
the processor 610 may be used to read and execute computer readable instructions. In particular implementations, processor 610 may include primarily controllers, operators, and registers. Illustratively, the controller is primarily responsible for instruction decoding and issues control signals for the operations to which the instructions correspond. The arithmetic unit is mainly responsible for performing fixed-point or floating-point arithmetic operations, shift operations, logic operations, and the like, and may also perform address operations and conversions. The register is mainly responsible for storing register operands, intermediate operation results and the like temporarily stored in the instruction execution process. In particular implementations, the hardware architecture of the processor 610 may be an application specific integrated circuit (application specific integrated circuits, ASIC) architecture, a microprocessor (microprocessor without interlocked piped stages architecture, MIPS) architecture of an interlocking-less pipeline stage architecture, an advanced reduced instruction set machine (advanced RISC machines, ARM) architecture, or an NP architecture, among others. Processor 610 may be single-core or multi-core.
Illustratively, the interface 620 may be used to input data to be processed to the processor 610, and may output the processing results of the processor 610 to the outside. In a specific implementation, interface 620 may be a general purpose input output (general purpose input output, GPIO) interface. Interface 620 is coupled to processor 610 through bus 630.
In a possible implementation manner, the processor 610 may be configured to invoke, from the memory, an implementation program or data of the digital predistortion coefficient acquiring method provided in one or more embodiments of the present application in the digital predistortion circuit, so that the chip may implement the method shown in fig. 6 described above. The memory may be integrated with the processor 610 or coupled to the communication chip 600 via the interface 620, i.e., the memory may be part of the communication chip 600 or may be separate from the communication chip 600. The interface 620 may be used to output the execution results of the processor 610. In this application, the interface 620 may be specifically configured to output the decoding result of the processor 610. The digital predistortion coefficient acquirer provided in one or more embodiments of the present application may refer to the foregoing embodiments, and will not be described herein.
It should be noted that, the functions corresponding to the processor 610 and the interface 620 may be implemented by a hardware design, a software design, or a combination of hardware and software, which is not limited herein.
It should also be understood that the memory referred to in the embodiments of the present application may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable EPROM (EEPROM), or a flash Memory. The volatile memory may be random access memory (Random Access Memory, RAM) which acts as an external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (Double Data Rate SDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), and Direct memory bus RAM (DR RAM).
It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, transistor logic device, or discrete hardware component, the memory (storage module) is integrated in the processor.
Embodiments of the present application also provide a transmitter including an antenna and a digital predistortion circuit as described above in any of the embodiments of fig. 1-4B.
The embodiment of the application also provides a computer storage medium, wherein the computer storage medium can store a program, and the program can include part or all of the steps of any one of the digital predistortion coefficient acquisition methods described in the above method embodiments when executed.
It should be noted that, for simplicity of description, the foregoing method embodiments are all expressed as a series of action combinations, but it should be understood by those skilled in the art that the present application is not limited by the order of actions described, as some steps may be performed in other order or simultaneously in accordance with the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required in the present application.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
In the several embodiments provided in this application, it should be understood that the disclosed apparatus may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, such as a division of units, merely a division of logic functions, and there may be additional divisions in actual implementation, such as multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, or may be in electrical or other forms.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a memory, including several instructions for causing a computer device (which may be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the methods of the embodiments of the present application. And the aforementioned memory includes: a U-disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Those of ordinary skill in the art will appreciate that all or a portion of the steps in the various methods of the above embodiments may be implemented by a program that instructs associated hardware, and that the program may be stored in a computer readable memory, which may include: flash disk, read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), magnetic disk or optical disk.
The foregoing has outlined rather broadly the more detailed description of embodiments of the present application, wherein specific examples are provided herein to illustrate the principles and embodiments of the present application, the above examples being provided solely to assist in the understanding of the methods of the present application and the core ideas thereof; meanwhile, as those skilled in the art will have modifications in the specific embodiments and application scope in light of the ideas of the present application, the present disclosure should not be construed as being limited to the above description.
Claims (23)
1. A digital predistortion circuit, said circuit comprising: a digital predistortion DPD module, a power amplifier, a signal recovery circuit and a band limited DPD coefficient extraction circuit, wherein,
the output signal of the digital predistortion DPD module is input to the power amplifier, the output signal of the power amplifier is input to the signal recovery circuit, the output signal of the signal recovery circuit is input to the band-limited DPD coefficient extraction circuit, and the output signal of the band-limited DPD coefficient extraction circuit is input to the digital predistortion DPD module;
The band-limited DPD coefficient extraction circuit is used for determining a DPD coefficient according to the output signal of the signal recovery circuit and a first input signal, wherein the first input signal comprises an input signal of the digital predistortion DPD module or an output signal of the digital predistortion DPD module;
the band-limited DPD coefficient extraction circuit includes an adder and a band-limited DPD coefficient extractor, wherein,
the input signal of the adder comprises an output signal of the digital predistortion DPD module and a first output signal of the band-limited DPD coefficient extractor, the output signal of the adder is input to the band-limited DPD coefficient extractor, a second output signal of the band-limited DPD coefficient extractor is input to the digital predistortion DPD module, and an output signal of the signal restorer is input to the band-limited DPD coefficient extractor;
the band-limited DPD coefficient extractor is used for determining the DPD coefficient according to the output signal of the adder and the output signal of the signal restorer.
2. The digital predistortion circuit of claim 1 wherein said signal recovery circuit comprises a multiplier, a spread spectrum signal generator, a pre-band limiting filter and a signal recoverer, wherein,
The input signals of the multiplier comprise the output signals of the power amplifier and the output signals of the spread spectrum signal generator, the output signals of the multiplier are input to the pre-band-limit filter, the output signals of the pre-band-limit filter are input to the signal restorer, and the output signals of the signal restorer are input to the band-limit DPD coefficient extraction circuit.
3. A digital predistortion circuit according to claim 2, further comprising an analog-to-digital converter through which the output signal of the pre-band-limited filter is input to the signal restorer.
4. A digital predistortion circuit according to claim 3, wherein the analog-to-digital converter comprises a low speed analog-to-digital converter.
5. A digital predistortion circuit according to any of the claims 2 to 4, wherein said predistortion filter comprises a low pass filter, a high pass filter or a band pass filter.
6. A digital predistortion circuit according to any one of claims 1 to 4, further comprising a coupler through which an output signal of said power amplifier is input to said signal recovery circuit.
7. A digital predistortion circuit according to any of claims 1 to 4, further comprising a digital to analog converter through which an output signal of the digital predistortion DPD module is input to the power amplifier.
8. A digital predistortion circuit, said circuit comprising: a digital predistortion DPD module, a power amplifier, a signal recovery circuit and a band limited DPD coefficient extraction circuit, wherein,
the output signal of the digital predistortion DPD module is input to the power amplifier, the output signal of the power amplifier is input to the signal recovery circuit, the output signal of the signal recovery circuit is input to the band-limited DPD coefficient extraction circuit, and the output signal of the band-limited DPD coefficient extraction circuit is input to the digital predistortion DPD module;
the band-limited DPD coefficient extraction circuit is used for determining a DPD coefficient according to the output signal of the signal recovery circuit and a first input signal, wherein the first input signal comprises an input signal of the digital predistortion DPD module or an output signal of the digital predistortion DPD module;
the band-limited DPD coefficient extraction circuit includes an adder and a band-limited DPD coefficient extractor, wherein,
The input signal of the adder comprises the input signal of the digital predistortion DPD module and the output signal of the signal restorer, the output signal of the adder is input to the band-limit DPD coefficient extractor, and the output signal of the band-limit DPD coefficient extractor is input to the digital predistortion DPD module;
the band-limited DPD coefficient extractor is used for determining the DPD coefficient according to the output signal of the adder.
9. The digital predistortion circuit of claim 8 wherein said signal recovery circuit comprises a multiplier, a spread spectrum signal generator, a pre-band limiting filter and a signal recoverer, wherein,
the input signals of the multiplier comprise the output signals of the power amplifier and the output signals of the spread spectrum signal generator, the output signals of the multiplier are input to the pre-band-limit filter, the output signals of the pre-band-limit filter are input to the signal restorer, and the output signals of the signal restorer are input to the band-limit DPD coefficient extraction circuit.
10. The digital predistortion circuit according to claim 9, further comprising an analog-to-digital converter, wherein the output signal of the pre-band-limited filter is input to the signal restorer through the analog-to-digital converter.
11. The digital predistortion circuit of claim 10 wherein said analog to digital converter comprises a low speed analog to digital converter.
12. A digital predistortion circuit according to any of the claims 9 to 11, wherein said predistortion filter comprises a low pass filter, a high pass filter or a band pass filter.
13. A digital predistortion circuit according to any of claims 8 to 11, wherein the circuit further comprises a coupler through which the output signal of the power amplifier is input to the signal recovery circuit.
14. A digital predistortion circuit according to any of claims 8 to 11, further comprising a digital to analog converter through which an output signal of the digital predistortion DPD module is input to the power amplifier.
15. A digital predistortion coefficient acquisition method, characterized in that it is applied to a digital predistortion circuit, said circuit comprising a digital predistortion DPD module, a power amplifier, a signal recovery circuit and a band limited DPD coefficient extraction circuit, said method comprising:
the digital predistortion DPD module carries out nonlinear correction on an input signal to obtain an output signal of the digital predistortion DPD module;
The power amplifier amplifies the output signal of the digital predistortion DPD module to obtain an output signal of the power amplifier;
the signal recovery signal circuit recovers the output signal of the power amplifier to obtain an output signal of the signal recovery signal circuit;
the band-limited DPD coefficient extraction circuit determines a DPD coefficient according to an output signal of the signal recovery signal circuit and a first input signal, and inputs the output signal comprising the DPD coefficient to the digital predistortion DPD module, wherein the first input signal comprises an input signal of the digital predistortion DPD module or an output signal of the digital predistortion DPD module;
the band-limited DPD coefficient extraction circuit comprises an adder and a band-limited DPD coefficient extractor, the first input signal is an output signal of the digital predistortion DPD module, and the band-limited DPD coefficient extraction circuit determines the DPD coefficient according to the output signal of the signal recovery signal circuit and the first input signal, and the determining of the DPD coefficient comprises:
the adder performs addition operation according to the output signal of the digital predistortion DPD module and the first output signal of the band-limited DPD coefficient extractor to obtain an output signal of the adder;
The band-limited DPD coefficient extractor determines the DPD coefficient according to the output signal of the adder and the output signal of the signal restorer.
16. The method of claim 15, wherein the signal recovery circuit comprises a multiplier, a spread spectrum signal generator, a pre-band limiting filter, and a signal recovery circuit that recovers the output signal of the power amplifier to obtain the output signal of the signal recovery signal circuit comprises:
the multiplier performs multiplication operation on the output signal of the power amplifier and the output signal of the spread spectrum signal generator to obtain an output signal of the multiplier;
the pre-band-limit filter filters the output signal of the multiplier to obtain a narrow-band signal;
the signal restorer restores according to the narrowband signal to obtain a restored signal, and inputs the restored signal to the band-limited DPD coefficient extraction circuit.
17. The method of claim 16, wherein the circuit further comprises an analog-to-digital converter that analog-to-digital converts the narrowband signal to a digital signal, and wherein the digital signal is input to the signal restorer.
18. A digital predistortion coefficient acquisition method, characterized in that it is applied to a digital predistortion circuit, said circuit comprising a digital predistortion DPD module, a power amplifier, a signal recovery circuit and a band limited DPD coefficient extraction circuit, said method comprising:
the digital predistortion DPD module carries out nonlinear correction on an input signal to obtain an output signal of the digital predistortion DPD module;
the power amplifier amplifies the output signal of the digital predistortion DPD module to obtain an output signal of the power amplifier;
the signal recovery signal circuit recovers the output signal of the power amplifier to obtain an output signal of the signal recovery signal circuit;
the band-limited DPD coefficient extraction circuit determines a DPD coefficient according to an output signal of the signal recovery signal circuit and a first input signal, and inputs the output signal comprising the DPD coefficient to the digital predistortion DPD module, wherein the first input signal comprises an input signal of the digital predistortion DPD module or an output signal of the digital predistortion DPD module;
the band-limited DPD coefficient extraction circuit comprises an adder and a band-limited DPD coefficient extractor, wherein the first input signal is the input signal of the digital predistortion DPD module, and the band-limited DPD coefficient extraction circuit determines the DPD coefficient according to the output signal of the signal recovery signal circuit and the first input signal, and comprises:
The adder performs addition operation according to the input signal of the digital predistortion DPD module and the first output signal of the band-limited DPD coefficient extractor to obtain an output signal of the adder;
the band-limited DPD coefficient extractor determines the DPD coefficient according to the output signal of the adder.
19. The method of claim 18, wherein the signal recovery circuit comprises a multiplier, a spread spectrum signal generator, a pre-band limiting filter, and a signal recovery circuit that recovers the output signal of the power amplifier to obtain the output signal of the signal recovery signal circuit comprises:
the multiplier performs multiplication operation on the output signal of the power amplifier and the output signal of the spread spectrum signal generator to obtain an output signal of the multiplier;
the pre-band-limit filter filters the output signal of the multiplier to obtain a narrow-band signal;
the signal restorer restores according to the narrowband signal to obtain a restored signal, and inputs the restored signal to the band-limited DPD coefficient extraction circuit.
20. The method of claim 19, wherein the circuit further comprises an analog-to-digital converter that analog-to-digital converts the narrowband signal to a digital signal and inputs the digital signal to the signal restorer.
21. A transmitter comprising an antenna and a digital predistortion circuit according to any of claims 1 to 14.
22. A chip system comprising a processor for supporting a digital predistortion circuit to implement the method of any of claims 15 to 20.
23. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program comprising program instructions which, when executed by a processor, cause the processor to perform the method of any of claims 15 to 20.
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