CN113299612B - Semiconductor device with a semiconductor device having a plurality of semiconductor chips - Google Patents
Semiconductor device with a semiconductor device having a plurality of semiconductor chips Download PDFInfo
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- CN113299612B CN113299612B CN202110160721.9A CN202110160721A CN113299612B CN 113299612 B CN113299612 B CN 113299612B CN 202110160721 A CN202110160721 A CN 202110160721A CN 113299612 B CN113299612 B CN 113299612B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 139
- 230000001681 protective effect Effects 0.000 claims abstract description 145
- 238000009826 distribution Methods 0.000 claims abstract description 85
- 230000002093 peripheral effect Effects 0.000 claims abstract description 51
- 230000005684 electric field Effects 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 230000007423 decrease Effects 0.000 claims description 15
- 239000003566 sealing material Substances 0.000 claims description 15
- 238000005538 encapsulation Methods 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 8
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 5
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 230000036961 partial effect Effects 0.000 abstract description 9
- 239000010410 layer Substances 0.000 description 21
- 238000010586 diagram Methods 0.000 description 18
- 239000003989 dielectric material Substances 0.000 description 10
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- 230000000052 comparative effect Effects 0.000 description 5
- 230000003247 decreasing effect Effects 0.000 description 5
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- 239000011229 interlayer Substances 0.000 description 4
- 239000002344 surface layer Substances 0.000 description 4
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- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
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- 238000009792 diffusion process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention suppresses partial discharge and creeping discharge by flattening the electric field intensity distribution in a pressure-resistant holding region of a semiconductor device. In a semiconductor device (100) in which a protective film (15) is provided in a pressure-resistant holding region (A2) from the end of an effective region (A1) to the peripheral end (A3) of a chip on a semiconductor substrate (1), the protective film (15) is formed by a dielectric having a dielectric constant that varies within the film. In a voltage-resistant holding area part (A2) from the end part of an effective area part (A1) to the end part (A3) of the periphery of a chip, when the electric field intensity in the case of not arranging a protective film (15) has a first inclination distribution, the dielectric constant of the protective film (15) is adjusted to have a second inclination distribution which is the same as the first inclination distribution, so that the electric field intensity distribution in the whole area of the voltage-resistant holding area part (A2) can be flattened.
Description
Technical Field
The present application relates to a semiconductor device.
Background
In a power semiconductor device used for power control, that is, in a power semiconductor device, it is necessary to maintain a high voltage. Therefore, a voltage holding region (ineffective region) for holding a high voltage is provided between the outer peripheral end of the divided semiconductor substrate and the effective region where the semiconductor element is formed.
In general, a pressure-resistant holding structure portion composed of a diffusion layer for sharing and holding a high voltage is formed in the pressure-resistant holding region portion. Examples of the pressure-resistant holding structure include an FLR (FIELD LIMITING RING: field limiting ring) structure, a RESURF (REduced SUrface Field: lowering surface electric field) structure, and a VLD (Variation of Lateral Doping: lateral doping variation) structure. The semiconductor device can hold a high voltage by providing a voltage holding region on one main surface of a semiconductor substrate surrounding a semiconductor element.
However, the larger the width of the pressure-resistant holding region portion from the end of the effective region located in the central portion of the semiconductor device to the outer peripheral end of the semiconductor substrate is, the larger the chip size becomes, and the number of chips taken out from 1 semiconductor wafer decreases, so the chip cost increases. Therefore, the pressure holding area portion is required to be formed smaller in width. In particular, silicon carbide (SiC) semiconductor devices expected as next-generation power semiconductor devices are required to be miniaturized because of many crystal defects in addition to the high cost of SiC wafers. If the chip size becomes smaller, the chip cost and the defect content can be reduced. Thus, in the related art, the width of the pressure-resistant holding region portion is reduced by using the FLR structure, RESURF structure, VLD structure, or the like.
On the other hand, if the width of the pressure-resistant holding region portion is small, the creepage distance between the chip outer peripheral end portion and the effective region portion becomes short, and therefore creeping discharge is liable to occur between the chip outer peripheral end portion and the effective region portion. Therefore, in a semiconductor device in which the width of the pressure-resistant holding region cannot be sufficiently ensured, for example, in order to prevent creeping discharge, it is necessary to use a dielectric having a higher value of dielectric constant to form a resin molded package or the like, and as a result, it is necessary to take a lot of effort on the package sealing material, and as a result, there is a case where the cost increases.
Further, a semiconductor device is disclosed in which a plurality of grooves are provided on an upper surface of a protective film covering a pressure-resistant holding region, thereby forming irregularities on the upper surface of the protective film and lengthening a creepage distance (for example, refer to patent document 1).
Further, a semiconductor device having a structure in which a voltage holding region is covered with a low-resistance film is disclosed (for example, refer to patent document 2).
Prior art literature
Patent literature
Patent document 1: japanese patent laid-open publication No. 2014-204067
Patent document 2: japanese patent laid-open No. 4-212468
Disclosure of Invention
Technical problem to be solved by the invention
In the technique of patent document 1, the creepage distance can be striven for by the groove portion formed on the upper surface of the protective film, but when the electric field intensity distribution in the base structure portion of the protective film has an oblique distribution, a local electric field may be generated in the pressure-resistant holding region portion, and even a partial discharge may occur.
In patent document 2, the voltage holding region is covered with a low-resistance film, so that the occurrence of partial discharge can be suppressed, but there is a problem in that the use of a low-resistance film increases leakage current contributing to progress of creeping discharge, and the progress of discharge is likely to occur.
The present application has been made to solve the above-described problems, and an object thereof is to provide a semiconductor device in which a high insulation property and a stress relaxation property are ensured as functions of a protective film, and in which creeping discharge and partial discharge can be effectively suppressed in a pressure-resistant holding region from an end portion of an effective region to an outer peripheral end portion of a semiconductor substrate by using the protective film.
Technical proposal adopted for solving the technical problems
The semiconductor device according to the present application includes: a semiconductor substrate; a semiconductor layer formed on one main surface of the semiconductor substrate; an effective region portion formed by forming a semiconductor element in the semiconductor layer; a pressure-resistant holding region portion provided between an end portion of the effective region portion and an outer peripheral end portion of the semiconductor substrate; and a protective film made of a dielectric material covering the voltage holding region, wherein when an electric field strength in a case where the protective film is not provided has a first tilt distribution in a range from an end of the effective region of the voltage holding region to an outer peripheral end of the semiconductor substrate, a dielectric constant of the protective film has a second tilt distribution, and the first tilt distribution and the second tilt distribution have the same tendency.
Effects of the invention
According to the semiconductor device of the present application, in the pressure-resistant holding region portion, when the electric field strength of the base structure portion has the first inclined portion, the electric potential gradient can be flattened by adjusting the dielectric constant of the protective film so as to become the second inclined distribution having the same tendency as the first inclined distribution. Therefore, the electric field intensity distribution in the pressure-resistant holding region portion provided with the protective film can be smoothed more than the first oblique distribution in the case where the protective film is not provided, and partial discharge and creeping discharge can be suppressed.
Drawings
Fig. 1 is a main part sectional view of a semiconductor device according to embodiment 1.
Fig. 2 is a plan view of a protective film of the semiconductor device according to embodiment 1.
Fig. 3 is a diagram illustrating a first mode of embodiment 1, fig. 3 (a) is a diagram illustrating an electric field intensity distribution of a pressure-resistant holding region portion of a protective film that does not include a base structure portion that is a protective film, and fig. 3 (b) is a diagram illustrating a dielectric constant distribution of the pressure-resistant holding region portion of the protective film.
Fig. 4 is a diagram showing an electric field intensity distribution in a pressure-resistant holding region portion including the protective film according to embodiment 1.
Fig. 5 is a diagram illustrating a second mode of embodiment 1, in which fig. 5 (a) is a diagram illustrating an electric field intensity distribution of a pressure-resistant holding region portion of a protective film that does not include a base structure portion that is a protective film, and fig. 5 (b) is a diagram illustrating a dielectric constant distribution of the pressure-resistant holding region portion of the protective film.
Fig. 6 is a diagram illustrating a third mode of embodiment 1, in which fig. 6 (a) is a diagram illustrating an electric field intensity distribution of a pressure-resistant holding region portion of a protective film that does not include a base structure portion that is a protective film, and fig. 6 (b) is a diagram illustrating a dielectric constant distribution of the pressure-resistant holding region portion of the protective film.
Fig. 7 is a plan view of a protective film of the semiconductor device according to embodiment 2.
Fig. 8 is a main part sectional view of the semiconductor device according to embodiment 3.
Fig. 9 is a main part sectional view of the semiconductor device according to embodiment 4.
Fig. 10 is a main part sectional view of the semiconductor device according to embodiment 5.
Fig. 11 is a main part sectional view of the semiconductor device according to embodiment 6.
Fig. 12 is a main part sectional view of a semiconductor device not provided with a protective film as a comparative example.
Detailed Description
Embodiment 1.
The semiconductor device 100 according to embodiment 1 of the present application will be described with reference to fig. 1 to 6 and 12. The semiconductor device 100 is, for example, a power semiconductor device suitable for use in power control, and has a withstand voltage performance capable of withstanding a high voltage. However, the structure of the semiconductor device 100 may be used for applications other than a power semiconductor device.
Fig. 12 is a cross-sectional view of a main portion of a semiconductor device 100 having no structure of a protective film according to a comparative example of the present application.
Fig. 1 is a main part sectional view of a semiconductor device 100 according to embodiment 1, and shows a section of a region including a pressure-resistant holding structure portion in the vicinity of an end portion of a semiconductor chip, which is a semiconductor substrate 1 after dicing. For example, the effective region A1 where the semiconductor element is formed is located in the center portion (left end portion in fig. 1) of the semiconductor substrate 1, the chip outer peripheral end portion A3 (outer peripheral end portion of the semiconductor substrate 1) is located in the outer peripheral portion (right end portion in fig. 1) of the semiconductor substrate 1, and the withstand voltage holding region A2 (withstand voltage holding region) is located between the effective region A1 and the chip outer peripheral end portion A3. The semiconductor device 100 has a structure sealed with a package sealing material, not shown, for example.
Fig. 2 is a plan view showing the planar shape of the protective film 15 formed on one principal surface side of the semiconductor device 100.
Fig. 3 (a) and 3 (b), fig. 5 (a) and 5 (b), fig. 6 (a) and 6 (b) are diagrams for explaining the characteristics of the semiconductor device 100 of the present application, and fig. 3 (a) and 3 (b) show a first mode in which the position where the electric field strength and the dielectric constant take the maximum value is located on the voltage holding area A2 side and tends to fall to the right, fig. 5 (a) and 5 (b) show a second mode in which the position where the electric field strength and the dielectric constant take the maximum value is located on the chip peripheral end portion A3 side and tends to rise to the right, and fig. 6 (a) and 6 (b) show a third mode in which the peak value of the electric field strength and the dielectric constant is located at the intermediate position of the voltage holding area A2.
Here, fig. 3 (a), 5 (a), and 6 (a) are explanatory diagrams showing the electric field intensity distribution (first oblique distribution) of the voltage holding region A2 in the base structure portion 20 (region portion including the upper surface of the field insulating film 14) of the protective film 15 in the case where the protective film 15 is not formed in the semiconductor device 100 as in the comparative example shown in fig. 12, the vertical axis shows the electric field intensity (electric field E), and the horizontal axis shows the position of the voltage holding region A2 from the end of the effective region A1 to the chip outer peripheral end A3.
Fig. 3b, 5 b, and 6 b are explanatory diagrams showing a dielectric constant distribution (second oblique distribution) of the voltage holding region A2 formed in the protective film 15 of the semiconductor device 100, the vertical axis showing the dielectric constant (dielectric constant epsilon), and the horizontal axis showing the position of the voltage holding region A2, similarly to fig. 3.
The typical protective film has an inherent dielectric constant, and the dielectric constant does not change within the film, but in the present application, the protective film 15 is adjusted so that the dielectric constant changes depending on the position within the film and according to the electric field strength.
Fig. 4 is an explanatory diagram showing the electric field intensity distribution of the voltage holding region A2 in the case where the protective film 15 is formed on the semiconductor device 100, and the vertical and horizontal axes are the same as those in fig. 3 (a), 5 (a), and 6 (a).
In the present application, since the first and second oblique distributions have the same tendency to increase or decrease, and the position of the maximum value or peak of the dielectric constant of the protective film 15 overlaps with the position of the maximum value or peak of the first oblique distribution, the electric field intensity distribution of the semiconductor device 100 including the protective film 15 is flattened as shown in fig. 4.
Next, the structure and the operation of the semiconductor device 100 according to embodiment 1 of the present application will be described in more detail. As shown in fig. 1, the semiconductor device 100 includes a semiconductor substrate 1 and an epitaxial layer 2, and the epitaxial layer 2 is a semiconductor layer formed on one main surface of the semiconductor substrate 1 and formed by epitaxial growth. The epitaxial layer 2 can be distinguished as: an effective region A1 formed with a semiconductor element; a chip outer peripheral end portion A3 as an outer peripheral portion of the semiconductor chip; and a pressure-resistant holding area part A2 having a pressure-resistant holding structure part arranged between the effective area part A1 and the chip peripheral end part A3. The pressure-resistant holding area portion A2 and the chip outer peripheral end portion A3 are formed so as to surround the effective area portion A1.
In the semiconductor device 100, for example, an N-type MOSFET is formed in the semiconductor element of the active area A1. In this case, the conductivity type of the semiconductor substrate 1 and the epitaxial layer 2 is set to be N-type. Here, the semiconductor substrate 1 and the epitaxial layer 2 are formed of silicon carbide (SiC). The semiconductor element is not limited to an N-type MOSFET, and may be a P-type MOSFET, an IGBT (Insulated Gate Bipolar Transistor: insulated gate bipolar transistor), a diode, or the like. The material of the semiconductor substrate 1 and the epitaxial layer 2 is not limited to silicon carbide, and may be other wide band gap semiconductors (gallium nitride (GaN), diamond, and the like). Further, a semiconductor device using silicon (Si) can also employ the structure of the present application.
In the active region A1, a P-type well region 3 is selectively formed in a surface layer portion of the epitaxial layer 2. The well region 3 has an N-type source region 4 and a well contact region 5, which is a high-concentration P-type region, formed in a surface layer portion thereof. The portion of the well region 3 sandwiched between the N-type region of the epitaxial layer 2 and the source region 4 becomes a channel region of the MOSFET.
A gate insulating film 6 is formed on the epitaxial layer 2 so as to cover the channel region, and a gate electrode 7 is formed on the gate insulating film 6. An interlayer insulating film 8 is formed on the upper layer of the gate electrode 7, and a source electrode 9 is formed on the upper layer of the interlayer insulating film 8. The source electrode 9 is connected to the source region 4 and the well contact region 5 via a contact hole opened in the interlayer insulating film 8. Further, a drain electrode 10 is disposed on the lower surface (back surface) of the semiconductor substrate 1.
On the other hand, in the voltage holding region A2, the surface layer portion of the epitaxial layer 2 is provided with a P-type termination well region 11 and a P-type FLR13, which is a voltage holding structure portion formed outside thereof, as termination structures for holding voltages. The termination well region 11 is connected to the source electrode 9 via a contact hole opened in a surface layer portion thereof, and the connection portion is formed with a high-concentration P-type region, i.e., a termination well contact region 12. As the pressure-resistant holding structure portion provided in the pressure-resistant holding region portion A2, A RESURF structure, A VLD structure, A JTE (Junction Termination Extension: junction termination extension) structure, or the like may be used in addition to the FLR structure.
A field insulating film 14 is formed on the upper layer of the epitaxial layer 2 in the voltage holding region A2, and a protective film 15 made of polyimide is formed on the upper layer of the base structure portion 20 formed by patterning the field insulating film 14, the source electrode 9, and the like on the semiconductor substrate 1 so as to cover the voltage holding region A2.
A sealing material (not shown) made of epoxy resin or the like is laminated on the protective film 15. In addition, the encapsulation sealing material has an inherent dielectric constant, which is constant.
In embodiment 1, as shown in fig. 2, a groove portion 16 (groove) is formed in a cross section of the protective film 15 from the protective film inner peripheral end 151 to the protective film outer peripheral end 152 so that the upper surface is uneven.
In the present application, the tendency of increasing or decreasing the dielectric constant distribution of the protective film 15 is superimposed on the tendency of increasing or decreasing the electric field intensity distribution of the base structure portion 20 of the protective film 15 serving as a comparative example to suppress the electric field, and thus the effect of suppressing the acceleration of electrons and the effect of preventing the progress of electrons by providing a wall portion on the path of electrons by the convex portion provided on the upper surface of the protective film 15 can be obtained, and the effect of suppressing the creeping discharge can be obtained.
Here, the characteristic of the semiconductor device 100 of the present application, that is, the tilt distribution of the dielectric constant of the protective film 15 will be described. The protective film 15 is made of a dielectric material, and the dielectric constant distribution (second oblique distribution) of the protective film 15 is adjusted so that the dielectric constant of the protective film 15 has a dielectric constant distribution (second oblique distribution) having the same tendency to increase as the first oblique distribution, so that the dielectric strength of the voltage holding region A2 from the outside of the effective region A1 to the chip peripheral end A3 is not constant.
Next, three typical modes of the semiconductor device 100 of the present application will be described in order.
First, a first mode will be described. In the case where the protective film 15 is not provided (the structure of the comparative example shown in fig. 12, including the case where a film having a uniform dielectric constant within the film is formed as the protective film), the electric field intensity distribution of the base structure portion 20 of the protective film 15 including the upper surface of the field insulating film 14 is locally higher in the electric field intensity on the side of the effective area portion A1 as shown in fig. 3 (a), and has an electric field intensity distribution (first slope distribution) which tends to decrease rightward (monotonically decrease) with the approach to the chip peripheral end portion A3. In this case, problems such as partial discharge are likely to occur at the position (left end portion in fig. 3 (a)) of the voltage holding area portion A2 near the effective area portion A1 where the electric field intensity is locally high.
Accordingly, for example, in order to make the electric field intensity distribution constant (smooth) in the voltage holding region A2 in accordance with the electric field intensity distribution in fig. 3 (a), the dielectric constant of the protective film 15 is configured such that the dielectric constant of the protective film 15 in the voltage holding region A2 is distributed so as to be inclined such that the dielectric constant becomes higher on the effective region A1 side and becomes lower on the chip peripheral end A3 side as shown in fig. 3 (b). That is, in the case of the first mode, the protective film 15 is formed by a dielectric having a monotonically decreasing dielectric constant from the outside of the effective region A1 to the chip peripheral end A3 in the pressure-resistant holding region A2 from the end of the effective region A1 to the chip peripheral end A3, thereby performing the processing.
By using the dielectric constant distribution (second slope distribution) of the protective film 15 having the same tendency to increase or decrease as the electric field intensity distribution (first slope distribution) of the voltage holding region A2 in the case where the protective film 15 is not provided, the portion of the protective film 15 having a large dielectric constant can be partially overlapped with the position where the electric field intensity is partially increased, and the potential gradient in the voltage holding region A2 can be relaxed. As a result, by the action of the protective film 15, the locally higher portion of the first oblique distribution can be further suppressed to be lower than in the case where the protective film 15 is not formed, and the electric field intensity distribution of the voltage holding region A2 on the upper surface of the field insulating film 14 can be flattened as shown in fig. 4.
Thereby, the occurrence of partial discharge and progress of creeping discharge between the effective area portion A1 and the chip peripheral end portion A3 can be suppressed. Further, since the protective film 15 is made of a dielectric (insulating material), the leakage current contributing to progress of the creeping discharge is significantly smaller than the leakage current using a resistive film (semiconductive material), and progress of the creeping discharge can be suppressed.
Next, a case of a second mode in which the potential gradient of the base structure portion 20, which is a first oblique distribution, is different from the first mode and tends to rise rightward (monotonically increases) will be described with reference to fig. 5 (a) and 5 (b).
As shown in fig. 5 (a), the electric field intensity distribution of the pressure-resistant holding region portion A2 of the base structure portion 20 decreases as it approaches the effective region portion A1, and increases as it approaches the chip outer peripheral end portion A3, and in the case where this tendency is present, as shown in fig. 5 (b), the protective film 15 is formed by using a dielectric having a second slope distribution in which the dielectric constant monotonically increases from the outside of the effective region portion A1 to the chip outer peripheral end portion A3. As a result, the tendency of increasing or decreasing the electric field intensity distribution (first oblique distribution) of the base structure portion 20 can be made to coincide with the tendency of increasing or decreasing the dielectric constant distribution (second oblique distribution) of the protective film 15, and the potential gradient of the pressure-resistant holding region portion A2 can be flattened as shown in fig. 4.
Next, a case of a third mode in which the potential gradient of the base structure portion 20, which is a first oblique distribution, is different from the first and second modes and a peak tends to be present at the intermediate position will be described with reference to fig. 6 (a) and 6 (b).
As shown in fig. 6a, when the electric field intensity distribution (first oblique distribution) of the pressure-resistant holding region portion A2 of the base structure portion 20 has a peak at an intermediate position between the effective region portion A1 and the chip outer peripheral end portion A3, for example, at the central portion, as shown in fig. 6b, the protective film 15 is formed by using a dielectric having a dielectric constant distribution (second oblique distribution) as follows: the dielectric constant monotonically increases from the outside of the effective region A1 to the intermediate position between the effective region A1 and the chip outer peripheral end portion A3, has a peak at the intermediate position thereof, and monotonically decreases from the peak to the chip outer peripheral end portion A3. This allows the peak value of the dielectric constant distribution (second oblique distribution) of the protective film 15 to overlap the peak value of the electric field intensity distribution (first oblique distribution) of the base structure portion 20, and the potential gradient of the pressure-resistant holding region portion A2 can be flattened as shown in fig. 4.
Fig. 6 (a) and 6 (b) show an example in which the peak values of the first and second oblique distributions are one, but in the case where there are a plurality of peak values, the dielectric constant of the protective film 15 is adjusted so that the peak values overlap each other at least one position or at positions of the plurality of peak values.
In addition, as for the tilt distribution (second tilt distribution) of the dielectric constant of the protective film 15, not only the dielectric constant can be changed in the lateral direction from the effective region portion A1 shown in fig. 3 (b), 5 (b), and 6 (b) toward the chip outer peripheral end portion A3, but also the dielectric constant whose dielectric constant changes in the thickness direction or both the thickness direction and the width direction of the protective film 15 can be applied if the electric field intensity distribution can be flattened.
As an example of changing the dielectric constant in the thickness direction of the protective film 15, for example, adjustment may be made so that the upper surface dielectric constant of the field insulating film 14, which becomes the surface portion of the base structure portion 20, becomes maximum and the upper surface dielectric constant of the protective film 15 becomes minimum. Thus, by matching the portion having the highest dielectric constant in the range of the thickness of the protective film 15 with the height at which the electric field intensity becomes locally large in the range of the thickness of the protective film 15, the potential gradient can be flattened also in the film thickness direction of the protective film 15.
The protective film 15 may be formed by using a series of dielectrics, and using dielectrics in which the dielectric constants are distributed obliquely, or may be formed by using 2 or more dielectrics each having a different dielectric constant, and by distributing the dielectrics to the divided regions and integrating the dielectrics, the entire structure is a single film.
Here, when the protective film 15 is formed using 2 or more dielectrics, the linear expansion coefficients of the dielectrics are preferably the same. However, if the local high electric field intensity can be flattened, the linear expansion coefficients may be different. The protective film 15 preferably has a linear expansion coefficient equal to that of the semiconductor substrate 1 or the encapsulation material (not shown). By setting the linear expansion coefficients of the protective film 15 and the encapsulation sealing material to the same value, peeling at their boundaries can be prevented.
As shown in fig. 2, the groove 16 may be formed in a ring shape so as to surround the effective area A1, or may be formed in a spiral shape so as to surround the effective area A1 if the length of the surface can be increased, or may be configured by being appropriately deformed.
Embodiment 2.
Fig. 7 is a plan view of the protective film 15 of the semiconductor device 100 according to embodiment 2.
The semiconductor device 100 according to embodiment 2 differs from the semiconductor device 100 according to embodiment 1 in that the planar shape of the groove portion 16 of the protective film 15 is formed in a checkered pattern (or a mosaic shape). When the planar shape of the groove 16 is in the shape of a checkered pattern, for example, as shown in fig. 7, the groove 16 having a square shape is configured such that 2 adjacent grooves 16 are in point contact with each other at each corner, and a square region having the upper surface of the protective film 15 where no groove 16 is formed is in marginal contact with the groove 16. In this case, in a cross section from the protective film inner peripheral end 151 to the protective film outer peripheral end 152, a surface shape having continuous irregularities as shown in fig. 1 can be realized, and a creepage distance can be strived for.
By forming the groove 16 in a checkered pattern, the boundary between the concave portion and the convex portion of the protective film 15 can be increased as compared with the annular groove as in embodiment 1, and the area of the upper surface of the protective film 15 can be increased, so that the adhesive strength between the protective film 15 and the sealing material can be increased when the sealing material is laminated on the upper layer of the protective film 15. Further, the adhesion of the encapsulation sealing material can be improved by utilizing the anchoring effect of the convex portion of the protective film 15, and thus, the occurrence of problems such as peeling of the encapsulation sealing material can be suppressed.
Embodiment 3.
Fig. 8 is a diagram showing a structure of the semiconductor device 100 according to embodiment 3, and shows a cross section near an end portion of a semiconductor chip.
The semiconductor device 100 according to embodiment 3 of the present application differs from embodiments 1 and 2 in that the corner 17 of the protective film 15 is formed in a C-chamfer shape.
By forming the corner 17 of the protective film 15 into a C-chamfer shape (a shape obtained by chamfering a plane), stress concentration of a package sealing material (not shown) can be suppressed, and thus occurrence of problems such as cracks and peeling can be suppressed, and thus, there is an effect that deterioration of insulating performance of the semiconductor device 100 is suppressed.
In fig. 8, the corner 17 is formed in a C-chamfer shape, but may be formed in an R-shape (or a curved surface shape naturally formed at the time of manufacture).
Embodiment 4.
Fig. 9 is a diagram showing a structure of the semiconductor device 100 according to embodiment 4, and shows a cross section near an end portion of a semiconductor chip.
The semiconductor device 100 according to embodiment 4 of the present application differs from embodiment 1 in that a groove portion 16b exposing the upper surface of the field insulating film 14 is formed in the protective film 15. In the protective film 15 located in the pressure-resistant holding area portion A2, a plurality of divided protective films 15a are arranged intermittently, and one continuous protective film 15 is constituted by the plurality of protective films 15 a. In the example of fig. 9, 4 cross sections of the protective films 15a are shown, and groove portions 16b are provided between adjacent protective films 15a, respectively.
Here, for example, the plurality of protective films 15a are made of dielectrics having different dielectric constants, and the dielectric constants of the protective films 15a can be set to dielectric constants corresponding to the positions in the pressure-resistant holding region A2 of the second oblique distribution shown in fig. 3 (b). Further, the dielectric constant of the protective film 15a is adjusted to be different from that of the encapsulation material.
Further, since the protective film 15 is not formed at the portion located in the groove 16b, the dielectric constant of the protective film 15 cannot be measured, and therefore, the data of the dielectric constant of the protective film 15 cannot be matched with the portion corresponding to the formation range of the groove 16b in the second oblique distribution illustrated in fig. 3 (b) and the like. However, in the actual structure, the encapsulation sealing material is buried in the groove portion 16b, and therefore, the dielectric constant of the encapsulation sealing material is matched.
Therefore, for example, the dielectric constants of the protective film 15 and the encapsulation material are matched to the second tilt distribution, and the electric field is smoothed to obtain the second tilt distribution.
In addition, in fig. 9 shows the example in which the protective film 15 of the pressure-resistant holding area A2 is formed with a plurality of groove portions 16b, but the formation site of the groove portions 16b may be of course only 1 place.
Thus, since the respective protective films 15a are formed locally by applying a dielectric constant different from that of the encapsulation sealing material, the potential sharing between the protective film 15a and the encapsulation sealing material is enabled, and therefore, as in embodiment 1, the occurrence of partial discharge and the progress of creeping discharge can be suppressed while suppressing the concentration of an electric field.
On the other hand, the protective film 15a may be formed in a region other than the groove portion 16b, not the entire surface of the pressure-resistant holding region portion A2, so that the material of the protective film 15 can be reduced, and the number of work steps can be reduced.
Embodiment 5.
Fig. 10 is a diagram showing a structure of a semiconductor device 100 according to embodiment 5, and shows a cross section near an end portion of a semiconductor chip.
The semiconductor device 100 according to embodiment 5 of the present application differs from embodiment 1 in that a protective film 15b having a smaller film thickness than the protective film 15 is formed in a region corresponding to the groove 16 on the upper surface of the protective film 15a, and the protective films 15a and 15b having two different heights are combined to form one protective film 15.
The protective film 15a and the protective film 15b may be formed by encapsulation using a plurality of molding machines (injectors) filled with materials having different dielectric constants, respectively.
Thus, even if the protective films 15a and 15b are formed as different members, the upper surface of the protective film 15 can be provided with irregularities by making the thicknesses thereof different as in embodiment 1.
Embodiment 6.
Fig. 11 is a diagram showing a structure of a semiconductor device 100 according to embodiment 6, and shows a cross section near an end portion of a semiconductor chip.
The semiconductor device 100 according to embodiment 6 of the present application differs from embodiment 1 in that the protective film 15 is extended to the chip end portion 18, and a protective film extension portion 15c is formed so as to cover the upper surface of the chip outer peripheral end portion A3 and the outer peripheral side end portion of the semiconductor substrate 1.
By forming the protective film extension 15c, the chip end 18 can be covered with the protective film 15, and the potential sharing area can be enlarged as compared with the case where the protective film extension 15c is not provided. Therefore, compared with the case where the protective film extension 15c is not provided, the generation of partial discharge and the progress of creeping discharge can be suppressed. At the same time, the stress concentration at the chip end 18 can be relaxed, and thus problems such as cracking and peeling can be suppressed.
The present disclosure describes the illustrated embodiments, but the various features, forms, and functions described in the embodiments are not limited to the application of the specific embodiments, and can be applied to the embodiments alone or in various combinations.
Accordingly, numerous modifications, which are not illustrated, are considered to be included in the technical scope of the present disclosure. For example, it is assumed that at least one component is deformed, added or omitted.
Description of the reference numerals
1. Semiconductor substrate
2. Epitaxial layer
3. Well region
4. Source region
5. Well contact region
6. Gate insulating film
7. Gate electrode
8. Interlayer insulating film
9. Source electrode
10. Drain electrode
11. Terminal well region
12. Terminal well contact region
13 FLR
14. Field insulating film
15. 15A, 15b protective film
15C protective film extension
16. 16B groove part
17. Corner portion
18. Chip end
20. Base structure
100. Semiconductor device with a semiconductor device having a plurality of semiconductor chips
151. Inner peripheral end of protective film
152. And a protective film peripheral end.
Claims (13)
1. A semiconductor device, comprising:
A semiconductor substrate;
a semiconductor layer formed on one main surface of the semiconductor substrate;
an effective region portion formed by forming a semiconductor element in the semiconductor layer;
A pressure-resistant holding region portion provided between an end portion of the effective region portion and an outer peripheral end portion of the semiconductor substrate; and
A protective film made of a dielectric covering the pressure-resistant holding region,
When the electric field strength in the case where the protective film is not provided has a first oblique distribution in a range from the end of the effective region portion of the pressure-resistant holding region portion to the outer peripheral end of the semiconductor substrate, the dielectric constant of the protective film has a second oblique distribution, and the first oblique distribution and the second oblique distribution have the same tendency.
2. The semiconductor device according to claim 1, wherein,
When the first slope distribution indicating an increase or decrease in the electric field intensity of the voltage holding region tends to monotonically decrease from the end of the effective region to the outer peripheral end of the semiconductor substrate, the second slope distribution indicating an increase or decrease in the dielectric constant of the protective film tends to monotonically decrease from the end of the effective region to the outer peripheral end of the semiconductor substrate.
3. The semiconductor device according to claim 1, wherein,
When the first slope distribution indicating the increase and decrease of the electric field intensity of the voltage holding region tends to monotonically increase from the end of the effective region to the outer peripheral end of the semiconductor substrate, the second slope distribution indicating the increase and decrease of the dielectric constant of the protective film tends to monotonically increase from the end of the effective region to the outer peripheral end of the semiconductor substrate.
4. The semiconductor device according to claim 1, wherein,
When the first slope distribution indicating the increase or decrease in the electric field intensity of the voltage holding region tends to have a peak at an intermediate position from the end of the effective region to the outer peripheral end of the semiconductor substrate, the second slope distribution indicating the increase or decrease in the dielectric constant of the protective film tends to have a peak at an intermediate position from the end of the effective region to the outer peripheral end of the semiconductor substrate.
5. The semiconductor device according to claim 4, wherein,
The peak of the first oblique distribution coincides with the peak of the second oblique distribution at least one position in a range from the end of the effective region portion of the pressure-resistant holding region portion to the outer peripheral end of the semiconductor substrate.
6. The semiconductor device according to any one of claims 1 to 5, wherein,
In the upper surface portion of the protective film, a cross section from an end portion of the effective region portion to an outer peripheral end portion of the semiconductor substrate is formed in a concave-convex shape.
7. The semiconductor device according to claim 6, wherein,
The planar shape of the groove portion of the concave portion constituting the upper surface portion of the protective film is configured to be a ring shape or a checkered pattern shape surrounding the outer periphery of the effective area portion.
8. The semiconductor device according to claim 6, wherein,
The protective film has corners formed by chamfering a curved surface or a plane.
9. The semiconductor device according to any one of claims 1 to 5, wherein,
The semiconductor device comprises an encapsulation material which covers the one main surface of the semiconductor layer and has a dielectric constant different from that of the protective film,
The protective film has the following structure: the pressure-resistant holding region is formed intermittently from an end of the effective region to an outer peripheral end of the semiconductor substrate, and the encapsulation sealing material is buried in a groove portion where the protective film is not formed.
10. The semiconductor device according to any one of claims 1 to 5, wherein,
The protective film is composed of a continuous film or a film obtained by integrating a plurality of films having different dielectric constants.
11. The semiconductor device according to any one of claims 1 to 5, wherein,
The protective film is formed to extend to an upper surface of an outer peripheral end portion of the semiconductor substrate, and is configured to cover a shape of an outer peripheral side end portion of the semiconductor substrate.
12. The semiconductor device according to any one of claims 1 to 5, wherein,
The structure is as follows: the dielectric constant of the protective film varies in the thickness direction of the protective film.
13. The semiconductor device according to any one of claims 1 to 5, wherein,
The semiconductor substrate is made of silicon carbide.
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| JP2006128646A (en) * | 2004-09-28 | 2006-05-18 | Sharp Corp | Electronic device and heterojunction fet |
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| JP2014204067A (en) * | 2013-04-09 | 2014-10-27 | 住友電気工業株式会社 | Semiconductor device and manufacturing method of the same |
| CN109891593A (en) * | 2016-10-28 | 2019-06-14 | 三菱电机株式会社 | Semiconductor device and power-converting device |
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| US7566917B2 (en) * | 2004-09-28 | 2009-07-28 | Sharp Kabushiki Kaisha | Electronic device and heterojunction FET |
| JP2011165924A (en) * | 2010-02-10 | 2011-08-25 | Mitsubishi Electric Corp | Semiconductor device |
| JP2015019014A (en) * | 2013-07-12 | 2015-01-29 | 住友電気工業株式会社 | Semiconductor device and method of manufacturing the same |
| US10361266B2 (en) * | 2014-06-09 | 2019-07-23 | Panasonic Intellectual Property Management Co., Ltd. | Semiconductor device |
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| JPH04212468A (en) * | 1990-11-08 | 1992-08-04 | Fuji Electric Co Ltd | High breakdown strength semiconductor device |
| CN1399348A (en) * | 2002-08-29 | 2003-02-26 | 电子科技大学 | Surface (transverse) voltage-proof structure with high-dielectric constant film |
| JP2006128646A (en) * | 2004-09-28 | 2006-05-18 | Sharp Corp | Electronic device and heterojunction fet |
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| JP6887541B1 (en) | 2021-06-16 |
| CN113299612A (en) | 2021-08-24 |
| JP2021132171A (en) | 2021-09-09 |
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