CN113299243A

CN113299243A - Pixel circuit, driving method thereof and display device

Info

Publication number: CN113299243A
Application number: CN202110679925.3A
Authority: CN
Inventors: 袁志东; 董学; 吴仲远; 王糖祥; 李永谦
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2021-06-18
Filing date: 2021-06-18
Publication date: 2021-08-24
Anticipated expiration: 2041-06-18
Also published as: CN113299243B

Abstract

The embodiment of the disclosure provides a pixel circuit, a driving method thereof and a display device. A pixel circuit, comprising: the voltage control module is respectively connected with the first power supply end, the control signal end and the first node and is configured to provide the voltage of the first power supply end to the first node under the control of the control signal end; the driving module is respectively connected with the data signal end, the first scanning signal end, the second scanning signal end, the first node, the second node and the detection signal line, and is configured to provide an electric signal of the detection signal line for the second node and provide an electric signal of the second node for the first node under the control of the first scanning signal end and the second scanning signal end; and a switching module configured to supply the voltage of the second power source terminal to the detection signal line under the control of the third scan signal terminal. According to the technical scheme, the second node can be completely reset in the data writing stage, so that the second node is prevented from being interfered by other pixels in the same row, and the display effect is improved.

Description

Pixel circuit, driving method thereof and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, and a display device.

Background

The mature technologies in the display field include liquid crystal display and active matrix Organic Light-Emitting Diode (OLED) display, and the OLED display has the advantages of high response, high contrast, flexibility and the like, and is considered to have a wide application prospect. The OLED display forms a pattern by exciting a spectrum of various wavelengths through direct recombination of electrons and holes. The OLED display device has a fast response speed and can maximize the contrast, and thus, the OLED display device is expected to become a mainstream product for next generation display.

When a conventional pixel driving circuit, such as a 3T1C circuit, is applied to a silicon-based micro display, an anode electrical signal of an OLED device is easily interfered by other pixels to affect a display effect, and thus a new pixel driving method is urgently needed.

Disclosure of Invention

Embodiments of the present disclosure provide a pixel circuit, a driving method thereof, and a display device to solve or alleviate one or more technical problems in the prior art.

As a first aspect of embodiments of the present disclosure, embodiments of the present disclosure provide a pixel circuit including:

the voltage control module is respectively connected with the first power supply end, the control signal end and the first node and is configured to provide the voltage of the first power supply end to the first node under the control of the control signal end;

a driving module, respectively connected to the data signal terminal, the first scanning signal terminal, the second scanning signal terminal, the first node, the second node, and the detection signal line, configured to receive a data voltage of the data signal terminal under the control of the first scanning signal terminal, and provide an electrical signal to the second node to drive the light emitting module to emit light based on a voltage of the first node, or configured to provide an electrical signal of the detection signal line to the second node and provide an electrical signal of the second node to the first node under the control of the first scanning signal terminal and the second scanning signal terminal;

and the switch module is respectively connected with the third scanning signal terminal, the detection signal line and the second power supply terminal and is configured to supply the voltage of the second power supply terminal to the detection signal line under the control of the third scanning signal terminal.

In some possible implementations, the voltage control module includes a fifth transistor, a gate of the fifth transistor is connected to the control signal terminal, a first pole of the fifth transistor is connected to the first power source terminal, and a second pole of the fifth transistor is connected to the first node.

In some possible implementations, the driving module includes:

the writing sub-module is respectively connected with the first scanning signal terminal, the data signal terminal and the third node and is configured to provide data voltage of the data signal terminal for the third node under the control of the first scanning signal terminal;

the driving sub-module is respectively connected with the third node, the first node and the second node, and is configured to provide an electric signal to the second node under the control of the third node so as to drive the light-emitting module to emit light, or is configured to provide an electric signal of the second node to the first node under the control of the third node;

a storage submodule respectively connected with the third node and the second node and configured to store the charge of the third node;

and the sensing submodule is respectively connected with the second scanning signal terminal, the second node and the detection signal line and is configured to provide the electric signal of the second node to the detection signal line under the control of the second scanning signal terminal or provide the electric signal of the detection signal line to the second node under the control of the second scanning signal terminal.

In some of the possible implementations of the present invention,

the writing submodule comprises a first transistor, the grid electrode of the first transistor is connected with a first scanning signal end, the first pole of the first transistor is connected with a data signal end, and the second pole of the first transistor is connected with a third node; and/or the presence of a gas in the gas,

the driving sub-module comprises a third transistor, the grid electrode of the third transistor is connected with a third node, the first pole of the third transistor is connected with the second node, and the second pole of the third transistor is connected with the first node; and/or the presence of a gas in the gas,

the sensing submodule comprises a second transistor, the grid electrode of the second transistor is connected with the second scanning signal end, the first pole of the second transistor is connected with the second node, and the second pole of the second transistor is connected with the detection signal line.

In some possible implementations, the switch module includes a fourth transistor, a gate of the fourth transistor is connected to the third scan signal terminal, a first pole of the fourth transistor is connected to the second power source terminal, and a second pole of the fourth transistor is connected to the detection signal line.

In some of the possible implementations of the present invention,

the voltage control module comprises a fifth transistor, wherein the grid electrode of the fifth transistor is connected with the control signal end, the first electrode of the fifth transistor is connected with the first power supply end, and the second electrode of the fifth transistor is connected with the first node;

the writing submodule comprises a first transistor, the grid electrode of the first transistor is connected with a first scanning signal end, the first pole of the first transistor is connected with a data signal end, and the second pole of the first transistor is connected with a third node;

the driving sub-module comprises a third transistor, the grid electrode of the third transistor is connected with a third node, the first pole of the third transistor is connected with the second node, and the second pole of the third transistor is connected with the first node;

the sensing submodule comprises a second transistor, the grid electrode of the second transistor is connected with a second scanning signal end, the first pole of the second transistor is connected with a second node, and the second pole of the second transistor is connected with a detection signal line;

the storage submodule comprises a storage capacitor, a first polar plate of the storage capacitor is connected with the third node, and a second polar plate of the storage capacitor is connected with the second node;

the switch module comprises a fourth transistor, the grid electrode of the fourth transistor is connected with the third scanning signal end, the first pole of the fourth transistor is connected with the second power supply end, and the second pole of the fourth transistor is connected with the detection signal line.

In some possible implementations, the pixel circuit further includes:

the first switch submodule is respectively connected with the detection signal line and the fourth node and is configured to enable the detection signal line to be communicated with the fourth node under the control of a first switch signal;

the sampling submodule is respectively connected with the fourth node and the third power supply end and is configured to store the charge of the fourth node;

and the second switch submodule is respectively connected with the fourth node and the input end of the analog-to-digital conversion circuit and is configured to provide the charges stored by the sampling submodule to the analog-to-digital conversion circuit under the control of a second switch signal.

In some possible implementation manners, the display device further includes a control signal generation module, where the control signal generation module includes a first input terminal, a second input terminal, and an output terminal, the first input terminal is connected to the first scan signal terminal, the second input terminal is connected to the first switch signal, and the output terminal is connected to the control signal terminal.

In some possible implementations, the voltage control module includes a fifth transistor, the fifth transistor is an NMOS transistor, the control signal generation module includes a first level shift sub-circuit, a first not gate, a first or gate, the input end of the first level conversion sub-circuit is connected with a first scanning signal end, the output end of the first level conversion sub-circuit is connected with the input end of the first NOT gate, the input end of the first NOT gate is connected with the first input end of the first OR gate, the second input end of the first OR gate is connected with a first switch signal, the output end of the first OR gate is connected with the input end of the second level conversion sub-circuit, the output end of the second level conversion sub-circuit is connected with the input end of the second NOT gate, the output end of the second NOT gate is connected with the input end of the third NOT gate, and the output end of the third NOT gate is connected with a control signal end.

In some possible implementations, the voltage control module includes a fifth transistor, the fifth transistor is an NMOS transistor, the control signal generation module includes a fourth not gate, a second or gate, and a third level shift sub-circuit, an input terminal of the fourth not gate is connected to the first scan signal terminal, an output terminal of the fourth not gate is connected to the first input terminal of the second or gate, a second input terminal of the second or gate is connected to the first switch signal, an output terminal of the second or gate is connected to an input terminal of the third level shift sub-circuit, and an output terminal of the third level shift sub-circuit is connected to the control signal terminal.

In some possible implementations, the voltage control module includes a fifth transistor, the fifth transistor is a PMOS transistor, the control signal generation module includes a fifth not gate, a third or gate, a sixth not gate, and a fourth level shift sub-circuit, an input terminal of the fifth not gate is connected to the first scan signal terminal, an output terminal of the fifth not gate is connected to the first input terminal of the third or gate, a second input terminal of the third or gate is connected to the first switch signal, an output terminal of the third or gate is connected to an input terminal of the sixth not gate, an output terminal of the sixth not gate is connected to an input terminal of the fourth level shift sub-circuit, and an output terminal of the fourth level shift sub-circuit is connected to the control signal terminal.

As a second aspect of the embodiments of the present disclosure, an embodiment of the present disclosure provides a driving method of a pixel circuit, which is applied to the pixel circuit in any one of the embodiments of the present disclosure above, and the driving method includes:

in the data writing stage, the voltage control module is cut off under the action of the control signal end; the switch module supplies the voltage of the second power supply end to the detection signal line under the control of the third scanning signal end; the driving module receives data voltage of a data signal end under the control of a first scanning signal end and a second scanning signal end, provides an electric signal of a detection signal line for a second node, and provides an electric signal of the second node for a first node;

in the light-emitting stage, the voltage control module provides the voltage of the first power supply end to the first node under the control of the control signal end; the driving module provides an electric signal to the second node based on the voltage of the first node to drive the light emitting module to emit light.

In some possible implementations, the drive module includes a write submodule, a sense submodule, and a drive submodule,

in the data writing stage, the writing sub-module provides data voltage of a data signal end to a third node under the control of a first scanning signal end; the sensing submodule provides an electric signal of a second node to the second node under the control of a second scanning signal end; the driving submodule provides the electrical signal of the second node to the first node under the control of the third node.

As a third aspect of the embodiments of the present disclosure, embodiments of the present disclosure provide a display device including the pixel circuit in any one of the embodiments of the present disclosure.

According to the technical scheme of the embodiment of the disclosure, in the data writing stage, the voltage control module can control the first power supply terminal VDD not to provide voltage for the first node, so that the first node floats. The switching module may be configured to supply the voltage of the second power source terminal VSS to the detection signal line under the control of the third scan signal terminal; the driving module may be configured to provide the electrical signal of the detection signal line to the second node and provide the electrical signal of the second node to the first node under the control of the first scan signal terminal and the second scan signal terminal. Therefore, in the data writing stage, the first node and the second node are both pulled low, the voltage between the first node and the second node at the two ends of the driving module is close to 0V, the current passing through the driving module is 0, the complete reset of the second node is realized, the total current for simultaneously resetting pixels in one row is 0, the influence of the current of the second node on the second power supply end VSS is avoided, the second node is further prevented from being interfered by other pixels in the same row, the influence on the final light-emitting current of the light-emitting module is avoided, and the display effect is improved.

The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present disclosure will be readily apparent by reference to the drawings and following detailed description.

Drawings

In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are not to be considered limiting of its scope.

FIG. 1 is a diagram of a control circuit for a row of pixels in a display device;

FIG. 2 is a schematic diagram of a column of pixels being affected by data voltages of other columns of pixels at a given data voltage;

FIG. 3 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a pixel circuit according to another embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a pixel circuit according to another embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a pixel circuit according to another embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure;

FIG. 9 is a schematic diagram of a pixel circuit according to another embodiment of the present disclosure;

FIG. 10 is a timing diagram illustrating operation of a pixel circuit according to an embodiment of the present disclosure;

fig. 11 is a schematic structural diagram of a pixel circuit according to an embodiment of the disclosure;

fig. 12 is a schematic structural diagram of a control signal generating module in a pixel circuit according to an embodiment of the disclosure;

fig. 13 is a schematic structural diagram of a control signal generation module in a pixel circuit according to another embodiment of the disclosure;

FIG. 14 is a timing diagram of the control signal generation module shown in FIG. 12 or FIG. 13;

fig. 15 is a schematic structural diagram of a control signal generation module in a pixel circuit according to another embodiment of the disclosure;

FIG. 16 is a timing diagram of the control signal generation module shown in FIG. 15;

FIG. 17 is a diagram illustrating a control circuit for a row of pixels in a display device according to an embodiment of the present disclosure;

FIG. 18 is a diagram illustrating a control circuit for n rows of pixels in a display device according to an embodiment of the present disclosure;

FIG. 19 is a diagram illustrating a control circuit for n rows of pixels in a display device according to another embodiment of the present disclosure;

FIG. 20 is a diagram illustrating a column of pixels affected by data voltages of other columns of pixels at a given predetermined data voltage in a display device according to an embodiment of the present disclosure.

Description of reference numerals:

10. a voltage control module; 20. a drive module; 21. writing the submodule; 22. a drive sub-module; 23. a storage submodule; 24. a sensing sub-module; 30. a switch module; 40. a light emitting module; 50. a sampling submodule; 61. a first switch submodule; 62. a second switch submodule; 70. an analog-to-digital conversion circuit; 80. a control signal generation module; 811. a first level shift sub-circuit; 812. a second level shift sub-circuit; 813. a third level shift sub-circuit; 821. a first not gate; 822. a second not gate; 823. a third not gate; 824. a fourth not gate; 825. a fifth not gate; 826. a sixth not gate; 831. a first OR gate; 832. a second OR gate; 833. and a third or gate.

Detailed Description

In the following, only certain exemplary embodiments are briefly described. As those skilled in the art can appreciate, the described embodiments can be modified in various different ways, without departing from the spirit or scope of the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

The present disclosure describes embodiments, but the description is illustrative rather than limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described in the present disclosure. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or instead of any other feature or element in any other embodiment, unless expressly limited otherwise.

The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements provided by the present disclosure may also be combined with any conventional features or elements to form a unique inventive aspect as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive aspects to form yet another unique inventive aspect, as defined by the claims. Thus, it should be understood that any features shown and/or discussed in this disclosure may be implemented alone or in any suitable combination. Accordingly, the embodiments are not limited except as by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

Further, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps herein, the method or process should not be limited to the particular sequence of steps herein. Other orders of steps are possible as will be understood by those of ordinary skill in the art. Therefore, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Further, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present disclosure.

Unless otherwise defined, technical or scientific terms used in the disclosure of the embodiments of the present disclosure should have the ordinary meaning as understood by those having ordinary skill in the art to which the present invention belongs. The use of "first," "second," and similar language in the embodiments of the present invention does not denote any order, quantity, or importance, but rather the terms "first," "second," and similar language are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It will be understood by those skilled in the art that the switching transistor and the driving transistor employed in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices having the same characteristics. Preferably, the thin film transistor used in the embodiment of the present invention may be an oxide semiconductor transistor. Since the source and drain of the switching transistor used here are symmetrical, the source and drain can be interchanged. In the embodiment of the present invention, in order to separate the two poles of the switching transistor except the gate, one of the electrodes is referred to as a first pole, the other electrode is referred to as a second pole, the first pole may be a source or a drain, and the second pole may be a drain or a source.

Herein, the coupling may include: the two ends are electrically connected or the two ends are directly connected (for example, the two ends are connected through a signal wire). The coupling between the two ends is not limited herein.

The active level refers to a level at which the transistor can be turned on, the inactive level refers to a level at which the transistor can be turned off, and when the transistor is a P-type transistor, the active level is low and the inactive level is high, and when the transistor is an N-type transistor, the active level is high and the inactive level is low.

The OLED display device comprises a display panel, a grid driving device, a data driving device and a time schedule controller. The display panel includes data lines, gate lines, and pixels controlled by the data lines and the gate lines. The display panel operates such that when a gate driving signal is supplied to the gate lines, pixels in a certain row are supplied with data voltages to the data lines, and the pixels emit light of different brightness according to the magnitude of the data voltages.

The gate driving device supplies a gate driving signal to the gate line, and the gate driving device includes a separate gate driving integrated circuit or a panel gate driving circuit. The single gate driving integrated circuit is disadvantageous to a narrow frame and low cost, and thus, the panel gate driving circuit is receiving more and more attention.

The panel gate driving circuit determines the circuit driving manner according to the process (such as oxide, LTPS, etc.), but the basic principle is similar to that of a separate gate driving integrated circuit.

FIG. 1 is a diagram of a control circuit for a row of pixels in a display device. The pixel circuit is exemplified by a 3T1C circuit, in which an NMOS is exemplified. As shown in fig. 1, the display device includes m columns of pixels, and the 3T1C pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor C_st. The gate of the first transistor T1 is connected to the first scan signal terminal G1, the first pole of the first transistor T1 is connected to the data line DL, the data line DL provides the data voltage, and the second pole of the first transistor T1 is connected to the gate of the third transistor T3. A first electrode of the third transistor T3 is connected to the first power source terminal VDD, and a second electrode of the third transistor T3 is connected to the anode of the OLED. The first plate of the storage capacitor Cst is connected to the gate of the third transistor T3, and the second plate of the storage capacitor Cst is connected to the anode of the OLED. A gate of the second transistor T2 is connected to the second scan signal terminal G2, a first pole of the second transistor T2 is connected to an anode of the OLED, and a second pole of the second transistor T2 is connected to the sensing signal line Sense. The cathode of the OLED is connected to a third power supply terminal GND.

The pixel circuit may further include a fourth transistor T4, a gate of the fourth transistor T4 being connected to the third scan signal terminal G3, a first pole of the fourth transistor T4 being connected to the second power source terminal VSS, and a second pole of the fourth transistor T4 being connected to the detection signal line Sense.

In the data writing stage, the first transistor T1 is turned on under the control of the first scan signal terminal G1, the second transistor T2 is turned on under the control of the second scan signal terminal G2, the fourth transistor T4 is turned on under the control of the third scan signal terminal G3, the first power source terminal VDD, the third transistor T3, the second transistor T2, the fourth transistor T4 and the second power source terminal VSS form a path, and the second pole S of the third transistor T3 has a reset current. In this way, on a large-sized Thin Film Transistor (TFT) device, the Vgs variation caused by the interference of the second pole S of the third transistor T3 by other column pixels is not significant due to the low overall reset current, the low TFT transconductance, and the high RC on the line. However, when the circuit shown in fig. 1 is applied to the silicon-based micro display, since the NMOS has a substrate bias effect, the current during reset is very large, the transconductance of the NMOS itself is large, and the reset current of the second pole S of the third transistor T3 affects the voltage of the second power source terminal VSS, thereby affecting other columns of pixels in the same row, so that the second pole S of the third transistor T3 is interfered by other pixels, and further greatly affecting the final light-emitting current.

Fig. 2 is a schematic diagram of a column of pixels being affected by data voltages of other columns of pixels at a given data voltage. For example, one row has 4000 sub-pixels, and given a certain column (e.g., the first column) of pixel data voltages Vdata, the other 3999 columns of pixel data voltages Vdata vary versus the column of pixel current variation curves. It can be seen from the graph that the conventional 3T1C circuit is not suitable for silicon-based microdisplays.

The embodiment of the disclosure provides a pixel circuit, which can avoid the influence of other columns of pixels on a column of pixels when data is written on the column of pixels, and is beneficial to being applied to a silicon-based micro display device.

Fig. 3 is a schematic structural diagram of a pixel circuit according to an embodiment of the disclosure. As shown in fig. 3, the pixel circuit may include a voltage control module 10, a driving module 20, and a switching module 30.

The voltage control block 10 is connected to the first power terminal VDD, the control signal terminal EM, and the first node N1, respectively, and is configured to supply the voltage of the first power terminal VDD to the first node N1 under the control of the control signal terminal EM. It is to be understood that, in the case where the level provided by the control signal terminal EM is an active level, the voltage control block 10 provides the voltage of the first power terminal VDD to the first node N1; in case that the level supplied from the control signal terminal EM is an inactive level, the voltage control block 10 disconnects between the first power source terminal VDD and the first node N1, the voltage control block 10 cannot supply the voltage of the first power source terminal VDD to the first node N1, and the first node N1 is in a floating state.

The driving module 20 is respectively connected to the data signal terminal DL, the first scan signal terminal G1, the second scan signal terminal G2, the first node N1, the second node N2 and the sensing signal line Sense. The driving module 20 is configured to receive a data voltage of the data signal terminal DL under the control of the first scan signal terminal G1 and supply an electrical signal to the second node N2 to drive the light emitting module 40 to emit light based on the voltage of the first node N1, or the driving module 20 is configured to supply an electrical signal of the sensing signal line Sense to the second node N2 and supply an electrical signal of the second node N2 to the first node N1 under the control of the first scan signal terminal G1 and the second scan signal terminal G2;

the switching module 30 is connected to the third scan signal terminal G3, the sensing signal line Sense, and the second power source terminal VSS, respectively, and is configured to supply the voltage of the second power source terminal VSS to the sensing signal line Sense under the control of the third scan signal terminal G3.

In the pixel circuit according to the embodiment of the disclosure, in the data writing phase, the voltage control module 10 may control the first power terminal VDD not to provide a voltage to the first node N1, so that the first node N1 floats. The switching module 30 may be configured to supply the voltage of the second power source terminal VSS to the detection signal line Sense under the control of the third scan signal terminal G3; the driving module 20 may be configured to supply the electric signal of the sensing signal line Sense to the second node N2 and the electric signal of the second node N2 to the first node N1 under the control of the first and second scan signal terminals G1 and G2. Therefore, in the data writing stage, the first node N1 and the second node N2 are both pulled low, the voltage between the first node N1 and the second node N2 at the two ends of the driving module 20 is close to 0V, the current passed by the driving module 20 is 0, the complete reset of the second node N2 is realized, the total current for simultaneously resetting pixels in one row is 0, the influence of the current of the second node N2 on the second power supply terminal VSS is avoided, the second node N2 is further prevented from being interfered by other pixels in the same row, the influence on the final light-emitting current of the light-emitting module 40 is avoided, and the display effect is improved.

The pixel circuit of the embodiment of the disclosure realizes that the total current of one row of pixels is reset to 0 at the same time, and is favorable for being applied to a silicon-based micro display device.

Fig. 4 is a schematic structural diagram of a pixel circuit according to an embodiment of the disclosure. As shown in fig. 4, the driving module 20 may include a writing sub-module 21, a driving sub-module 22, a storage sub-module 23, and a sensing sub-module 24.

The write submodule 21 is respectively connected to the first scan signal terminal G1, the data signal terminal DL, and the third node N3, and is configured to supply the data voltage of the data signal terminal DL to the third node N3 under the control of the first scan signal terminal G1.

The driving sub-module 22 is respectively connected to the third node N3, the first node N1 and the second node N3, and is configured to provide an electrical signal to the second node N2 under the control of the third node N3 to drive the light emitting module 40 to emit light, or to provide an electrical signal to the second node N2 under the control of the third node N3 to the first node N1.

The storage submodule 23 is connected to the third node N3 and the second node N3, respectively, and is configured to store the charge of the third node N3.

The sensing sub-module 24 is respectively connected to the second scan signal terminal G2, the second node N2, and the Sense signal line Sense, and is configured to supply the electrical signal of the second node N2 to the Sense signal line Sense under the control of the second scan signal terminal G2, or to supply the electrical signal of the Sense signal line Sense to the second node N2 under the control of the second scan signal terminal G2.

In the driving module 20 in the pixel circuit of the embodiment of the disclosure, in the data writing phase, the driving submodule 22 may be configured to provide the electrical signal of the second node N2 to the first node N1 under the control of the third node N3; the sensing sub-module 24 may be configured to provide the electrical signal of the detection signal line G4 to the second node N2 under the control of the second scan signal terminal G2; the switching module 30 may be configured to supply an electrical signal of the second power source terminal VSS to the detection signal line Sense under the control of the third scan signal terminal G3. Therefore, in the data writing stage, the first node N1 and the second node N2 are both pulled low, the voltage between the first node N1 and the second node N2 at the two ends of the driving submodule 22 is close to 0V, the current passing through the driving submodule 22 is 0, the complete reset of the second node N2 is realized, the total current for simultaneously resetting a row of pixels is 0, the influence of the current of the second node N2 on the second power supply terminal VSS is avoided, the second node N2 is further prevented from being interfered by other columns of pixels in the same row, the influence on the final light-emitting current of the light-emitting module 40 is avoided, and the display effect is improved.

Fig. 5 is a schematic structural diagram of a pixel circuit according to another embodiment of the disclosure. In one embodiment, as shown in fig. 5, the voltage control module 10 may include a fifth transistor T5, a gate of the fifth transistor T5 may be connected to the control signal terminal EM, a first pole of the fifth transistor T5 may be connected to the first power terminal VDD, and a second pole of the fifth transistor T5 may be connected to the first node N1. The fifth transistor T5 is configured to supply the voltage of the first power source terminal VDD to the first node N1 under the control of the control signal terminal EM. Illustratively, in case that the control signal terminal EM is at an active level, the fifth transistor T5 is turned on, supplying the voltage of the first power source terminal VDD to the first node N1; in the case where the control signal terminal EM is at the inactive level, the fifth transistor T5 is turned off, leaving the first node N1 in a floating state.

Exemplarily, an exemplary structure of the voltage control module is shown in fig. 5, and it can be understood by those skilled in the art that the voltage control module is not limited to the structure shown in fig. 5 as long as the function thereof can be achieved.

Fig. 6 is a schematic structural diagram of a pixel circuit according to another embodiment of the disclosure. In one embodiment, as shown in fig. 6, the write sub-module 21 may include a first transistor T1, a gate of the first transistor T1 may be connected to the first scan signal terminal G1, a first pole of the first transistor T1 may be connected to the data signal terminal DL, and a second pole of the first transistor T1 may be connected to the third node N3. The first transistor T1 is configured to supply the data voltage of the data signal terminal DL to the third node N3 under the control of the first scan signal terminal G1.

Illustratively, the driving sub-module 22 may include a third transistor T3, a gate of the third transistor T3 being connected to a third node N3, a second pole of the third transistor T3 being connected to a first node N1, and a first pole of the third transistor T3 being connected to a second node N2. The third transistor T3 is configured to provide an electrical signal to the second node N2 under the control of the third node N3 to drive the light emitting module 40 to emit light.

Illustratively, the storage submodule 23 may include a storage capacitor Cst, a first plate of the storage capacitor Cst being connected to the third node N3, a second plate of the storage capacitor Cst being connected to the second node N2, the storage capacitor Cst being configured to store the charge of the third node N3.

For example, the sensing sub-module 24 may include a second transistor T2, a gate of the second transistor T2 may be connected to the second signal scan terminal G2, a first pole of the second transistor T2 may be connected to the second node N2, and a first pole of the second transistor T2 may be connected to the sensing signal line Sense. The second transistor T2 is configured to supply the electric signal of the second node N2 to the sensing signal line Sense under the control of the second scan signal terminal G2, or to supply the electric signal of the sensing signal line G4 to the second node N2 under the control G2 of the second scan signal terminal G2. For example, in the data writing stage, the second transistor T2 supplies an electric signal of the sensing signal line Sense to the second node N2 under the control of the second scan signal terminal G2; during the sampling period during Blank, the second transistor T2 supplies the electric signal of the second node N2 to the sensing signal line Sense under the control of the second scan signal terminal G2.

In one embodiment, the first pole of the light emitting module 40 is connected to the second node N2, and the second pole of the light emitting module 40 is connected to the third power terminal GND, and illustratively, the first pole of the light emitting module 40 may be an anode and the second pole of the light emitting module 40 may be a cathode.

Exemplarily, the light emitting module 40 may be an OLED. It is understood that the light emitting module 40 is not limited to the OLED, and in other embodiments, the light emitting module 40 may be a QLED, an LED, or the like.

It should be noted that fig. 6 shows an exemplary structure of the writing sub-module 21, the driving sub-module 22, the storage sub-module 23, and the sensing sub-module 24, and those skilled in the art can understand that the writing sub-module 21, the driving sub-module 22, the storage sub-module 23, and the sensing sub-module 24 are not limited to the structure shown in fig. 6 as long as the functions thereof can be realized.

The driving module 20 shown in fig. 6 has a structure of 3T1C, and it is understood that the driving module 20 is not limited to the structure of 3T1C, and may also have a structure of 4T1C, 5T1C, 6T1C, 7T1C, or 8T 1C.

Fig. 7 is a schematic structural diagram of a pixel circuit in another embodiment of the present disclosure. In one embodiment, as shown in fig. 7, the switch module 30 may include a fourth transistor T4, a gate of the fourth transistor T4 being connected to the third scan signal terminal G3, a first pole of the fourth transistor T4 being connected to the second power source terminal VSS, and a second pole of the fourth transistor T4 being connected to the sensing signal line Sense. The fourth transistor T4 is configured to supply the voltage of the second power source terminal VSS to the detection signal line Sense under the control of the third scan signal terminal G3.

It should be noted that fig. 7 shows an exemplary structure of the switch module 30, and those skilled in the art will understand that the switch module is not limited to the structure shown in fig. 7 as long as the function thereof can be achieved.

Fig. 8 is a schematic structural diagram of a pixel circuit according to an embodiment of the disclosure. In one embodiment, as shown in fig. 8, the voltage control module 10 may include a fifth transistor T5, a gate of the fifth transistor T5 may be connected to the control signal terminal EM, a first pole of the fifth transistor T5 may be connected to the first power source terminal VDD, and a second pole of the fifth transistor T5 may be connected to the first node N1. The fifth transistor T5 is configured to supply the voltage of the first power source terminal VDD to the first node N1 under the control of the control signal terminal EM. Illustratively, in case that the control signal terminal EM is at an active level, the fifth transistor T5 is turned on, supplying the voltage of the first power source terminal VDD to the first node N1; in the case where the control signal terminal EM is at the inactive level, the fifth transistor T5 is turned off, leaving the first node N1 in a floating state.

The write submodule 21 may include a first transistor T1, a gate of the first transistor T1 may be connected to the first scan signal terminal G1, a first pole of the first transistor T1 may be connected to the data signal terminal DL, and a second pole of the first transistor T1 may be connected to the third node N3. The first transistor T1 is configured to supply the data voltage of the data signal terminal DL to the third node N3 under the control of the first scan signal terminal G1.

The driving sub-module 22 may include a third transistor T3, a gate of the third transistor T3 being connected to a third node N3, a second pole of the third transistor T3 being connected to the first node N1, and a first pole of the third transistor T3 being connected to the second node N2. The third transistor T3 is configured to provide an electrical signal to the second node N2 under the control of the third node N3 to drive the light emitting module 40 to emit light.

The storage sub-module 23 may include a storage capacitor Cst, a first plate of the storage capacitor Cst being connected to the third node N3, a second plate of the storage capacitor Cst being connected to the second node N2, the storage capacitor Cst being configured to store a charge of the third node N3.

The sensing sub-module 24 may include a second transistor T2, a gate of the second transistor T2 may be connected to the second signal scan terminal G2, a first pole of the second transistor T2 may be connected to the second node N2, and a first pole of the second transistor T2 may be connected to the sensing signal line Sense. The second transistor T2 is configured to supply the electric signal of the second node N2 to the sensing signal line Sense under the control of the second scan signal terminal G2, or to supply the electric signal of the sensing signal line G4 to the second node N2 under the control G2 of the second scan signal terminal G2. For example, in the data writing stage, the second transistor T2 supplies an electric signal of the sensing signal line Sense to the second node N2 under the control of the second scan signal terminal G2; during the sampling period during Blank, the second transistor T2 supplies the electric signal of the second node N2 to the sensing signal line Sense under the control of the second scan signal terminal G2.

The first pole of the light emitting module 40 is connected to the second node N2, the second pole of the light emitting module 40 may be connected to the third power terminal GND, and the first pole of the light emitting module 40 may be an anode and the second pole of the light emitting module 40 may be a cathode, for example. The light emitting module 40 may be an OLED.

The switching module 30 may include a fourth transistor T4, a gate of the fourth transistor T4 being connected to the third scan signal terminal G3, a first pole of the fourth transistor T4 being connected to the second power source terminal VSS, and a second pole of the fourth transistor T4 being connected to the sensing signal line Sense. The fourth transistor T4 is configured to supply the voltage of the second power source terminal VSS to the detection signal line Sense under the control of the third scan signal terminal G3.

In one embodiment, the voltage of the second power source terminal VSS is less than the voltage of the first power source terminal VDD, and the voltage of the second power source terminal VSS may be 0V or 1V.

Fig. 9 is a schematic structural diagram of a pixel circuit in another embodiment of the present disclosure. In one embodiment, as shown in fig. 9, the pixel circuit may further include a first switch submodule 61, a sampling submodule 50, and a second switch submodule 62. The first switching submodule 61 is connected to the Sense signal line Sense and the fourth node N4, respectively, and is configured to supply an electric signal of the Sense signal line Sense to the fourth node N4 under the control of a first switching signal SW 0.

The first plate of the sampling submodule 50 is connected to the fourth node N4, and the second plate of the sampling submodule 50 is connected to the third power terminal VDD, and is configured to store the charge of the fourth node N4. A second switch submodule 62. Illustratively, the sampling submodule 50 may include a sampling capacitor C having a first plate connected to the fourth node N4 and a second plate connected to the third power source terminal VDD.

The second switch submodule 62 is respectively connected to the fourth node N4 and an input terminal of the analog-to-digital conversion circuit 70, and is configured to supply the analog-to-digital conversion circuit 70 with the charges stored by the sampling submodule 50 under the control of a second switch signal SW 1. Illustratively, the second switching submodule 62 is configured to provide the charge stored by the sampling submodule 50 to the analog-to-digital conversion circuit 70 through the fourth node N4 under control of a second switching signal AW 1.

It is understood that the analog-to-digital conversion circuit 70 may adopt an analog-to-digital conversion circuit structure conventional in the art, and the analog-to-digital conversion circuit 70 is connected with the pixel compensation circuit so as to perform voltage compensation on the pixel. The first switch submodule 61 and the second switch submodule 62 may employ devices having a switching function, such as thin film transistors, etc., which are commonly used in the art, as long as the first switch submodule 61 can provide the electric signal of the detection signal line Sense to the fourth node N4 under the control of the first switch signal SW0, and the second switch submodule 62 can provide the electric charge stored in the sampling submodule 50 to the analog-to-digital conversion circuit 70 under the control of the second switch signal SW 1.

Fig. 10 is a timing diagram of the operation of the pixel circuit according to the embodiment of the disclosure, which is illustrated by taking a certain column of pixels in the ith row as an example. It is understood that the Display device includes a Display (Display) period and a Blank (Blank) period.

The display period includes a first phase t1 (also called a write data phase), in the first phase t1, as shown in fig. 10, the first scan signal terminal G1 is at an active level, the second scan signal terminal G2 is at an active level, the control signal terminal EM is at an inactive level, the third scan signal terminal G3 is at an active level, and the first switch signal SW0 is at an inactive level.

The voltage control block 10 is turned off by an inactive level of the control signal terminal EM and the first node N1 is floated.

The switching module 30 supplies the voltage of the second power source terminal VSS to the detection signal line Sense under the control of the third scan signal terminal G3.

The driving module 20 supplies the electric signal of the sensing signal line Sense to the second node N2 and the electric signal of the second node N2 to the first node N1 under the control of the first and second scan signal terminals G1 and G2, so that the first and second nodes N1 and N2 are simultaneously pulled low. Vds of the third transistor T3 is close to 0V and a current between the first pole and the second pole of the third transistor is 0. Thus, the complete reset of the second node N2 is realized, the total current for simultaneously resetting pixels in one row is 0, the influence of the current of the second node N2 on the second power supply terminal VSS is avoided, the second node N2 is further prevented from being interfered by pixels in other columns in the same row, the influence on the final light-emitting current of the light-emitting module 40 is avoided, and the display effect is improved.

Illustratively, in the first stage t1, the write submodule 21 supplies the data voltage of the data signal terminal DL to the third node N3 under the control of the first scan signal terminal G1, and the storage submodule 23 stores the charge of the third node N3. The switching module 30 supplies the voltage of the second power source terminal VSS to the detection signal line Sense under the control of the third scan signal terminal G3; the sensing sub-module 24 supplies an electric signal of the detection signal line Sense to the second node N2 under the control G2 of the second scan signal terminal; the driving sub-module 22 provides the electrical signal of the second node N2 to the first node N1 under the control of the third node N3.

The display period further includes a second period t2 (also called a light-emitting period), in which the first scan signal terminal G1 is at an inactive level, the second scan signal terminal G2 is at an inactive level, the control signal terminal EM is at an active level, the third scan signal terminal G3 is at an active level, and the first switch signal SW0 is at an inactive level, at the second period t 2.

In the second stage t2, the voltage control module 10 supplies the voltage of the first power terminal VDD to the first node N1 under the control of the control signal terminal EM. The driving module 20 supplies an electrical signal to the second node N2 to drive the light emitting module 40 to emit light based on the voltage of the first node N1.

Illustratively, in the second stage t2, the write submodule 21 is turned off by the inactive level of the first scan signal terminal G1, and the sense submodule 24 is turned off by the inactive level of the second scan signal terminal G2. The driving sub-module 22 supplies a voltage to the second node N2 to drive the light emitting module 40 to emit light based on the voltage of the first node N1 under the action of the third node N3.

The blank period includes a reset phase t3 and a sampling phase t 4. During the blank period, the control signal terminal EM is maintained at the active level, and the voltage control block 10 supplies the voltage of the first power terminal VDD to the first node N1 under the control of the control signal terminal EM.

In the reset phase t3, as shown in fig. 10, the first scan signal terminal G1 is at an active level, the second scan signal terminal G2 is at an active level, the third scan signal terminal G3 is at an active level, and the first switch signal SW0 is at an active level. The write submodule 21 supplies the data voltage of the data signal terminal DL to the third node N3 under the control of the first scan signal terminal G1; the switching module 30 supplies the voltage of the second power source terminal VSS to the detection signal line Sense under the control of the third scan signal terminal G3; the sensing submodule 24 provides the voltage of the sensing signal line Sense to the second node N2 under the control of the second scan signal terminal G2, and thus resets the second node N2. The first switch submodule 61 provides the electric signal of the detection signal line Sense to the fourth node N4 under the control of the first switch signal SW0, and resets the sampling submodule 50.

In the sampling period t4, as shown in fig. 10, the first scan signal terminal G1 is at an active level, the second scan signal terminal G2 is at an active level, the third scan signal terminal G3 is at an inactive level, and the first switch signal SW0 is at an active level. The switching module 30 is turned off by the inactive level of the third scan signal terminal G3. The write submodule 21 supplies the data voltage of the data signal terminal DL to the third node N3 under the control of the first scan signal terminal G1; the driving sub-module 22 supplies an electric signal to the second node N2 based on the voltage of the first node N1 under the control of the third node N3; the sensing sub-module 24 supplies the electric signal of the second node N2 to the detection signal line Sense under the control G2 of the second scan signal terminal; the first switch submodule 61 provides the electric signal of the detection signal line Sense to the fourth node N4 under the control of the first switch signal SW0, so that the driving submodule 22 charges the sampling submodule 50, the sampling submodule 50 performs sampling, and the detection of the threshold voltage Vth of the driving submodule 22 is completed.

In the embodiment of the present disclosure, after the compensation voltage Vref is given during the blanking period, the active level of the first scan signal terminal G1, the active level of the second scan signal terminal G2 and the active level of the first switch signal SW0 are earlier than the inactive level of the third scan signal terminal G3, so that after the active levels of the first scan signal terminal G1, the second scan signal terminal G2 and the first switch signal SW0 arrive and before the inactive level of the third scan signal terminal G3 arrives, the second node N2 and the sampling sub-module 50 may be reset, thereby improving the sampling accuracy.

In one embodiment, the first scan signal G1 generated from the first scan signal terminal G1, the second scan signal G2 generated from the second scan signal terminal G2, and the control signal EM generated from the control signal terminal EM may be implemented by a shift register.

Fig. 11 is a schematic structural diagram of a pixel circuit according to an embodiment of the disclosure. IN one embodiment, as shown IN fig. 11, the pixel circuit may further include a control signal generating block 80, the control signal generating block 80 including a first input terminal IN1, a second input terminal IN2, and an output terminal, the first input terminal IN1 being connected to the first scan signal terminal G1, the second input terminal IN2 being connected to the first switching signal SW0, and the output terminal of the control signal generating block 80 being connected to the control signal terminal EM. The control signal generating module 80 is used to generate the control signal EM according to the first scan signal terminal G1 and the first switch signal SW0, thereby reducing the number of shift registers and simplifying the digital driving circuit.

It is understood that in other embodiments, a synchronization signal (V-Sync signal) may be used instead of the first switch signal SW0, and the control signal EM may be generated as well.

Fig. 12 is a schematic structural diagram of a control signal generation module in a pixel circuit according to an embodiment of the disclosure. As shown in fig. 12, the control signal generation module 80 may include a first level shift sub-circuit 811, a first not gate 821, a first or gate 831, a second level shift sub-circuit 812, a second not gate 822, and a third not gate 823. An input end of the first level shift sub-circuit 811 is connected to the first scan signal end G1, an output end of the first level shift sub-circuit 811 is connected to an input end of the first not gate 821, an input end of the first not gate 821 is connected to a first input end of the first or gate 831, a second input end of the first or gate 831 is connected to the first switch signal SW0, an output end of the first or gate 831 is connected to an input end of the second level shift sub-circuit 812, an output end of the second level shift sub-circuit 812 is connected to an input end of the second not gate 822, an output end of the second not gate 822 is connected to an input end of the third not gate 823, an output end of the third not gate 823 is connected to the control signal end EM, and an output end of the third not gate 823 outputs the control signal EM to the control signal end EM.

Fig. 13 is a schematic structural diagram of a control signal generation module in a pixel circuit according to another embodiment of the disclosure. As shown in fig. 13, the control signal generating module 80 may include a fourth not gate 824, a second or gate 832, and a third level shift sub-circuit 813, wherein an input terminal of the fourth not gate 824 is connected to the first scan signal terminal G1, an output terminal of the fourth not gate 824 is connected to a first input terminal of the second or gate 832, a second input terminal of the second or gate 832 is connected to the first switch signal SW0, an output terminal of the second or gate 832 is connected to an input terminal of the third level shift sub-circuit 813, an output terminal of the third level shift sub-circuit 813 is connected to the control signal terminal EM, and an output terminal of the third level shift sub-circuit 813 outputs the control signal EM to the control signal terminal EM.

Fig. 14 is a timing diagram of the control signal generation module shown in fig. 12 or 13. As can be seen from fig. 14, with the control signal generation module shown in fig. 12 or fig. 13, the control signal EM may be obtained based on the first scan signal G1 and the first switch signal SW 0.

In one embodiment, in the case that the fifth transistor T5 is an NMOS transistor, the control signal generating module may have a structure as shown in fig. 12 or 13.

Fig. 15 is a schematic structural diagram of a control signal generation module in a pixel circuit according to another embodiment of the disclosure. As shown in fig. 15, the control signal generating module 80 may include a fifth not gate 825, a third or gate 833, a sixth not gate 826 and a fourth level shifter sub-circuit 814, an input terminal of the fifth not gate 825 is connected to the first scan signal terminal G1, an output terminal of the fifth not gate 825 is connected to a first input terminal of the third or gate 833, a second input terminal of the third or gate 833 is connected to the first switch signal SW0, an output terminal of the third or gate 833 is connected to an input terminal of the sixth not gate 826, an output terminal of the sixth not gate 826 is connected to an input terminal of the fourth level shifter sub-circuit 814, an output terminal of the fourth level shifter sub-circuit 814 is connected to the control signal terminal EM, and an output terminal of the fourth level shifter sub-circuit 814 outputs the control signal EM to the control signal terminal EM.

Fig. 16 is a timing diagram of the control signal generation module shown in fig. 15. As can be seen from fig. 16, with the control signal generation module shown in fig. 15, the control signal EM may be obtained based on the first scan signal G1 and the first switch signal SW 0.

In one embodiment, in the case that the fifth transistor T5 is a PMOS transistor, the control signal generating module may have a structure as shown in fig. 15.

It is understood that the first level shift sub-circuit 811, the second level shift sub-circuit 812 and the third level shift sub-circuit 813 can be implemented by using a level shift sub-circuit conventional in the art, and will not be described herein.

It should be noted that, in the embodiment of the present disclosure, each transistor may be an NMOS transistor or a PMOS transistor, which can unify process flows, reduce the process of the OLED display device, and is beneficial to improving the yield of the product.

The embodiment of the disclosure also provides a driving method of the pixel circuit, which is suitable for the pixel circuit in any embodiment of the disclosure. The driving method of the pixel circuit may include:

in the data writing stage, the first scan signal terminal G1 is asserted, the second scan signal terminal G2 is asserted, the control signal terminal EM is de-asserted, and the third scan signal terminal G3 is asserted. The voltage control block 10 is turned off by the inactive level of the control signal terminal EM, the voltage control block 10 cannot supply the voltage of the first power source terminal VDD to the first node N1, and the first node N1 floats. The switching module 30 supplies the voltage of the second power source terminal VSS to the detection signal line Sense under the control of the third scan signal terminal G3. The driving module 20 receives the data voltage of the data signal terminal DL under the control of the first scan signal terminal G1 and the second scan signal terminal G2, provides the electrical signal of the sensing signal line Sense to the second node N2, and provides the electrical signal of the second node N2 to the first node N1, so that the first node N1 and the second node N2 are pulled low at the same time.

In the light emitting stage, the first scan signal terminal G1 is at the inactive level, the second scan signal terminal G2 is at the inactive level, the control signal terminal EM is at the active level, and the third scan signal terminal G3 is at the active level. The voltage control block 10 supplies the voltage of the first power terminal VDD to the first node N1 under the control of the control signal terminal EM. The driving module 20 provides an electrical signal to the second node N2 to drive the light emitting module 40 to emit light based on the voltage of the first node N1.

In one embodiment, the driving sub-module may include a writing sub-module 21, a driving sub-module 22, a storage sub-module 23, and a sensing sub-module 24. In the data writing phase, the write submodule 21 supplies the data voltage of the data signal terminal DL to the third node N3 under the control of the first scan signal terminal G1, and the storage submodule 23 stores the charge of the third node N3. The sensing sub-module 24 supplies an electric signal of the detection signal line Sense to the second node N2 under the control G2 of the second scan signal terminal; the driving sub-module 22 provides the electrical signal of the second node N2 to the first node N1 under the control of the third node N3.

Fig. 17 is a schematic structural diagram of a control circuit for a row of pixels in a display device according to an embodiment of the disclosure. The disclosed embodiment also provides a display device, which may include a plurality of rows of pixels, each row of pixels including m columns of pixels, a control circuit of each row of pixels including a voltage control module, m driving modules and m switching modules, the m driving modules sharing a first node N1, as shown in fig. 17. That is, one voltage control block 10 is shared by one row of pixels. Thus, the structure of the control circuit for each row of pixels can be further simplified.

As shown in fig. 17, the control circuits of one row of pixels share one analog-to-digital conversion circuit 70. It can be understood that, for m columns of pixels in each row of pixels, voltage compensation is performed in sequence, and by controlling SW1 to be turned on in sequence, the analog-to-digital conversion circuit 70 converts the electrical signals stored by the sampling capacitors C corresponding to the pixels in each column into compensation data in sequence to perform pixel voltage compensation.

Fig. 18 is a schematic diagram of a control circuit for n rows of pixels in a display device according to an embodiment of the disclosure. As shown in fig. 18, the display device may include a display area (AA) provided with n rows of pixels, and a non-display area, where one row of pixels shares one voltage control module. As shown in fig. 17, the driving module (e.g., 3T1C circuit in fig. 17) in the pixel circuit corresponding to each pixel is located in the pixel region, and the voltage control module is located in the non-display region, illustratively, the voltage control module is located on the left side of the display region.

Fig. 19 is a schematic diagram of a control circuit for n rows of pixels in a display device according to another embodiment of the disclosure. As shown in fig. 19, the display device may include a display area (AA) and a non-display area, the display area is provided with n rows of pixels, one row of pixels adopts two voltage control modules, and the two voltage control modules may be respectively disposed at both sides of the display area. Illustratively, each row of pixels may be divided into 1 st to i th columns of pixels and i +1 th to m th columns of pixels, the 1 st to i th columns of pixels sharing one of the two voltage control blocks, and the i +1 th to m th columns of pixels sharing the other of the two voltage control blocks. It can be understood that, in a row of pixels, a plurality of voltage control modules may be arranged as required, and the correspondence relationship between the voltage control modules and m columns of pixels may be arranged as required. As shown in fig. 18, the driving module (e.g., 3T1C circuit in fig. 18) in the pixel circuit corresponding to each pixel is located in the pixel region, and the voltage control module is located in the non-display region, and illustratively, two voltage control modules corresponding to one row of pixels are located on the left side and the right side of the display region, respectively.

FIG. 20 is a diagram illustrating a column of pixels affected by data voltages of other columns of pixels at a given predetermined data voltage in a display device according to an embodiment of the present disclosure. After the display device adopts the pixel circuit in the embodiment of the present disclosure, after a preset data voltage is given to a certain column of pixels, the influence of writing different data voltages into other columns on the light emitting current of the column of pixels is simulated, and as a simulation result, as shown in fig. 20, it can be found that when the same data voltage is written into the column of pixels, the light emitting current is constant. It is further proved that the reliability of the pixel circuit in the embodiment of the present disclosure can be better applied to a silicon-based micro display device.

The display device in the embodiments of the present disclosure may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

In the description of the present specification, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present disclosure and to simplify the description, but are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the present disclosure.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present disclosure, "a plurality" means two or more unless specifically limited otherwise.

In the present disclosure, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integral; the connection can be mechanical connection, electrical connection or communication; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.

In the present disclosure, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise the first and second features being in direct contact, or may comprise the first and second features being in contact, not directly, but via another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly above and obliquely above the second feature, or simply meaning that the first feature is at a lesser level than the second feature.

The above disclosure provides many different embodiments or examples for implementing different features of the disclosure. The components and arrangements of specific examples are described above to simplify the present disclosure. Of course, they are merely examples and are not intended to limit the present disclosure. Moreover, the present disclosure may repeat reference numerals and/or reference letters in the various examples, which have been repeated for purposes of simplicity and clarity and do not in themselves dictate a relationship between the various embodiments and/or arrangements discussed.

While the present disclosure has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A pixel circuit, comprising:

the voltage control module is respectively connected with a first power supply end, a control signal end and a first node and is configured to provide the voltage of the first power supply end to the first node under the control of the control signal end;

a driving module, respectively connected to a data signal terminal, a first scanning signal terminal, a second scanning signal terminal, the first node, the second node, and a detection signal line, configured to receive a data voltage of the data signal terminal under the control of the first scanning signal terminal, and provide an electrical signal to the second node to drive the light emitting module to emit light based on the voltage of the first node, or configured to provide an electrical signal of the detection signal line to the second node and provide an electrical signal of the second node to the first node under the control of the first scanning signal terminal and the second scanning signal terminal;

and the switch module is respectively connected with a third scanning signal terminal, the detection signal line and a second power supply terminal and is configured to supply the voltage of the second power supply terminal to the detection signal line under the control of the third scanning signal terminal.

2. The pixel circuit according to claim 1, wherein the voltage control module comprises a fifth transistor, a gate of the fifth transistor is connected to the control signal terminal, a first pole of the fifth transistor is connected to the first power source terminal, and a second pole of the fifth transistor is connected to the first node.

3. The pixel circuit according to claim 1, wherein the driving module comprises:

the write-in submodule is respectively connected with the first scanning signal terminal, the data signal terminal and a third node and is configured to provide a data voltage of the data signal terminal for the third node under the control of the first scanning signal terminal;

a driving sub-module, respectively connected to the third node, the first node and the second node, configured to provide an electrical signal to the second node under the control of the third node to drive the light emitting module to emit light, or configured to provide an electrical signal to the second node under the control of the third node to the first node;

a storage submodule respectively connected to the third node and the second node and configured to store a charge of the third node;

a sensing sub-module respectively connected to a second scan signal terminal, the second node, and the detection signal line, and configured to provide an electrical signal of the second node to the detection signal line under the control of the second scan signal terminal, or configured to provide an electrical signal of the detection signal line to the second node under the control of the second scan signal terminal.

4. The pixel circuit according to claim 3,

the writing submodule comprises a first transistor, the grid electrode of the first transistor is connected with the first scanning signal end, the first pole of the first transistor is connected with the data signal end, and the second pole of the first transistor is connected with the third node; and/or the presence of a gas in the gas,

the driving sub-module comprises a third transistor, wherein the grid electrode of the third transistor is connected with the third node, the first pole of the third transistor is connected with the second node, and the second pole of the third transistor is connected with the first node; and/or the presence of a gas in the gas,

the sensing submodule comprises a second transistor, a grid electrode of the second transistor is connected with the second scanning signal end, a first pole of the second transistor is connected with the second node, and a second pole of the second transistor is connected with the detection signal line.

5. The pixel circuit according to claim 1, wherein the switching module comprises a fourth transistor, a gate of the fourth transistor is connected to the third scan signal terminal, a first pole of the fourth transistor is connected to a second power source terminal, and a second pole of the fourth transistor is connected to the detection signal line.

6. The pixel circuit according to claim 3,

the voltage control module comprises a fifth transistor, a grid electrode of the fifth transistor is connected with the control signal end, a first electrode of the fifth transistor is connected with the first power supply end, and a second electrode of the fifth transistor is connected with the first node;

the writing submodule comprises a first transistor, the grid electrode of the first transistor is connected with the first scanning signal end, the first pole of the first transistor is connected with the data signal end, and the second pole of the first transistor is connected with the third node;

the driving sub-module comprises a third transistor, wherein the grid electrode of the third transistor is connected with the third node, the first pole of the third transistor is connected with the second node, and the second pole of the third transistor is connected with the first node;

the sensing submodule comprises a second transistor, the grid electrode of the second transistor is connected with the second scanning signal end, the first pole of the second transistor is connected with the second node, and the second pole of the second transistor is connected with the detection signal line;

the switch module comprises a fourth transistor, a grid electrode of the fourth transistor is connected with the third scanning signal end, a first electrode of the fourth transistor is connected with a second power supply end, and a second electrode of the fourth transistor is connected with the detection signal line.

7. The pixel circuit according to claim 1, wherein the pixel circuit further comprises:

a first switch submodule respectively connected to the detection signal line and a fourth node and configured to connect the detection signal line and the fourth node under control of a first switch signal;

the sampling submodule is respectively connected with the fourth node and a third power supply end and is configured to store the charge of the fourth node;

8. The pixel circuit according to any one of claims 1 to 7, further comprising a control signal generation module including a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is connected to the first scan signal terminal, the second input terminal is connected to the first switch signal, and the output terminal is connected to the control signal terminal.

9. The pixel circuit according to claim 8, wherein the voltage control module comprises a fifth transistor, the fifth transistor is an NMOS transistor, the control signal generating module comprises a first level shifter sub-circuit, a first NOT gate, a first OR gate, a second level shifter sub-circuit, a second NOT gate and a third NOT gate, an input terminal of the first level shifter sub-circuit is connected to the first scan signal terminal, an output terminal of the first level shifter sub-circuit is connected to an input terminal of the first NOT gate, an input terminal of the first NOT gate is connected to a first input terminal of the first OR gate, a second input terminal of the first OR gate is connected to the first switch signal, an output terminal of the first OR gate is connected to an input terminal of the second level shifter sub-circuit, and an output terminal of the second level shifter sub-circuit is connected to an input terminal of the second NOT gate, the output end of the second NOT gate is connected with the input end of the third NOT gate, and the output end of the third NOT gate is connected with the control signal end.

10. The pixel circuit according to claim 8, wherein the voltage control module comprises a fifth transistor, the fifth transistor is an NMOS transistor, the control signal generating module comprises a fourth not gate, a second or gate and a third level shift sub-circuit, an input terminal of the fourth not gate is connected to the first scan signal terminal, an output terminal of the fourth not gate is connected to a first input terminal of the second or gate, a second input terminal of the second or gate is connected to the first switch signal, an output terminal of the second or gate is connected to an input terminal of the third level shift sub-circuit, and an output terminal of the third level shift sub-circuit is connected to the control signal terminal.

11. The pixel circuit according to claim 8, wherein the voltage control module comprises a fifth transistor, the fifth transistor is a PMOS transistor, the control signal generating module comprises a fifth not gate, a third or gate, a sixth not gate and a fourth level shifter sub-circuit, an input terminal of the fifth not gate is connected to the first scan signal terminal, an output terminal of the fifth not gate is connected to a first input terminal of a third or gate, a second input terminal of the third or gate is connected to the first switch signal, an output terminal of the third or gate is connected to an input terminal of the sixth not gate, an output terminal of the sixth not gate is connected to an input terminal of a fourth level shifter sub-circuit, and an output terminal of the fourth level shifter sub-circuit is connected to the control signal terminal.

12. A driving method of a pixel circuit, applied to the pixel circuit according to any one of claims 1 to 11, the driving method comprising:

13. The driving method of claim 12, wherein the driving module includes a writing sub-module, a sensing sub-module, and a driving sub-module,

in the data writing stage, the writing sub-module provides a data voltage of a data signal end to the third node under the control of the first scanning signal end; the sensing submodule provides an electric signal of the second node to the second node under the control of the second scanning signal terminal; the driving submodule provides the electrical signal of the second node to the first node under the control of the third node.

14. A display device comprising the pixel circuit according to any one of claims 1 to 11.