CN113285705B - Mixed CMOS-memristor full adder circuit - Google Patents

Mixed CMOS-memristor full adder circuit Download PDF

Info

Publication number
CN113285705B
CN113285705B CN202110456022.9A CN202110456022A CN113285705B CN 113285705 B CN113285705 B CN 113285705B CN 202110456022 A CN202110456022 A CN 202110456022A CN 113285705 B CN113285705 B CN 113285705B
Authority
CN
China
Prior art keywords
nmos transistor
memristor
gate
threshold
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110456022.9A
Other languages
Chinese (zh)
Other versions
CN113285705A (en
Inventor
林弥
王旭亮
陈俊杰
韩琪
罗文瑶
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hangzhou Dianzi University
Original Assignee
Hangzhou Dianzi University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hangzhou Dianzi University filed Critical Hangzhou Dianzi University
Priority to CN202110456022.9A priority Critical patent/CN113285705B/en
Publication of CN113285705A publication Critical patent/CN113285705A/en
Application granted granted Critical
Publication of CN113285705B publication Critical patent/CN113285705B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

The invention discloses a hybrid CMOS-memristor full adder circuit which comprises a first threshold memristor M1, a second threshold memristor M2, a third threshold memristor M3, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, an eighth NMOS transistor NM8, a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4 and a fifth PMOS transistor PM 5. The circuit realizes the function of full addition operation by adjusting the resistance state of the memristor and the conduction and the cut-off of the CMOS tube, has a simple structure, and has great significance for the research of the memristor digital logic circuit.

Description

Mixed CMOS-memristor full adder circuit
Technical Field
The invention belongs to the technical field of circuit design, and relates to a mixed CMOS-memristor full adder circuit with a new structure.
Background
The memristor is a two-port circuit device representing the relation between magnetic flux and electric charge, and has the characteristics of nonvolatility, nanometer size, CMOS compatibility and the like. The threshold type memristor model has a high resistance state, a low resistance state, a controllable initial resistance state and a determined threshold voltage, has obvious switching characteristics, corresponds to a logic high sum and a logic low sum in a digital circuit, and is very suitable for application of the digital logic circuit.
Therefore, the invention provides a novel structure hybrid CMOS-memristor full adder circuit based on a threshold memristor. Most of traditional full adder circuits are built by utilizing more basic gate circuits, the circuit structure is complex, and a large number of circuit elements are needed when the full adder operation function is realized. It becomes crucial to construct a simplified circuit by improving the conventional full adder circuit. Therefore, the invention relates to a memristor full adder circuit with a simpler structure.
Disclosure of Invention
Aiming at the problems in the prior art and the research cost, the invention provides a mixed CMOS-memristor full adder circuit with a new structure, which realizes the function of full addition operation by controlling the height of the resistance state of a memristor and the switching state of a CMOS transistor, and provides a new application field and a new design idea for a memristor digital circuit.
The technical scheme adopted by the invention for solving the technical problem is as follows: a mixed CMOS-memristor full adder circuit comprises three threshold-type memristors, eight NMOS transistors and five PMOS transistors. Wherein the negative terminal of the first threshold-type memristor M1 is connected to the source of the second NMOS transistor NM 2; the positive terminal of the first threshold-type memristor M1 connects the connection point of the gate of the third NMOS transistor NM3 and the gate of the second PMOS transistor PM 2; the negative terminal of the second threshold type memristor M2 is connected to the source of the fifth NMOS transistor NM 5; the positive terminal of the second threshold-type memristor M2 is connected with the connection point of the gate of the sixth NMOS transistor NM6 and the gate of the fourth PMOS transistor PM 4; the negative terminal of the third threshold-type memristor M3 is connected to the source of the eighth NMOS transistor NM 8; the positive end of the third threshold type memristor M3 is connected with the signal input end B;
a gate of the first NMOS transistor NM1 is connected to the signal input terminal a, and a source of the NM1 is connected to a connection point of a drain of the third NMOS transistor NM3 and a drain of the second PMOS transistor PM 2; a gate of the second NMOS transistor NM2 is connected to the signal input terminal a, a drain of the NM2 is connected to a connection point of the drain of the first NMOS transistor NM1 and the drain of the first PMOS transistor PM1, and a source of the NM2 is connected to the circuit intermediate signal terminal Q1; a gate of the third NMOS transistor NM3 is connected to the signal input terminal B, and a source of the NM3 is connected to ground; a gate of the fourth NMOS transistor NM4 is connected to the circuit intermediate signal terminal Q1, and a source of the NM4 is connected to a connection point of the drain of the sixth NMOS transistor NM6 and the drain of the fourth PMOS transistor PM 4; a gate of the fifth NMOS transistor NM5 is connected to the circuit intermediate signal terminal Q1, a drain of the NM5 is connected to a connection point of the drain of the fourth NMOS transistor NM4 and the drain of the third PMOS transistor PM3, and a source of the NM5 is connected to the output terminal S; a gate of the sixth NMOS transistor NM6 is connected to the signal input terminal C, and a source of the NM6 is connected to the ground terminal; the gate of the seventh NMOS transistor NM7 is connected to the circuit intermediate signal terminal Q1, and the source of NM7 is connected to the signal input terminal C; a gate of the eighth NMOS transistor NM8 is connected to the circuit intermediate signal terminal Q1, a drain of the NM8 is connected to a connection point of a drain of the seventh NMOS transistor NM7 and a drain of the fifth PMOS transistor PM5, and a source of the NM8 is connected to the carry output terminal CO;
the gate of the first PMOS transistor PM1 is connected to the signal input terminal A, and the source of PM1 is connected to the power supply signal VCC(ii) a The gate of the second PMOS transistor PM2 is connected to the signal input terminal B, and the source of the second PMOS transistor PM2 is connected to the power supply signal VCC(ii) a The gate of the third PMOS transistor PM3 is connected to the circuit intermediate signal terminal Q1, and the source of PM3 is connected to the power supply signal VCC(ii) a The gate of the fourth PMOS transistor PM4 is connected to the signal input terminal C, and the source of PM4 is connected to the power supply signal VCC(ii) a The gate of the fifth PMOS transistor PM5 is connected to the circuit intermediate signal terminal Q1, and the source of PM5 is connected to the power supply signal VCC。
The invention designs a mixed CMOS-memristor full adder circuit with a new structure. The circuit realizes the function of full addition operation by controlling the change of the resistance state of the memristor and the connection and the disconnection of the CMOS transistor in the circuit, has a simple circuit structure, and can provide more approaches for the design of a memristor digital logic circuit.
Drawings
Fig. 1 is a circuit symbol of a memristor.
FIG. 2 is a current-voltage characteristic of a threshold-type memristor.
Fig. 3 is a circuit structure diagram of the hybrid CMOS-memristor full adder of the present invention.
FIG. 4 is a simulation test diagram of a hybrid CMOS-memristor full-adder circuit of the present invention.
Detailed Description
The following detailed description of the embodiments of the invention refers to the accompanying drawings
Referring to fig. 1, a circuit symbol of the memristor is shown, fig. 2 is a current-voltage characteristic curve of the threshold type memristor, and it can be known from fig. 2 that when a signal exceeding a threshold voltage is applied to two ends of the threshold type memristor, the resistance value is in a high resistance state ROFFAnd a low resistance state RONThe switching between the two circuits is realized, and the switching characteristic and the controllability are obvious.
As shown in fig. 3, the hybrid CMOS-memristor full adder circuit of the present invention is composed of three threshold memristors, eight NMOS transistors, and five PMOS transistors. A. B, C is the signal input end, where A, B is the addend input, C is the carry input, VCCFor a direct-current working power supply, Q1 is a circuit intermediate signal, S is a sum signal output end, CO is a carry signal output end, M1, M2 and M3 are threshold type memristor models, NM1, NM2, NM3, NM4, NM5, NM6, NM7 and NM8 are all NMOS transistors, PM1, PM2, PM3, PM4 and PM5 are all PMOS transistors, and the function of full-addition operation is realized by controlling states of the memristor and the CMOS transistors on the assumption that initial states of the memristor are low-resistance states.
1. When the addend input signal a is equal to 0, the first and second NMOS transistors NM1 and NM2 are in an off state, and the first PMOS transistor PM1 is in an on state.
(1) When the addend input signal B is equal to 0, since the first NMOS transistor NM1 and the second NMOS transistor NM2 are turned off, the circuit intermediate signal Q1 is determined by only the first threshold memristor M1 and the addend input signal B, and the value of Q1 is equal to the value of B, that is, the circuit intermediate signal Q1 is logic 0. At this time, there is no voltage difference between the two ends of the first threshold memristor M1, M1 maintains a low-resistance state, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, the seventh NMOS transistor NM7, and the eighth NMOS transistor NM8 are all in a cut-off state, and the third PMOS transistor PM3 and the fifth PMOS transistor PM5 are in a conduction state.
(a) When the carry input signal C is equal to 0, since the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, the seventh NMOS transistor NM7, and the eighth NMOS transistor NM8 are in the off state, the sum output S is determined only by the branch of the second threshold memristor M2 and the carry input signal C, that is, the sum output S is logic 0; the carry output CO is determined only by a branch of the third threshold memristor M3 and the addend input signal B, that is, the carry output CO is logic 0, and at this time, the second threshold memristor M2 and the third threshold memristor M3 both maintain a low-resistance state.
(b) When the carry input signal C is equal to 1, the second threshold memristor M2 is switched from the low resistance to the high resistance state, and the states of the other elements are the same as (a), and do not change. Since the fifth NMOS transistor NM5 is in the off state, the sum output S is determined only by the branch of the second threshold memristor M2 and the carry input signal C, i.e., the sum output S is logic 1; the carry output CO is determined only by a branch of the third threshold memristor M3 and the addend input signal B, that is, the carry output CO is logic 0, and the third threshold memristor M3 maintains a low-resistance state.
(2) When the addend input signal B is equal to 1, the first threshold memristor M1 and the third threshold memristor M3 are switched from a low resistance to a high resistance state. Since the second NMOS transistor NM2 is in an off state, the value of the circuit intermediate signal Q1 is equal to the value of B, which is logic 1, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, the seventh NMOS transistor NM7, and the eighth NMOS transistor NM8 are in an on state, and the third PMOS transistor PM3, and the fifth PMOS transistor PM5 are in an off state.
(a) When the carry input signal C is equal to 0, the sixth NMOS transistor NM6 is in an off state, the fourth PMOS transistor PM4 is in an on state, VCCSignals are transmitted to a sum output S through PM4, NM4 and NM5, namely the sum output S is logic 1, at the moment, the voltage difference between two ends of the second threshold type memristor M2 does not reach a forward threshold voltage, a low resistance state is still kept, and the signal is equivalent to a small resistor serving as a circuit load; the third threshold memristor M3 is in a high-impedance state, which is equivalent to a large-resistance load, the carry input signal C is transmitted from the seventh NMOS transistor NM7 and the eighth NMOS transistor NM8 to the carry output CO, and the carry output CO is logic 0.
(b) When the carry input signal C is 1, the second threshold memristor M2 is converted from low resistance to high resistance state, the sixth NMOS transistor NM6 is in on state, the fourth PMOS transistor PM4 is in off state, the ground signal is transmitted to and output S through NM4, NM5 and NM6, the branch of the second threshold memristor M2 may be equivalent to a large resistance load, and the output S is logic 0; the third threshold memristor M3 branch is also equivalent to a large resistance load, the carry input signal C is transmitted from the seventh NMOS transistor NM7 and the eighth NMOS transistor NM8 to the carry output CO, and the carry output CO is logic 1.
2. When the addend input signal a is equal to 1, the first and second NMOS transistors NM1 and NM2 are in an on state, and the first PMOS transistor PM1 is in an off state.
(1) When the addend input signal B is equal to 0, the third NMOS transistor NM3 is in an off state, the second PMOS transistor PM2 is in an on state, and V is set to zeroCCThe signals are transmitted to the Q1 end through NM3, NM1 and NM2, the circuit intermediate signal Q1 is logic 1, at this time, the first threshold memristor M1 keeps a low resistance state, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, the seventh NMOS transistor NM7 and the eighth NMOS transistor NM8 are in a conducting state, and the third PMOS transistor PM3 and the fifth PMOS transistor PM5 are in a blocking state.
(a) When the carry input signal C is equal to 0, the sixth NMOS transistor NM6 is in an off state, the fourth PMOS transistor PM4 is in an on state, VCCThe signals are transmitted via PM4, NM4 and NM5 to and output S, which is a logic 1; the carry input signal C is transmitted from the seventh NMOS transistor NM7 and the eighth NMOS transistor NM8 to the carry output CO, and the carry output CO is logic 0, and at this time, the second threshold memristor M2 and the third threshold memristor M3 both maintain a low resistance state.
(b) When the carry input signal C is 1, the second threshold memristor M2 is converted from low resistance to high resistance state, the sixth NMOS transistor NM6 is in on state, the fourth PMOS transistor PM4 is in off state, the ground signal is transmitted to and output S through NM4, NM5 and NM6, and the output S is logic 0; the carry input signal C is transmitted from the seventh NMOS transistor NM7 and the eighth NMOS transistor NM8 to the carry output CO, the carry output CO is logic 1, at this time, the second threshold memristor M2 maintains a high resistance state, and the third threshold memristor M3 maintains a low resistance state.
(2) When the addend input signal B is equal to 1, the first threshold memristor M1 and the third threshold memristor M3 are switched from low resistance to high resistance, the third NMOS transistor NM3 is in a conducting state, the second PMOS transistor PM2 is in a blocking state, the ground signal is transmitted to the Q1 end through NM1, NM2 and NM3, the circuit intermediate signal Q1 is logic 0, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, the seventh NMOS transistor NM7 and the eighth NMOS transistor NM8 are in a blocking state, and the third PMOS transistor PM3 and the fifth PMOS transistor PM5 are in a conducting state.
(a) When the carry input signal C is 0, since the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, the seventh NMOS transistor NM7, and the eighth NMOS transistor NM8 are in an off state, the sum output S is determined only by the branch of the second threshold type memristor M2 and the carry input signal C, and the sum output S is logic 0; the carry output CO is determined by only a branch of the third threshold memristor M3 and the addend input signal B, the carry output CO is logic 1, at this time, the second threshold memristor M2 maintains a low-resistance state, and the third threshold memristor M3 maintains a high-resistance state.
(b) When the carry input signal C is equal to 1, the second threshold memristor M2 is switched from a low resistance to a high resistance state, and the output S is determined only by a branch of the second threshold memristor M2 and the carry input signal C, and the output S is logic 1; the carry output CO is determined only by the branch of the third threshold memristor M3 and the addend input signal B, and the carry output CO is logic 1, and at this time, both the second threshold memristor M2 and the third threshold memristor M3 maintain a high-impedance state.
The voltage drop between the source and the drain of the MOS tube is ignored in the above analysis. To sum up:
(1) the addend input signal A is equal to 0, B is equal to 0, when the carry input C is equal to 0, the sum output S is equal to 0, and the carry output CO is equal to 0;
(2) when the addend input signal A is equal to 0, B is equal to 0, and the carry input C is equal to 1, the sum output S is equal to 1, and the carry output CO is equal to 0;
(3) the addend input signal A is equal to 0, B is equal to 1, when the carry input C is equal to 0, the sum output S is equal to 1, and the carry output CO is equal to 0;
(4) the addend input signal A is equal to 0, B is equal to 1, when the carry input C is equal to 1, the sum output S is equal to 0, and the carry output CO is equal to 1;
(5) when the addend input signal A is equal to 1, B is equal to 0, and the carry input C is equal to 0, the sum output S is equal to 1, and the carry output CO is equal to 0;
(6) when the addend input signal A is equal to 1, B is equal to 0, and the carry input C is equal to 1, the sum output S is equal to 0, and the carry output CO is equal to 1;
(7) the addend input signal A is equal to 1, B is equal to 1, when the carry input C is equal to 0, the sum output S is equal to 0, and the carry output CO is equal to 1;
(8) when the addend input signal a is equal to 1, B is equal to 1, and the carry input C is equal to 1, the sum output S is equal to 1, and the carry output CO is equal to 1.
And the full addition operation is realized, and the design of a full adder circuit is achieved.
In a preferred embodiment, the high resistance values of the memristors M1, M2 and M3 are all defined as 100K Ω, the low resistance values are all defined as 100 Ω, and the threshold voltage is all defined as about 4V; the addend input signal A, B and the carry input C are both pulse signals with amplitude of 6V. Fig. 4 shows the PSPICE simulation result of the hybrid CMOS-memristor full-adder circuit.
As can be seen from FIG. 4, the simulation result is consistent with the theoretical analysis, the full addition operation function is realized, and the design of the CMOS-memristor full adder circuit is achieved.
It should be appreciated by those skilled in the art that the above embodiments are only used for verifying the present invention, and are not to be construed as limiting the present invention, and that the changes and modifications of the above embodiments are within the scope of the present invention.

Claims (1)

1. A hybrid CMOS-memristor full adder circuit is characterized by comprising a first threshold memristor M1, a second threshold memristor M2, a third threshold memristor M3, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, an eighth NMOS transistor NM8, a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, and a fifth PMOS transistor PM5, wherein the function of full addition operation is realized by controlling the states of memristor state, on and off of the CMOS transistors;
the negative end of the first threshold memristor M1 is connected with the source of a second NMOS transistor NM 2; the positive terminal of the first threshold-type memristor M1 connects the connection point of the gate of the third NMOS transistor NM3 and the gate of the second PMOS transistor PM 2; the negative terminal of the second threshold-type memristor M2 is connected to the source of the fifth NMOS transistor NM 5; the positive terminal of the second threshold-type memristor M2 is connected with the connection point of the gate of the sixth NMOS transistor NM6 and the gate of the fourth PMOS transistor PM 4; the negative terminal of the third threshold-type memristor M3 is connected to the source of the eighth NMOS transistor NM 8; the positive end of the third threshold type memristor M3 is connected with the signal input end B;
the gate of the first NMOS transistor NM1 is connected to the signal input terminal a, and the source of the first NMOS transistor NM1 is connected to the connection point between the drain of the third NMOS transistor NM3 and the drain of the second PMOS transistor PM 2; a gate of the second NMOS transistor NM2 is connected to the signal input terminal a, a drain of the NM2 is connected to a connection point of the drain of the first NMOS transistor NM1 and the drain of the first PMOS transistor PM1, and a source of the NM2 is connected to the circuit intermediate signal terminal Q1; the gate of the third NMOS transistor NM3 is connected to the signal input terminal B, and the source of NM3 is connected to ground; a gate of the fourth NMOS transistor NM4 is connected to the circuit intermediate signal terminal Q1, and a source of the NM4 is connected to a connection point of the drain of the sixth NMOS transistor NM6 and the drain of the fourth PMOS transistor PM 4; a gate of the fifth NMOS transistor NM5 is connected to the circuit intermediate signal terminal Q1, a drain of the NM5 is connected to a connection point of the drain of the fourth NMOS transistor NM4 and the drain of the third PMOS transistor PM3, and a source of the NM5 is connected to the output terminal S; a gate of the sixth NMOS transistor NM6 is connected to the signal input terminal C, and a source of the NM6 is connected to the ground terminal; the gate of the seventh NMOS transistor NM7 is connected to the circuit intermediate signal terminal Q1, and the source of NM7 is connected to the signal input terminal C; a gate of the eighth NMOS transistor NM8 is connected to the circuit intermediate signal terminal Q1, a drain of the NM8 is connected to a connection point of a drain of the seventh NMOS transistor NM7 and a drain of the fifth PMOS transistor PM5, and a source of the NM8 is connected to the carry output terminal CO;
the gate of the first PMOS transistor PM1 is connected to the signal input terminal A, and the source of the first PMOS transistor PM1 is connected to the power supply signal VCC(ii) a The gate of the second PMOS transistor PM2 is connected to the signal input terminal B, and the source of PM2 is connected to the power supply signal VCC(ii) a The gate of the third PMOS transistor PM3 is connected to the circuit intermediate signal terminal Q1, and the source of PM3 is connected to the power supply signal VCC(ii) a The gate of the fourth PMOS transistor PM4 is connected to the signal input terminal C, and the source of PM4 is connected to the power supply signal VCC(ii) a The gate of the fifth PMOS transistor PM5 is connected to the circuit intermediate signal terminal Q1, and the source of PM5 is connected to the power supply signal VCC；
The signal input end A and the signal input end B are used for inputting addend input signals, and the signal input end C is used for inputting carry input signals.
CN202110456022.9A 2021-04-26 2021-04-26 Mixed CMOS-memristor full adder circuit Active CN113285705B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110456022.9A CN113285705B (en) 2021-04-26 2021-04-26 Mixed CMOS-memristor full adder circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110456022.9A CN113285705B (en) 2021-04-26 2021-04-26 Mixed CMOS-memristor full adder circuit

Publications (2)

Publication Number Publication Date
CN113285705A CN113285705A (en) 2021-08-20
CN113285705B true CN113285705B (en) 2022-05-17

Family

ID=77275707

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110456022.9A Active CN113285705B (en) 2021-04-26 2021-04-26 Mixed CMOS-memristor full adder circuit

Country Status (1)

Country Link
CN (1) CN113285705B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9921808B1 (en) * 2017-06-02 2018-03-20 Board Of Regents, The University Of Texas System Memristor-based adders using memristors-as-drivers (MAD) gates
CN108449080A (en) * 2018-04-20 2018-08-24 西南大学 The full power-up road constituted based on CMOS inverter and memristor
CN211015470U (en) * 2019-11-29 2020-07-14 珠海复旦创新研究院 Half adder and multiplier based on memristor array

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100164543A1 (en) * 2008-12-31 2010-07-01 Shepard Daniel R Low-complexity electronic adder circuits and methods of forming the same
US8832009B2 (en) * 2012-05-15 2014-09-09 The United States Of America As Represented By The Secretary Of The Air Force Electronic charge sharing CMOS-memristor neural circuit
US8937829B2 (en) * 2012-12-02 2015-01-20 Khalifa University of Science, Technology & Research (KUSTAR) System and a method for designing a hybrid memory cell with memristor and complementary metal-oxide semiconductor
GB2548081B (en) * 2016-02-23 2019-10-02 Univ Oxford Brookes Logic gate
US10318242B2 (en) * 2017-09-08 2019-06-11 Board Of Regents, The University Of Texas System Memristor-based multipliers using memristors-as-drivers (MAD) gates

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9921808B1 (en) * 2017-06-02 2018-03-20 Board Of Regents, The University Of Texas System Memristor-based adders using memristors-as-drivers (MAD) gates
CN108449080A (en) * 2018-04-20 2018-08-24 西南大学 The full power-up road constituted based on CMOS inverter and memristor
CN211015470U (en) * 2019-11-29 2020-07-14 珠海复旦创新研究院 Half adder and multiplier based on memristor array

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
A novel hybrid CMOS-memristor logic circuit using Memristor Ratioed Logic;Mehri Teimoori;《2016 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)》;20161103;第1-4页 *
Memristor-CMOS logic and digital computational components;KyoungrokCho;《Microelectronics Journal》;20150331;第214-220页 *
基于混合忆阻器-CMOS逻辑的全加器电路优化设计;冯朝文;《微纳电子技术》;20191021;第868-874页 *
忆阻数字逻辑电路设计;王晓媛;《电子与信息学报》;20200415;第851-861页 *

Also Published As

Publication number Publication date
CN113285705A (en) 2021-08-20

Similar Documents

Publication Publication Date Title
CN108092658B (en) Logic circuit operation method
EP2241009B1 (en) Low-swing cmos input circuit
JP3682857B2 (en) Level shifting passgate
JP2010524303A5 (en)
CN101587753A (en) A kind of simulating signal sample circuit and a kind of switched-capacitor circuit
CN108011624B (en) Analog multiplexer
US20120007660A1 (en) Bias Current Generator
CN107094012A (en) A kind of level shifting circuit and method
WO2015161450A1 (en) Latch and d trigger
CN206993065U (en) A kind of power supply time schedule controller and microwave power amplifier
CN111427820A (en) IO circuit and access control signal generation circuit for IO circuit
CN113285705B (en) Mixed CMOS-memristor full adder circuit
CN108736863B (en) Output driving circuit
WO2023155439A1 (en) Electronic device and memristor-based logic gate circuit thereof
TWI524672B (en) Voltage level translator and process for keeping a voltage level translator
CN104579306A (en) Low-power phase inverter circuit
CN110601691B (en) Level shift circuit
Gao et al. Memristor-based logic gate circuit
CN101404499B (en) Novel invertor based on nervous MOS pipe
CN207884585U (en) Power supply sample circuit and electrification reset circuit
CN112787657B (en) Programmable memristor logic circuit
CN206283486U (en) A kind of smooth output circuit of electric current D A conversions
CN107564565B (en) Memristor logic circuit with three-input and logic functions
CN112383298B (en) DDR (double data Rate) sending circuit
CN210405268U (en) Computer communication interface device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant