CN113284948A - GaN device and preparation method thereof - Google Patents

GaN device and preparation method thereof Download PDF

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Publication number
CN113284948A
CN113284948A CN202110745865.0A CN202110745865A CN113284948A CN 113284948 A CN113284948 A CN 113284948A CN 202110745865 A CN202110745865 A CN 202110745865A CN 113284948 A CN113284948 A CN 113284948A
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layer
substrate
metal
epitaxial layer
hard mask
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CN113284948B (en
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蒋洋
唐楚滢
于洪宇
汪青
汤欣怡
杜方洲
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Southwest University of Science and Technology
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Southwest University of Science and Technology
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Abstract

The embodiment of the invention discloses a GaN device and a preparation method thereof. The GaN device comprises a substrate, and a buffer layer, an epitaxial layer and a metal electrode layer which are sequentially stacked on the substrate, wherein the epitaxial layer comprises a GaN channel layer, an AlN layer and a barrier layer which are sequentially stacked on the substrate, the metal electrode layer comprises a source drain metal layer, the source drain metal layer comprises a protruding structure which extends into the epitaxial layer towards one side of the substrate, a source electrode and a drain electrode in the metal electrode layer are both contacted with the epitaxial layer to form an ohmic contact electrode mechanism, the protruding structures which extend into the epitaxial layer towards one side of the substrate are arranged on the source drain metal electrode layer and the drain metal electrode layer, the contact area between the metal electrode layer and the epitaxial layer is increased, the ohmic contact resistance is reduced, the on-resistance of the GaN device is reduced, the low-temperature ohmic contact process is realized through the etching of a source drain electrode region, and the overall reliability of the GaN device is improved.

Description

GaN device and preparation method thereof
Technical Field
The embodiment of the invention relates to the technical field of GaN radio frequency devices, in particular to a GaN device and a preparation method thereof.
Background
Gallium nitride (GaN) materials have wide forbidden bandwidth, high breakdown electric field, high thermal conductivity, high electron saturation rate and higher radiation resistance, and have wide application prospects in high-temperature, high-frequency, radiation-resistant and high-power semiconductor devices. GaN-based High Electron Mobility Transistors (HEMTs) have been widely used in the fields of microwave communications and power electronic conversion.
The on-resistance of the GaN HEMT device is a key index affecting the performance of the device, for example, the GaN HEMT device has a large on-resistance, and is characterized by a reduction in output power density in a radio frequency device and an increase in conduction loss in a power electronic device, thereby affecting the power conversion efficiency, and meanwhile, the large on-resistance causes a large heat productivity of the device, and increases the heat dissipation cost or even affects the reliability of the device. At present, the channel resistance of the material is mainly reduced by optimizing the epitaxial material, but the resistance of the material at present reaches about 250 Ω, so that great breakthrough is difficult to occur, the contact area between the metal electrode and the GaN cannot be effectively increased to a certain extent, the on-resistance of the device cannot be reduced, and the preparation process is complex.
Disclosure of Invention
The embodiment of the invention provides a GaN device and a preparation method thereof, which can effectively increase the contact area between a metal electrode and GaN and effectively reduce the ohmic contact resistance of the device, thereby reducing the on-resistance of the device, and has the advantages of simple preparation process and lower implementation cost.
In a first aspect, embodiments of the present invention provide a GaN device, including:
the epitaxial layer comprises a GaN layer, an AlN layer and a barrier layer which are sequentially stacked on the substrate, and the metal electrode layer comprises a source drain metal layer;
the source drain metal layer comprises a protruding structure extending into the epitaxial layer towards one side of the substrate.
Optionally, the protrusion structure includes a plurality of first sub-protrusions.
Optionally, the bump structure further includes a second sub-bump located on a side of the first sub-bumps away from the substrate, and the second sub-bump is connected to the first sub-bumps.
Optionally, the height of the first sub-bump is smaller than the thickness of the barrier layer.
Optionally, the height of the first sub-bump is greater than or equal to the thickness of the barrier layer and less than the sum of the thicknesses of the barrier layer and the AlN layer.
Optionally, the height of the first sub-bump is greater than or equal to the sum of the thicknesses of the barrier layer and the AlN layer, and is less than or equal to the sum of the thicknesses of the barrier layer, the AlN layer, and the GaN layer.
Optionally, a cross-sectional shape of the first sub-protrusion perpendicular to the first direction is a circle, and the first direction is a stacking direction of the substrate and the buffer layer.
Optionally, the source-drain metal layer includes a source electrode and a drain electrode, the plurality of first sub-protrusion arrangements of the source electrode include, but are not limited to, a matrix, a circle, a rectangle, a zigzag, an X shape, two squares whose diagonal lines are located on the same straight line, or a plurality of staggered row structures, and the plurality of first sub-protrusion arrangements of the drain electrode include, but are not limited to, a matrix, a circle, a rectangle, a zigzag, an X shape, two squares whose diagonal lines are located on the same straight line, or a plurality of staggered row structures.
In a second aspect, an embodiment of the present invention further provides a GaN device, including:
providing a substrate;
sequentially forming a buffer layer, an epitaxial layer and a metal electrode layer on the substrate, wherein the epitaxial layer comprises a GaN layer, an AlN layer and a barrier layer which are sequentially stacked on the substrate, and the metal electrode layer comprises a source drain metal layer;
the source drain metal layer comprises a plurality of protruding structures extending into the epitaxial layer towards one side of the substrate.
Optionally, sequentially forming the buffer layer, the epitaxial layer, and the metal electrode layer on the substrate includes:
sequentially forming a buffer layer and an epitaxial layer on the substrate;
forming a first hard mask layer and a second hard mask layer which are stacked on the epitaxial layer;
patterning the first hard mask layer and the second hard mask layer, and patterning the epitaxial layer by taking the patterned first hard mask layer and the patterned second hard mask layer as masks to form a plurality of first grooves in the epitaxial layer;
removing the first hard mask layer and the second hard mask layer;
forming a source drain metal layer on one side of the epitaxial layer, which is far away from the substrate, wherein the source drain metal layer fills the first groove;
and forming other metal layers in the metal electrode layer.
Optionally, sequentially forming the buffer layer, the epitaxial layer, and the metal electrode layer on the substrate includes:
sequentially forming a buffer layer and an epitaxial layer on the substrate;
patterning the epitaxial layer to form a plurality of second grooves on the epitaxial layer;
forming a first hard mask layer on one side, far away from the substrate, of the epitaxial layer, wherein the first hard mask layer fills the plurality of second grooves;
forming a second hard mask layer on the first hard mask layer;
patterning the first hard mask layer and the second hard mask layer in the area of the second groove to form a plurality of third grooves in the first hard mask layer and the second hard mask layer in the area of the second groove;
forming a plurality of fourth grooves in the epitaxial layer below the second groove by taking the patterned first hard mask layer and the patterned second hard mask layer as masks;
removing the first hard mask layer and the second hard mask layer;
forming a source drain metal layer on one side of the epitaxial layer, which is far away from the substrate, wherein the source drain metal layer fills the second groove and the fourth groove;
forming other metal layers in the metal electrode layer.
Optionally, sequentially forming the buffer layer, the epitaxial layer, and the metal electrode layer on the substrate includes:
sequentially forming a buffer layer and an epitaxial layer on the substrate;
forming a metal film on the epitaxial layer, and performing an annealing process;
an external mask plate is adopted to define a region where the source electrode is located and a region where the drain electrode is located, and the upper surfaces of the barrier layers in the region where the source electrode is located and the region where the drain electrode is located are exposed;
etching the barrier layer by using the metal film subjected to annealing treatment in the region where the source electrode is located and the region where the drain electrode is located as a mask and adopting an ICP (inductively coupled plasma) process to form a plurality of fifth grooves on the barrier layer;
removing the external mask plate and the metal film;
forming a source drain metal layer on one side of the epitaxial layer, which is far away from the substrate, wherein the source drain metal layer fills the fifth groove;
and forming other metal layers in the metal electrode layer.
Optionally, sequentially forming the buffer layer, the epitaxial layer, and the metal electrode layer on the substrate includes:
sequentially forming a buffer layer and an epitaxial layer on the substrate;
etching the barrier layer by adopting an ICP (inductively coupled plasma) process to form a plurality of sixth grooves on the barrier layer so as to expose the upper surface of the barrier layer in the region where the source electrode is located and the region where the drain electrode is located;
forming a metal film on the epitaxial layer, and performing an annealing process;
patterning the epitaxial layer below the sixth groove to form a plurality of seventh grooves by taking the metal film subjected to annealing treatment in the region where the source electrode is located and the region where the drain electrode is located as a mask;
removing the external mask plate and the metal film;
forming a source drain metal layer on one side of the epitaxial layer, which is far away from the substrate, wherein the source drain metal layer fills the sixth groove and the seventh groove;
forming the other metal in the metal electrode layer.
The GaN device provided by the embodiment of the invention comprises a substrate, and a buffer layer, an epitaxial layer and a metal electrode layer which are sequentially laminated on the substrate, wherein the epitaxial layer comprises a GaN layer, an AlN layer and a barrier layer which are sequentially laminated on the substrate, the metal electrode layer comprises a source drain metal layer, the source drain metal layer comprises a protruding structure which extends into the epitaxial layer towards one side of the substrate, a source electrode and a drain electrode in the metal electrode layer are contacted with the epitaxial layer to form an ohmic contact electrode mechanism, the protruding structure which extends into the epitaxial layer towards one side of the substrate is arranged on the source electrode and the drain metal electrode layer to increase the contact area of the metal electrode layer and the epitaxial layer, so that the ohmic contact resistance is reduced, as the main factor influencing the on-resistance in the GaN device is the ohmic contact resistance, when the ohmic contact resistance is reduced, the on-resistance is also reduced, and through the etching of a source drain electrode region, the low-temperature ohmic contact process is realized, and the overall reliability of the GaN device is further improved.
Drawings
Fig. 1 is a schematic structural diagram of a GaN device according to an embodiment of the present invention;
FIG. 2 is a schematic view of a bump structure according to an embodiment of the present invention;
FIG. 3 is a schematic view of a bump structure according to an embodiment of the present invention;
FIG. 4 is a schematic view of another bump structure provided in this embodiment;
FIG. 5 is a schematic view of another bump structure provided in this embodiment;
FIGS. 6a-6g are top views of a source metal layer or a drain metal layer provided in this embodiment;
FIG. 7 is a schematic flow chart of a method for fabricating a GaN device according to an embodiment of the invention;
fig. 8 is a schematic flow chart of sequentially forming a buffer layer, an epitaxial layer, and a metal electrode layer on a substrate according to an embodiment of the present invention;
FIGS. 9a-9g are schematic process diagrams of a manufacturing method for sequentially forming a buffer layer, an epitaxial layer and a metal electrode layer on a substrate according to an embodiment of the present invention;
fig. 10 is a schematic flow chart of sequentially forming a buffer layer, an epitaxial layer and a metal electrode layer on a substrate according to another embodiment of the present invention;
FIGS. 11a-11g are schematic process diagrams of another fabrication method for sequentially forming a buffer layer, an epitaxial layer and a metal electrode layer on a substrate according to an embodiment of the present invention;
fig. 12 is a schematic flow chart of sequentially forming a buffer layer, an epitaxial layer and a metal electrode layer on a substrate according to another embodiment of the present invention;
FIGS. 13a-13f are schematic process diagrams of another fabrication method for sequentially forming a buffer layer, an epitaxial layer and a metal electrode layer on a substrate according to an embodiment of the present invention;
fig. 14 is a schematic flow chart of sequentially forming a buffer layer, an epitaxial layer and a metal electrode layer on a substrate according to another embodiment of the present invention;
fig. 15a to 15g are schematic process diagrams of another preparation method for sequentially forming a buffer layer, an epitaxial layer and a metal electrode layer on a substrate according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in further detail below with reference to the accompanying drawings. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention.
It should be noted that, in order to further explain the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description of the embodiments, structures, features and effects of the GaN device and the method for manufacturing the same according to the present invention will be made with reference to the accompanying drawings and preferred embodiments.
Fig. 1 is a schematic structural diagram of a GaN device according to an embodiment of the present invention. As shown in fig. 1, the device comprises: the semiconductor structure comprises a substrate 10, and a buffer layer 11, an epitaxial layer 12 and a metal electrode layer 13 which are sequentially stacked on the substrate 10, wherein the epitaxial layer 12 comprises a GaN layer 14, an AlN layer 15 and a barrier layer 16 which are sequentially stacked on the substrate 10, and the metal electrode layer 13 comprises a source-drain metal layer 17, wherein the source-drain metal layer 17 comprises a protruding structure 18 which extends into the epitaxial layer 12 towards one side of the substrate 10.
GaN, i.e., a gallium nitride material, is a semiconductor material having a wide forbidden band width, a high breakdown electric field, a high thermal conductivity, a high electron saturation rate, and a high radiation resistance. The GaN-based High Electron Mobility Transistor (HEMT) can be widely applied to the fields of microwave communication, electronic conversion and the like, and the on-resistance of the GaN HEMT device is a key index influencing the performance of the device. In an electronic power device, the large on-resistance leads to large heat productivity of the device, increases the heat dissipation cost and even affects the reliability of the device. In general, the on-resistance Ron of a GaN HEMT device can be roughly calculated by the following formula: ron is 2Rc + Rsh Lsd, where Ron is on-resistance, Rc is ohmic contact resistance, Rsh is channel resistance, and Lsd is channel length, and in a GaN power device, the channel resistance Rsh is the main factor affecting on-resistance Ron, while in a radio frequency device, the ohmic contact resistance Rc is the main factor affecting on-resistance Ron.
The barrier layer 16 at the outermost layer of the epitaxial layer 12 may be made of AlGaN, InGaN, or InAlN. In order to improve the performance of the GaN device, when the barrier layer 16 is made of AlGaN, the thickness of the AlGaN layer ranges from 10nm to 30nm, and the composition of Al therein ranges from 0.15 to 0.30. When the barrier layer 16 is InGaN, the thickness of the InGaN layer ranges from 10nm to 30nm, and In is 0.10 to 0.30, and Ga is 0.70 to 0.90. When the barrier layer 16 is made of InAlN, the thickness of the InAlN layer ranges from 10nm to 30nm, wherein the In component is 0.10 to 0.20, and the Al component is 0.80 to 0.90. In addition, the AlN layer 15 in the epitaxial layer 12 has a thickness in the range of 1nm to 3nm, and the substrate 10 is made of silicon, silicon carbide, GaN or sapphire.
In this embodiment, in order to reduce the on-resistance in the GaN device, the metal electrode is an ohmic contact electrode, and the source electrode 171 and the drain electrode 172 in the metal electrode layer 13 are connected to the epitaxial layer 12 to achieve conduction, and the metal electrode of the source electrode and the drain electrode may be a metal electrode having gold or a metal electrode having no gold. Illustratively, when the electrode in the metal electrode layers of the source and drain is a gold metal electrode, the electrode layer may be Ti/Al/Ni/Au, Ti/Al/Ti/Au, Ta/Al/Au, Ti/Au, Ni/Au, etc., and when the electrode in the metal electrode layers of the source and drain is a gold-free metal electrode, the electrode layer may be Ti/Al/Ti/TiN, Ta/Al/Ta, Ti/Al/W, Ta/Si/Ti/Al/Ni/Ta, Ti/Al/Ni/Pt, Ti/Al/TiN, Ti/Al/Ti/W, Ti5Al1/TiN、Ti5Al1and/W, etc.
Specifically, the buffer layer 11, the epitaxial layer 12, and the metal electrode layer 13 are sequentially stacked on the substrate 10, and both the source 171 and the drain 172 in the metal electrode layer 13 are in contact with the epitaxial layer 12 to form an ohmic contact electrode, and the source 171 and the drain 172 electrode layers are provided with the protruding structures 18 extending into the epitaxial layer 12 toward the substrate 10 side, so that the contact area between the metal electrode layer 13 and the epitaxial layer 12 is increased, thereby reducing the ohmic contact resistance.
The GaN device provided by this embodiment includes a substrate, and a buffer layer, an epitaxial layer and a metal electrode layer sequentially stacked on the substrate, the epitaxial layer includes a GaN layer, an AlN layer and a barrier layer sequentially stacked on the substrate, the metal electrode layer includes a source drain metal layer, wherein the source drain metal layer includes a protruding structure extending into the epitaxial layer toward one side of the substrate, both a source and a drain in the metal electrode layer are in contact with the epitaxial layer to form an ohmic contact electrode mechanism, and the source and drain metal electrode layers are provided with the protruding structure extending into the epitaxial layer toward one side of the substrate to increase a contact area of the metal electrode layer and the epitaxial layer, thereby reducing ohmic contact resistance, because in the GaN device, a main factor affecting on-resistance is ohmic contact resistance, when the ohmic contact resistance is reduced, the on-resistance is also reduced, by etching of a source drain electrode region, the low-temperature ohmic contact process is realized, and the overall reliability of the GaN device is further improved.
Optionally, fig. 2 is a schematic view of a protrusion structure provided in an embodiment of the present invention. As shown in fig. 2, the bump structure 18 includes a plurality of first sub-bumps 181.
In order to better contact the metal electrode layer 13 with the epitaxial layer 12, the first sub-protrusions 181 in the protrusion structures 18 extend along the buffer layer and substrate direction, and are used for contacting the source electrode 171 and the drain electrode 172 with the epitaxial layer 12, so as to increase the contact area of the metal electrode layer 13 with the epitaxial layer 12.
Optionally, with continued reference to fig. 2, the bump structure 18 further includes a second sub-bump 182 located on a side of the first sub-bumps 181 away from the substrate, and the second sub-bump 182 is connected to the first sub-bumps 181.
In addition, on the basis of the above embodiment, the second sub-protrusions 182 may be disposed in the source 171 and drain 172 regions, forming the source electrode 171 and the drain electrode 172 protruding above the epitaxial layer 12.
Optionally, fig. 3 is a schematic diagram of a protrusion structure according to an embodiment of the present invention. As shown in fig. 3, the height of the raised structure is less than the thickness of the barrier layer.
The epitaxial layer 12 includes a barrier layer 16, an AlN layer 15, and a GaN layer 14 stacked from top to bottom, and in order to reduce the on-resistance of the GaN device, the ohmic contact resistance needs to be reduced, and the source 171 and drain 172 metal layers are now in contact with the epitaxial layer 12 to form an ohmic contact electrode mechanism. Therefore, when the first sub-bump 181 in the bump structure 18 extends along the buffer layer 11 and the substrate 10, it is only required to contact any one of the epitaxial layers 12.
Specifically, when the protrusion structure extends along the buffer layer 11 and the substrate 10, the first sub-protrusion 181 contacts the barrier layer 16 in the epitaxial layer 12, and an ohmic contact electrode mechanism can be implemented. In order to avoid the mutual influence between the structural layers of three different materials in the epitaxial layer, referring to fig. 2, the height h1 of the first sub-protrusion 181 is set to be smaller than the thickness of the barrier layer 16.
Optionally, fig. 4 is a schematic view of another protrusion structure provided in this embodiment. As shown in fig. 4, the height h2 of the first sub-protrusion 181 is greater than or equal to the thickness of the barrier layer 16 less than the sum of the thicknesses of the barrier layer 16 and the AlN layer 15.
Similarly, when the first sub-protrusion 181 extends along the buffer layer 11 and the substrate 10, and reaches the AlN layer 15 in the epitaxial layer 12, referring to fig. 4, the height h2 of the first sub-protrusion 181 in the protrusion structure 18 is greater than or equal to the thickness of the barrier layer 16 and less than the sum of the thicknesses of the barrier layer 16 and the AlN layer 15.
Note that the height h2 of the first sub-bump 181 in the drawing only shows that the thickness larger than the barrier layer 16 is smaller than the sum of the thicknesses of the barrier layer 16 and the AlN layer 15.
Optionally, fig. 5 is a schematic view of another protrusion structure provided in this embodiment. As shown in fig. 5, the height h3 of the first sub-protrusion 181 is greater than or equal to the sum of the thicknesses of the barrier layer 16 and the AlN layer 15, and less than or equal to the sum of the thicknesses of the barrier layer 16, the AlN layer 15, and the GaN layer 14.
Similarly, when the first sub-protrusion 181 in the protrusion structure 18 extends in the direction of the buffer layer 11 and the substrate 10 to reach the GaN layer 14 in the epitaxial layer 12, referring to fig. 5, the height h3 of the first sub-protrusion 181 is greater than or equal to the sum of the thicknesses of the barrier layer 16 and the AlN layer 15 and less than or equal to the sum of the thicknesses of the barrier layer 16, the AlN layer 15, and the GaN layer 14.
With the arrangement, the contact area between the metal electrode layer 13 and the epitaxial layer 12 is greatly increased, and the ohmic contact resistance can be greatly reduced on the basis of an ohmic contact electrode forming mechanism, so that the on-resistance of the GaN device is reduced.
Also, fig. 5 shows only that the height h3 of the first sub-bump 181 is greater than the sum of the thicknesses of the barrier layer 16 and the AlN layer 15, and less than the sum of the thicknesses of the barrier layer 16, the AlN layer 15, and the GaN layer 14.
Optionally, a cross-sectional shape of the first sub-protrusion perpendicular to the first direction is a circle, and the first direction is a stacking direction of the substrate and the buffer layer.
The GaN device is divided along a first direction by using a source electrode and a drain electrode in the GaN device as first sub-bulges positioned on one side of the epitaxial layer, which is far away from the substrate, and the cross section of each first sub-bulge is circular.
It should be noted that, in other embodiments, the shape of the first sub-protrusion may also be other than a circle, which is not limited herein.
Optionally, fig. 6a to 6g are top views of a source metal layer or a drain metal layer provided in this embodiment. As shown in fig. 6a to 6g, the plurality of first sub-protrusions 181 in the source 171 region may be arranged in a matrix 6a, a circle 6b, a rectangle 6c, a zigzag 6d, an X-shape 6e, two squares 6f whose diagonal lines are located on the same straight line, or in a staggered row structure 6g, and the plurality of first sub-protrusions of the drain region may also be arranged in a matrix, a circle, a rectangle, a zigzag, an X-shape, two squares whose diagonal lines are located on the same straight line, or in a staggered row structure.
It should be noted that the first protrusions of the source and the drain may be arranged in other patterns, which is not limited herein.
The arrangement of the raised structures on the source or drain metal layer is the same, and the source 171 metal layer is taken as an example for illustration.
Specifically, referring to fig. 6, there are various arrangement modes of the first sub-protrusions in the protrusion structure extending into the epitaxial layer toward the substrate side in the source-drain metal layer. When the at least one first sub-protrusion 181 is arranged in a matrix, a circle, a rectangle, a zigzag, an X shape, two squares having diagonal lines on the same line, or a plurality of staggered rows, each first sub-protrusion 181 may have a size of 50-500nm, and the interval between every two first sub-protrusions 181 is maintained between 50-500 nm.
Fig. 7 is a schematic flow chart of a method for manufacturing a GaN device according to an embodiment of the present invention. The method is suitable for preparing the GaN device in any embodiment, and as shown in FIG. 7, the preparation method specifically comprises the following steps:
and S710, providing a substrate.
After a substrate is provided, the substrate is cleaned by adopting an ultrasonic cleaning process to remove impurities on the surface of the substrate.
Specifically, the substrate is ultrasonically cleaned by acetone for 5 minutes, then ultrasonically cleaned by isopropyl alcohol for 10 minutes, finally cleaned by deionized water for 10 minutes, and dried by nitrogen after cleaning is finished, so that the purpose of removing impurities on the surface of the substrate is achieved.
Acetone and isopropyl alcohol are representative compounds of aliphatic ketones, can dissolve substances, can be used as a safe fusion splicer, do not cause harm to human health, and do not adversely affect the environmental level of a workplace, and thus can be used as a solution for ultrasonic cleaning.
S720, sequentially forming a buffer layer, an epitaxial layer and a metal electrode layer on the substrate, wherein the epitaxial layer comprises a GaN layer, an AlN layer and a barrier layer which are sequentially stacked on the substrate, and the metal electrode layer comprises a source drain metal layer.
The source-drain metal layer comprises a plurality of protruding structures extending into the epitaxial layer towards one side of the substrate.
The technical scheme provided by the embodiment comprises providing a substrate, sequentially forming a buffer layer, an epitaxial layer and a metal electrode layer on the substrate, wherein the epitaxial layer comprises a GaN layer, an AlN layer and a barrier layer which are sequentially laminated on the substrate, the metal electrode layer comprises a source drain metal layer, wherein the source-drain metal layer comprises a plurality of convex structures extending into the epitaxial layer towards one side of the substrate, and the source electrode and the drain electrode in the metal electrode layer are both contacted with the epitaxial layer to form an ohmic contact electrode, and the source and drain metal electrode layers are provided with a convex structure extending into the epitaxial layer towards one side of the substrate, so that the contact area of the metal electrode layer and the epitaxial layer is increased, the ohmic contact resistance is reduced, in the GaN device, the main factor influencing the on-resistance is the ohmic contact resistance, and when the ohmic contact resistance is reduced, the on-resistance is also reduced, so that the overall reliability of the GaN device is improved.
Fig. 8 is a schematic flow chart of sequentially forming a buffer layer, an epitaxial layer, and a metal electrode layer on a substrate according to an embodiment of the present invention. As shown in fig. 8, the method specifically includes the following steps:
and S810, sequentially forming a buffer layer and an epitaxial layer on the substrate.
And S820, forming a first hard mask layer and a second hard mask layer which are stacked on the epitaxial layer.
It should be noted that, in this embodiment, the dual-layer hard mask is provided to avoid affecting the sidewalls of the device during the patterning process.
Specifically, after a buffer layer and an epitaxial layer are formed on a substrate, the buffer layer and the epitaxial layer are placed in a plasma enhanced chemical vapor deposition device as an integral structure, and a layer of SiO is plated on the surface of the epitaxial layer by adopting an evaporation method2Or Si3N4In SiO by electron beam evaporation process2Or Si3N4The surface is plated with a layer of Cr or Ni metal. Plasma coupled etching process is adopted to etch SiO2Or Si3N4And etching the layer and the Cr or Ni metal layer to form a first hard mask layer and a second hard mask layer which are stacked.
In the cvd apparatus, a gas is excited to generate a low-temperature plasma, thereby enhancing the chemical activity of a reaction material and performing epitaxy.
In addition, SiO is plated on the surface of the epitaxial layer2Or Si3N4The thickness of the layer is in the range of 100-500nm in SiO2Or Si3N4The thickness of the surface-plated Cr or Ni metal layer is in the range of 10-30nm。
It should be further noted that after the first hard mask layer and the second hard mask layer are formed, the substrate, the buffer layer, the epitaxial layer, the first hard mask layer, and the second hard mask layer are cleaned by the ultrasonic cleaning process in the above steps, so as to remove organic matters remaining on the surface of the overall structure.
And S830, patterning the first hard mask layer and the second hard mask layer, and patterning the epitaxial layer by using the patterned first hard mask layer and the patterned second hard mask layer as masks to form a plurality of first grooves on the epitaxial layer.
Specifically, on the basis of the above embodiment, the first hard mask layer and the second hard mask layer are patterned by using an electronic lithography technique to define a patterned pattern of the source and drain regions of the GaN device. And patterning the epitaxial layer by using the patterned first hard mask layer and the patterned second hard mask layer as masks and adopting an electronic photoetching technology, so that the epitaxial layer is positioned in the source electrode area and the drain electrode area to form a plurality of first grooves.
And S840, removing the first hard mask layer and the second hard mask layer.
And etching the whole structure consisting of the substrate, the buffer layer, the epitaxial layer, the first hard mask layer and the second hard mask layer by adopting a plasma coupled etching process and a BOE etching process so as to remove the first hard mask layer and the second hard mask layer.
Specifically, the integral structure is placed into a metal etching solution and a BOE solution to be soaked for 10 minutes, then deionized water is used for washing for 10 minutes, and after the belt is washed, nitrogen is used for drying.
And S850, forming a source drain metal layer on one side, far away from the substrate, of the epitaxial layer, and filling the first groove with the source drain metal layer.
Specifically, after the first hard mask layer and the second hard mask layer are removed, an integral structure comprising a substrate, a buffer layer, an epitaxial layer and a first groove formed by the epitaxial layer in a source region and a drain region is formed, the integral structure is sequentially subjected to a photoresist coating process, a pre-baking process, a photoetching process, a developing process and a post-baking process to form a patterned metal layer of the source electrode and the drain electrode, and on the basis, the source electrode and the drain electrode metal layer are filled in the source electrode and the drain electrode region by adopting an electron beam evaporation process to form a patterned ohmic contact electrode.
And S860, forming other metal layers in the metal electrode layer.
It should be noted that, in some other embodiments, after the plurality of first grooves are formed in the other electrode regions of the metal electrode layer in the epitaxial layer, the corresponding metal layer is filled in the other electrode regions by using an electron beam evaporation process to form the other metal electrode layers.
Illustratively, the gate metal layer is formed on a side of the epitaxial layer remote from the substrate.
The following is a specific description of the preparation method of the present invention for sequentially forming a buffer layer, an epitaxial layer and a metal electrode layer on a substrate.
Fig. 9a to 9g are schematic process diagrams of a preparation method for sequentially forming a buffer layer, an epitaxial layer and a metal electrode layer on a substrate according to an embodiment of the present invention. Referring to fig. 9a, a buffer layer 11 and an epitaxial layer 12 are sequentially formed on a substrate 10.
The epitaxial layer 12 includes a barrier layer 16, an AlN layer 15, and a GaN layer 14.
Referring to fig. 9b-9c, a first hard mask layer and a second hard mask layer are stacked on the epitaxial layer 12.
Wherein, a layer of SiO is plated on the surface of the epitaxial layer by adopting an evaporation method2Or Si3N4Layer 19.
Depositing a layer of SiO on the epitaxial layer 122Or Si3N4After layer 19, an electron beam evaporation process is used to deposit on the SiO2Or Si3N4A Cr or Ni metal layer 20 is plated on the surface of the layer 19, and SiO is plated on the surface2Or Si3N4A layer 20 of Cr or Ni metal is deposited on the layer 19 to form a first and second hardmask layer in a stack.
Referring to fig. 9 d-9 e, the first hard mask layer and the second hard mask layer are patterned, and the epitaxial layer is patterned using the patterned first hard mask layer and the patterned second hard mask layer as masks to form a plurality of first recesses in the epitaxial layer.
Specifically, in addition to fig. 9c, the first hard mask layer and the second hard mask layer formed are patterned with reference to fig. 9 d. Next, referring to fig. 9e, the epitaxial layer 12 is patterned using the patterned first and second hard mask layers as masks to form a plurality of first recesses 21 in the epitaxial layer 12.
Referring to fig. 9f, the first hard mask layer and the second hard mask layer are removed.
Referring to fig. 9g, a source drain metal layer 17 is formed on the side of the epitaxial layer 12 away from the substrate 10, and the source drain metal layer 17 fills the first recess 21.
Fig. 10 is a schematic flow chart of sequentially forming a buffer layer, an epitaxial layer, and a metal electrode layer on a substrate according to another embodiment of the present invention. As shown in fig. 10, the method specifically includes the following steps:
and S1010, sequentially forming a buffer layer and an epitaxial layer on the substrate.
And S1020, patterning the epitaxial layer to form a plurality of second grooves on the epitaxial layer.
Wherein, before forming a plurality of second recesses on the epitaxial layer, still include: and sequentially carrying out a glue homogenizing process, a pre-baking process, a photoetching process, a developing process and a post-baking process on the whole structure consisting of the substrate, the buffer layer and the epitaxial layer so as to define ohmic contact regions of a source electrode and a drain electrode on the epitaxial layer.
Specifically, the barrier layer of the source electrode contact region and the barrier layer of the drain electrode contact region are etched by adopting a plasma coupling etching process, and a plurality of second grooves are formed in the epitaxial layer.
And S1030, forming a first hard mask layer on one side, far away from the substrate, of the epitaxial layer, wherein the first hard mask layer fills the plurality of second grooves.
After the plurality of second grooves are formed, the substrate, the buffer layer, the epitaxial layer and the plurality of second grooves formed in the epitaxial layer form an integral structure, the integral structure is sequentially cleaned for 5 minutes through acetone by adopting an ultrasonic cleaning process, then cleaned for 10 minutes through acetone, and after the cleaning is finished, the integral structure is washed for 10 minutes by deionized water and then dried by nitrogen to remove organic matters remained on the surface of the integral structure.
Specifically, the integral structure is placed into plasma enhanced chemical vapor deposition equipment, and a layer of SiO is plated on the surface of an epitaxial layer by adopting an evaporation method2Or Si3N4And forming a first hard mask layer on one side of the epitaxial layer, which is far away from the substrate, wherein the first hard mask layer fills the plurality of second grooves formed in the epitaxial layer.
And S1040, forming a second hard mask layer on the first hard mask layer.
Specifically, the electron beam evaporation process is adopted to deposit SiO2Or Si3N4Plating a layer of Cr or Ni metal on the surface, and forming a second hard mask layer on the first hard mask layer.
And S1050, patterning the first hard mask layer and the second hard mask layer in the region where the second groove is located, so as to form a plurality of third grooves in the first hard mask layer and the second hard mask layer in the second groove region.
Specifically, on the basis of forming the second groove, the first hard mask layer and the second hard mask layer in the region where the second groove is located are etched by adopting an electron beam lithography technology, and a patterned graph of a third groove in the source electrode region and the drain electrode region is formed.
And S1060, forming a plurality of fourth grooves in the epitaxial layer under the second grooves by taking the patterned first hard mask layer and the patterned second hard mask layer as masks.
Specifically, on the basis of forming the second grooves, a plurality of fourth grooves are formed in the epitaxial layer below the second grooves by adopting a plasma coupling etching process, so that the fourth grooves are located in part of the AlN layer and part of the GaN layer.
And S1070, removing the double-layer hard mask layer.
It should be noted that, as in the method for removing the mask layer in the foregoing embodiment, the plasma coupling etching process and the BOE etching process are used to etch the entire structure formed by the substrate, the buffer layer, the epitaxial layer, the first hard mask layer, the second groove, the third groove, and the fourth groove, so as to remove the first hard mask layer and the second hard mask layer.
And S1080, forming a source-drain metal layer on one side, far away from the substrate, of the epitaxial layer, and filling the source-drain metal layer in the second groove and the fourth groove.
And S1090, forming other metal layers in the metal electrode layer.
The following describes a method for sequentially forming a buffer layer, an epitaxial layer and a metal electrode layer on a substrate according to another embodiment of the present invention.
Referring to fig. 9a, a buffer layer 11 and an epitaxial layer 12 are sequentially formed on a substrate.
Fig. 11a to 11g are schematic process diagrams of another preparation method for sequentially forming a buffer layer, an epitaxial layer and a metal electrode layer on a substrate according to an embodiment of the present invention. Referring to fig. 11a, the epitaxial layer is patterned to form a plurality of second recesses 22 on the epitaxial layer 12.
Referring to FIG. 11b, a layer of SiO is deposited on epitaxial layer 122Or Si3N4Layer 19 to form a first hard mask layer.
Referring to fig. 11c, a layer of SiO is deposited on epitaxial layer 122Or Si3N4After layer 19, it is necessary to be on SiO2Or Si3N4A layer 20 of Cr or Ni metal is deposited on the layer 19 to form a second hard mask layer.
Specifically, the electron beam evaporation process is adopted to deposit SiO2Or Si3N4The surface of layer 19 is plated with a Cr or Ni metal layer 20. A first hard mask layer is formed on the side of the epitaxial layer 12 remote from the substrate 10, the first hard mask layer filling the plurality of second recesses 22.
Referring to fig. 11d, the first and second hard mask layers in the region of the second recess are patterned to form a plurality of third recesses 23 in the first and second hard mask layers in the second recess region.
Referring to fig. 11e, a plurality of fourth grooves 24 are formed in the epitaxial layer 12 under the second grooves by using the patterned first and second hard mask layers as masks.
Referring to fig. 11f, the first hard mask layer and the second hard mask layer are removed.
Referring to fig. 11g, a source-drain metal layer is formed on one side of the epitaxial layer away from the substrate, and the source-drain metal layer fills the second groove and the fourth groove.
Fig. 12 is a schematic flow chart of sequentially forming a buffer layer, an epitaxial layer, and a metal electrode layer on a substrate according to another embodiment of the present invention. As shown in fig. 12, the method specifically includes the following steps:
and S1210, sequentially forming a buffer layer and an epitaxial layer on the substrate.
And S1220, forming a metal film on the epitaxial layer and performing an annealing process.
Wherein the annealing process is a metal heat treatment process, which heats the metal to a certain temperature, holds for a sufficient time, and then cools at a suitable rate to reduce the hardness and reduce the tendency of structural deformation and cracking.
Specifically, the substrate, the buffer layer and the epitaxial layer are used as an integral structure, and an electron beam evaporation process is adopted to evaporate a metal film on the surface of the integral structure, wherein the metal film can be Ni, Ti or Al metal. The annealing process is adopted to carry out the annealing process on the whole structure coated with the metal film within the range of 300-600 ℃, and the effect is best within the range of 5-10 minutes.
And S1230, defining a source electrode area and a drain electrode area by using an external mask plate, and exposing the upper surfaces of the barrier layers in the source electrode area and the drain electrode area.
In order to better define the position of a source/drain region on the epitaxial layer on the basis of protecting the original structure, an external mask plate can be arranged outside a manufacturer.
And S1240, etching the barrier layer by using the metal film subjected to annealing treatment in the region where the source electrode is located and the region where the drain electrode is located as a mask and adopting an ICP (inductively coupled plasma) process to form a plurality of fifth grooves on the barrier layer.
Specifically, the positions of the source and drain regions on the barrier layer are etched by using a plasma coupled etching process (ICP), and a plurality of fifth grooves are formed on the barrier layer.
It should be noted that, when the barrier layer is etched by the plasma coupled etching process, the etching depth ranges from 10nm to 30 nm.
S1250, removing the external mask plate and the metal film.
Specifically, the substrate, the buffer layer, the epitaxial layer and the fifth groove are taken as an integral structure, the integral structure is cleaned by an ultrasonic cleaning process, acetone is specifically adopted for cleaning for 5 minutes, then the acetone is used for cleaning for 10 minutes, after the cleaning is completed, deionized water is used for washing for 10 minutes and then nitrogen is used for blow-drying, so that the external mask plate on the surface of the integral structure is removed, and finally the metal film on the surface of the integral structure is removed by soaking of metal stripping liquid.
And S1260, forming a source drain metal layer on one side of the epitaxial layer, which is far away from the substrate, wherein the source drain metal layer fills the fifth groove.
The substrate, the buffer layer, the epitaxial layer and the fifth groove are used as an integral structure, a glue homogenizing process, a pre-baking process, a photoetching process, a developing process and a post-baking process are sequentially adopted, a source electrode and a drain electrode are defined to be positioned above the epitaxial layer to form a source drain metal layer, the source drain metal layer is deposited in the fifth groove by an electron beam evaporation process, and a patterned ohmic contact electrode is formed.
And S1270, forming other metal layers in the metal electrode layer.
The following describes a method for sequentially forming a buffer layer, an epitaxial layer and a metal electrode layer on a substrate according to another embodiment of the present invention.
With continued reference to fig. 9a, a buffer layer and an epitaxial layer are sequentially formed on the substrate.
Fig. 13a to 13f are schematic process diagrams of another preparation method for sequentially forming a buffer layer, an epitaxial layer and a metal electrode layer on a substrate according to an embodiment of the present invention. Referring to fig. 13a-13 b, a metal film 25 is formed on the epitaxial layer 12 and an annealing process is performed.
Specifically, a metal thin film 25 is deposited on the surface of the epitaxial layer 12, and the metal thin film 25 may be Ni, Ti, or Al metal. Next, referring to fig. 13b, the entire structure plated with the metal thin film is subjected to an annealing process using an annealing process.
Referring to fig. 13c, an external mask 26 is used to define the source region and the drain region, exposing the upper surface of the barrier layer 16 in the source region and the drain region.
Referring to fig. 13d, the barrier layer is etched by using the ICP process with the annealed metal film in the region of the source electrode 171 and the annealed metal film in the region of the drain electrode 172 as a mask, so as to form a plurality of fifth grooves 27 on the barrier layer 16.
Referring to fig. 13e, the external mask and the metal thin film are removed.
Referring to fig. 13f, a source drain metal layer is formed on the side of the epitaxial layer away from the substrate, and the source drain metal layer fills the fifth groove 27
Fig. 14 is a schematic flow chart of sequentially forming a buffer layer, an epitaxial layer, and a metal electrode layer on a substrate according to another embodiment of the present invention. As shown in fig. 14, the method specifically includes the following steps:
and S1410, sequentially forming a buffer layer and an epitaxial layer on the substrate.
And S1420, etching the barrier layer by adopting an ICP (inductively coupled plasma) process to form a plurality of sixth grooves on the barrier layer so as to expose the upper surfaces of the barrier layer in the region where the source electrode is located and the region where the drain electrode is located.
Before forming the sixth groove on the barrier layer, the substrate, the buffer layer and the epitaxial layer are used as an integral structure, and the positions of the source electrode region and the drain electrode region on the upper surface of the barrier layer of the epitaxial layer are defined by adopting a photoresist homogenizing process, a pre-baking process, a photoetching process, a developing process and a post-baking process in sequence.
And etching the source electrode area and the drain electrode area in the area of the barrier layer by adopting a plasma coupled etching (ICP) process to form a plurality of sixth grooves, wherein the upper surfaces of the barrier layer in the area where the source electrode is located and the area where the drain electrode is located are exposed.
And S1430, forming a metal film on the epitaxial layer and performing an annealing process.
It should be noted that, the metal film formation and annealing process in this embodiment are the same as those in the above embodiment, and are not described herein again.
And S1440, patterning the epitaxial layer below the sixth groove by taking the annealed metal films in the region where the source electrode is located and the region where the drain electrode is located as masks to form a plurality of seventh grooves.
Specifically, the substrate, the buffer layer, the epitaxial layer, the fifth groove and the annealed metal mask are of an integral structure, and the source electrode region and the drain electrode region are defined on the upper surface of the barrier layer of the epitaxial layer by adopting a photoresist coating process, a pre-baking process, a photoetching process, a developing process and a post-baking process. And etching the source electrode region and the drain electrode region in the sixth grooves in the barrier layer by adopting an ICP (inductively coupled plasma) etching process, and forming a seventh groove under the sixth grooves along the extending direction of the buffer layer and the substrate.
It should be noted that, when the IPC etching process is used to etch one of the seventh grooves, the etching depth ranges from 10nm to 30 nm.
And S1450, removing the external mask plate and the metal film.
It should be noted that, in this embodiment, the process of removing the external mask and the metal film is the same as that in the above embodiment, and details are not described here.
And S1460, forming a source drain metal layer on one side, far away from the substrate, of the epitaxial layer, and filling the sixth groove and the seventh groove with the source drain metal layer.
It should be noted that the process of depositing the source/drain metal layers in the sixth recess and the seventh recess is the same as the process of filling the fifth recess in the above embodiment, and details are not described here.
And S1470, forming other metal layers in the metal electrode layer.
The following describes a method for sequentially forming a buffer layer, an epitaxial layer and a metal electrode layer on a substrate according to another embodiment of the present invention.
With continued reference to fig. 9a, a buffer layer and an epitaxial layer are sequentially formed on the substrate.
Fig. 15a to 15g are schematic process diagrams of another preparation method for sequentially forming a buffer layer, an epitaxial layer and a metal electrode layer on a substrate according to an embodiment of the present invention. Referring to fig. 15a, the barrier layer is etched using an ICP process to form a plurality of sixth grooves 28 on the barrier layer to expose the upper surface of the barrier layer 16 in the region of the source electrode 171 and the region of the drain electrode 172.
Referring to fig. 15b-15c, a metal film 25 is formed on the epitaxial layer and an annealing process is performed.
It should be noted that, in the present embodiment, the specific methods for forming the metal film and performing the annealing process are the same as those in the above embodiments, and are not described herein again.
Referring to fig. 15d to 15e, the metal film after the annealing treatment in the region where the source electrode is located and the region where the drain electrode is located is used as a mask, and a plurality of seventh grooves 29 are formed in the epitaxial layer 12 under the sixth grooves by patterning.
Referring to fig. 15f, the external mask and the metal thin film are removed.
Referring to fig. 15g, a source drain metal layer 30 is formed on the side of the epitaxial layer 12 remote from the substrate 10, and fills the sixth recess 28 and the seventh recess 29.
According to the technical scheme provided by the embodiment of the invention, the epitaxial layer is etched to form the patterning through the electron beam lithography process and the metal annealing process, so that the protruding structure of the metal electrode layer positioned above the epitaxial layer is in contact with any one layer of the epitaxial layer along the extending directions of the buffer layer and the substrate, and an ohmic contact electrode mechanism is formed, the contact area of the metal electrode layer and the epitaxial layer is effectively increased, the ohmic contact resistance is reduced, the on resistance of the device is reduced, and the overall performance of the device is improved.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (13)

1. A GaN device, comprising:
the epitaxial layer comprises a GaN layer, an AlN layer and a barrier layer which are sequentially stacked on the substrate, and the metal electrode layer comprises a source drain metal layer;
the source drain metal layer comprises a protruding structure extending into the epitaxial layer towards one side of the substrate.
2. The GaN device of claim 1 wherein the bump structure comprises a plurality of first sub-bumps.
3. The GaN device of claim 2 wherein the bump structure further comprises a second sub-bump on a side of the first sub-bumps remote from the substrate, the second sub-bump being connected to the first sub-bumps.
4. The GaN device of claim 2 wherein the height of the first sub-bump is less than the thickness of the barrier layer.
5. The GaN device of claim 2 wherein the height of the first sub-bump is greater than or equal to the thickness of the barrier layer less than the sum of the thicknesses of the barrier layer and the AlN layer.
6. The GaN device of claim 2 wherein the height of the first sub-bump is greater than or equal to the sum of the thicknesses of the barrier layer and the AlN layer, and less than or equal to the sum of the thicknesses of the barrier layer, the AlN layer, and the GaN layer.
7. The GaN device of claim 2 wherein a cross-sectional shape of the first sub-bump perpendicular to the first direction is a circle, the first direction being a stacking direction of the substrate and the buffer layer.
8. The GaN device of claim 2 wherein the source drain metal layer comprises a source electrode and a drain electrode, wherein the plurality of first sub-bump arrangements of the source electrode comprise, but are not limited to, a matrix, a circle, a rectangle, a zigzag, an X-shape, two squares with diagonals in the same line, or a plurality of staggered row structures, and the plurality of first sub-bump arrangements of the drain electrode comprise, but are not limited to, a matrix, a circle, a rectangle, a zigzag, an X-shape, two squares with diagonals in the same line, or a plurality of staggered row structures.
9. A method for fabricating a GaN device, comprising:
providing a substrate;
sequentially forming a buffer layer, an epitaxial layer and a metal electrode layer on the substrate, wherein the epitaxial layer comprises a GaN layer, an AlN layer and a barrier layer which are sequentially stacked on the substrate, and the metal electrode layer comprises a source drain metal layer;
the source drain metal layer comprises a plurality of protruding structures extending into the epitaxial layer towards one side of the substrate.
10. The method of claim 9, wherein sequentially forming a buffer layer, an epitaxial layer, and a metal electrode layer on the substrate comprises:
sequentially forming a buffer layer and an epitaxial layer on the substrate;
forming a first hard mask layer and a second hard mask layer which are stacked on the epitaxial layer;
patterning the first hard mask layer and the second hard mask layer, and patterning the epitaxial layer by taking the patterned first hard mask layer and the patterned second hard mask layer as masks to form a plurality of first grooves in the epitaxial layer;
removing the first hard mask layer and the second hard mask layer;
forming a source drain metal layer on one side of the epitaxial layer, which is far away from the substrate, wherein the source drain metal layer fills the first groove;
and forming other metal layers in the metal electrode layer.
11. The method of claim 9, wherein sequentially forming a buffer layer, an epitaxial layer, and a metal electrode layer on the substrate comprises:
sequentially forming a buffer layer and an epitaxial layer on the substrate;
patterning the epitaxial layer to form a plurality of second grooves on the epitaxial layer;
forming a first hard mask layer on one side, far away from the substrate, of the epitaxial layer, wherein the first hard mask layer fills the plurality of second grooves;
forming a second hard mask layer on the first hard mask layer;
patterning the first hard mask layer and the second hard mask layer in the area of the second groove to form a plurality of third grooves in the first hard mask layer and the second hard mask layer in the area of the second groove;
forming a plurality of fourth grooves in the epitaxial layer below the second groove by taking the patterned first hard mask layer and the patterned second hard mask layer as masks;
removing the first hard mask layer and the second hard mask layer;
forming a source drain metal layer on one side of the epitaxial layer, which is far away from the substrate, wherein the source drain metal layer fills the second groove and the fourth groove;
forming other metal layers in the metal electrode layer.
12. The method of claim 9, wherein sequentially forming a buffer layer, an epitaxial layer, and a metal electrode layer on the substrate comprises:
sequentially forming a buffer layer and an epitaxial layer on the substrate;
forming a metal film on the epitaxial layer, and performing an annealing process;
an external mask plate is adopted to define a region where the source electrode is located and a region where the drain electrode is located, and the upper surfaces of the barrier layers in the region where the source electrode is located and the region where the drain electrode is located are exposed;
etching the barrier layer by using the metal film subjected to annealing treatment in the region where the source electrode is located and the region where the drain electrode is located as a mask and adopting an ICP (inductively coupled plasma) process to form a plurality of fifth grooves on the barrier layer;
removing the external mask plate and the metal film;
forming a source drain metal layer on one side of the epitaxial layer, which is far away from the substrate, wherein the source drain metal layer fills the fifth groove;
and forming other metal layers in the metal electrode layer.
13. The method of claim 9, wherein sequentially forming a buffer layer, an epitaxial layer, and a metal electrode layer on the substrate comprises:
sequentially forming a buffer layer and an epitaxial layer on the substrate;
etching the barrier layer by adopting an ICP (inductively coupled plasma) process to form a plurality of sixth grooves on the barrier layer so as to expose the upper surface of the barrier layer in the region where the source electrode is located and the region where the drain electrode is located;
forming a metal film on the epitaxial layer, and performing an annealing process;
patterning the epitaxial layer below the sixth groove to form a plurality of seventh grooves by taking the metal film subjected to annealing treatment in the region where the source electrode is located and the region where the drain electrode is located as a mask;
removing the external mask plate and the metal film;
forming a source drain metal layer on one side of the epitaxial layer, which is far away from the substrate, wherein the source drain metal layer fills the sixth groove and the seventh groove;
and forming other metal layers in the metal electrode layer.
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