CN113284807B - Method for manufacturing semiconductor structure - Google Patents

Method for manufacturing semiconductor structure Download PDF

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Publication number
CN113284807B
CN113284807B CN202110816834.XA CN202110816834A CN113284807B CN 113284807 B CN113284807 B CN 113284807B CN 202110816834 A CN202110816834 A CN 202110816834A CN 113284807 B CN113284807 B CN 113284807B
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insulating layer
electrode
layer
substrate
etching
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CN113284807A (en
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林祐丞
杨智强
林子茬
徐钲竤
段厚成
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Jingxincheng Beijing Technology Co Ltd
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Jingxincheng Beijing Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention discloses a manufacturing method of a semiconductor structure, which comprises the following steps: providing a substrate; forming an electrode on the substrate; forming an insulating layer on the electrode, wherein the insulating layer covers the top and the side wall of the electrode and the substrate; forming a photoresist layer on the insulating layer; etching the photoresist layer to the top of the insulating layer; etching the insulating layer on top of the electrode to a thickness equal to the thickness of the insulating layer on the substrate; and removing the photoresist layer and etching the insulating layer to form a gap wall. The manufacturing method of the semiconductor structure can improve the quality of the semiconductor structure.

Description

Method for manufacturing semiconductor structure
Technical Field
The invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a manufacturing method of a semiconductor structure.
Background
In the semiconductor manufacturing process, the thickness of the formed semiconductor layer is not uniform due to the accuracy problem of the semiconductor device. Particularly, when a semiconductor layer is deposited on the electrode, the bottom of the electrode has a certain distance from the top, and the side wall of the electrode is in a vertical structure. The semiconductor layers with different thicknesses easily affect the quality of the finally obtained semiconductor device. When the semiconductor layer on the electrode needs to be etched, the semiconductor layer at the bottom of the electrode is easily etched, but the semiconductor layer at the top of the electrode still has a certain thickness, which affects the shape and quality of the finally obtained semiconductor.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor structure, and the quality of the semiconductor structure is improved through the manufacturing method of the semiconductor structure.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention provides a manufacturing method of a semiconductor structure, which comprises the following steps:
providing a substrate;
forming an electrode on the substrate;
forming an insulating layer on the electrode, wherein the insulating layer covers the top and the side wall of the electrode and the substrate;
forming a photoresist layer on the insulating layer;
etching the photoresist layer to the top of the insulating layer;
etching the insulating layer on top of the electrode to a thickness equal to the thickness of the insulating layer on the substrate;
and removing the photoresist layer and etching the insulating layer to form a gap wall.
In an embodiment of the invention, the insulating layer includes a first insulating layer covering the top and the sidewalls of the electrode and the substrate, and the first insulating layer is made of silicon dioxide.
In an embodiment of the invention, the insulating layer includes a second insulating layer, the second insulating layer covers the first insulating layer, and the second insulating layer is made of silicon nitride.
In an embodiment of the invention, the insulating layer includes a third insulating layer, the third insulating layer covers the second insulating layer, and the third insulating layer is made of silicon dioxide.
In an embodiment of the invention, the thickness of the first insulating layer is 7.5 to 20nm, and the thickness of the second insulating layer is 15 to 25 nm.
In an embodiment of the invention, a gap is formed between adjacent electrodes, the photoresist layer covers the insulating layer and the gap, and the photoresist layer is higher than the insulating layer.
In one embodiment of the present invention, etching the photoresist layer to the top of the insulating layer comprises: and etching the photoresist layer by adopting a dry etching method to ensure that the photoresist layer is equal to the insulating layer on the top of the electrode in height.
In one embodiment of the present invention, etching the insulating layer on top of the electrode comprises: and etching back the insulating layer on the top of the electrode under the protection of the photoresist layer.
In an embodiment of the invention, after the spacer is obtained, the first insulating layer with a thickness of 50-70 angstroms is formed on the substrate.
In an embodiment of the present invention, the spacer includes a first insulating layer, a second insulating layer, and a third insulating layer formed on the sidewall of the electrode.
In the manufacturing method of the semiconductor structure provided by the invention, the quality of the gap wall is improved by arranging the multiple insulating layers; the electrode and the substrate are provided with the light resistance layers, so that only the light resistance layer at the position with thicker etching thickness is ensured to be etched, and the thicknesses of the light resistance layers at all positions after etching are kept consistent; by ensuring the consistency of the thickness of the photoresist layer, the problem that the residual insulating layer is arranged on the top of the electrode and the substrate is etched in the process of forming the gap wall is ensured. The manufacturing method of the semiconductor structure provided by the invention solves the problem that the thicknesses of the insulating layers are not uniform at all positions, and maintains the appearance of the spacer so as to improve the quality of a semiconductor.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flow chart of a method of fabricating a semiconductor structure.
Fig. 2 is a diagram of a semiconductor structure corresponding to steps S1 to S2 in this embodiment.
Fig. 3 is a diagram of a semiconductor structure corresponding to step S3 in this embodiment.
Fig. 4 is a diagram of a semiconductor structure corresponding to step S4 in this embodiment.
Fig. 5 is a diagram of a semiconductor structure corresponding to step S5 in this embodiment.
Fig. 6 is a diagram of a semiconductor structure corresponding to step S6 in this embodiment.
Fig. 7 is a diagram illustrating a structure of a semiconductor after the photoresist is removed in step S7 according to the present embodiment.
Fig. 8 is a diagram illustrating a structure of a semiconductor device after forming the spacer in step S7 in this embodiment.
Fig. 9 is a electron microscope image of the semiconductor structure corresponding to step S3 in this embodiment.
FIG. 10 is an electron microscope image of a semiconductor structure after a first direct etch of the insulating layer without the addition of photoresist.
FIG. 11 is an electron microscope image of a semiconductor structure after a second direct etch of the insulating layer with photoresist added.
Fig. 12 is a schematic electron microscope image of the semiconductor structure after step S7 is performed in this embodiment.
Description of reference numerals:
100 a substrate; 101 electrodes; 102 gap; 200 an insulating layer; 201 a first insulating layer; 202 a second insulating layer; 203 a third insulating layer; 204 a spacer; 300 photo resist layer; the steps S1-S7 are labeled.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, in an embodiment of the present invention, a semiconductor layer is formed with a non-uniform thickness due to the accuracy of the semiconductor device during the fabrication of the semiconductor structure. As shown in the electron microscope image of the semiconductor structure before etching shown in fig. 9 and the electron microscope image of the semiconductor structure after etching shown in fig. 11, a plurality of insulating layers are provided on the electrodes. In a normal condition, the insulating layer is etched to form the sidewall, as shown in fig. 11, after a plurality of etching, the insulating layer with a certain thickness is still on the electrode, the insulating layer at the bottom of the electrode is completely etched, and a part of the semiconductor substrate is etched, which easily causes a quality problem of the finally formed semiconductor structure. The manufacturing method of the semiconductor structure provided by the invention can form the gap wall with better appearance and ensure the quality of the semiconductor structure. The present invention is not limited to the type of semiconductor structure and is applicable to all semiconductor structures that require etching to form spacers. In this embodiment, the semiconductor structure is, for example, a power device.
Referring to fig. 1 to 8, in an embodiment of the present invention, a method for manufacturing a semiconductor structure includes the following steps:
s1: providing a substrate 100;
s2: forming an electrode 101 on a substrate 100;
s3: forming an insulating layer 200 on the electrode 101;
s4: forming a photoresist layer 300 on the insulating layer 200;
s5: etching the photoresist layer 300 to the top of the insulating layer 200;
s6: etching the insulating layer 200 on top of the electrode 100 to make the thickness of the insulating layer 200 on top of the electrode 100 equal to the thickness of the insulating layer 200 on the bottom of the electrode 101;
s7: the photoresist layer 300 is removed and the insulating layer 200 is etched to form the spacers 204.
Referring to fig. 1 to 2 and 8, in step S1, the material and thickness of the substrate 100 are not limited by the invention. In an embodiment of the present invention, the substrate 100 is, for example, a silicon substrate for forming a semiconductor structure, the substrate 100 may include a substrate and a silicon layer disposed above the substrate, the substrate is, for example, a semiconductor substrate material such as silicon (Si), silicon carbide (SiC), sapphire ((Al 2O3), gallium arsenide (GaAs), lithium aluminate (LiAlO2), etc., the silicon layer is formed above the substrate, in this embodiment, phosphorus ions or arsenic ions may be implanted into the silicon layer to form a doped region to form a source or drain region of the semiconductor structure, and the ion implantation process may be performed after the spacer 204 is formed.
Referring to fig. 1-2, in step S2, the number and formation of the electrodes 101 on the substrate 100 are not limited by the present invention. In an embodiment of the invention, the electrodes 101 are, for example, gate electrodes, and the number of the electrodes 101 is one or more. When the number of the electrodes 101 is plural, gaps 102 are formed between the adjacent electrodes 101. In the present embodiment, the method of forming an electrode includes: a polysilicon layer is formed on the substrate 100 by a low pressure chemical vapor deposition method, and the polysilicon layer is etched to form the electrode 101. In this process, the reaction gas is, for example, silane (SiH 4) or dichlorosilane (SiH 2Cl 2).
Referring to fig. 1, 3 and 9, in an embodiment of the invention, the insulating layer 200 in step S3 covers the top of the electrode 101, the sidewall of the electrode 101 and the upper portion of the substrate 100 (the bottom of the electrode 101). The number of the insulating layers 200 is not limited by the invention, and in the present embodiment, the number of the insulating layers 200 is, for example, 3, and the insulating layer 200 specifically includes a first insulating layer 201 formed over the electrode 101, a second insulating layer 202 formed over the first insulating layer 201, and a third insulating layer 203 formed over the second insulating layer 202. The material of the first insulating layer 201 is, for example, silicon dioxide (SiO 2), and the thickness of the first insulating layer 201 is, for example, 7.5 to 20 nm. The material of the second insulating layer 202 is, for example, silicon nitride (Si3N4), and the thickness of the second insulating layer 202 ranges from 15 nm to 25 nm. The material of the third insulating layer 203 is the same as that of the first insulating layer 201, such as silicon dioxide, and the thickness of the third insulating layer 203 is, for example, 30 to 70 nm. In step S3 of the present embodiment, the thickness of the third insulating layer 203 is, for example, 44 to 45nm on the top of the electrode 101, and the thickness of the third insulating layer 203 is, for example, 28 to 30nm on the sidewall of the electrode 101 and the substrate 100 beside the electrode 101.
Referring to fig. 3, in an embodiment of the invention, the first insulating layer 201 and the third insulating layer 203 are formed by a rapid thermal oxidation method at about 1000 ℃ for 3-5 minutes. The second insulating layer 202 may be formed by a low pressure chemical vapor deposition method using dichlorosilane (SiH 2Cl 2) and ammonia (NH 3) as reaction gases to form a silicon nitride layer with a thickness of, for example, 17 to 19nm on the surface of the substrate 100 and the first insulating layer 201.
Referring to fig. 1 and 3, in step S3, the thickness of the insulating layer 200 formed on the top of the electrode 101 is greatly different from the thickness of the insulating layer 200 formed on the sidewall of the electrode 101 and the substrate 100 due to the process. In the present embodiment, the thickness difference between the thickness of the third insulating layer 203 on the top of the electrode 101 and the thickness of the third insulating layer 203 on the sidewall of the electrode 101 and the substrate 100 is, for example, 14 to 17 nm. When the insulating layer 200 is etched, if the insulating layer 200 is directly etched in the vertical direction, when the insulating layer 200 on the top of the electrode 101 is completely etched, the insulating layer 200 on the substrate 100 is completely etched, and a portion of the substrate 100 is etched, which may easily cause the semiconductor structure to be damaged. If it is ensured that the insulating layer 200 on the substrate 100 is just etched completely, the insulating layer 200 on top of the electrode 101 cannot be etched completely. By adopting the steps S4-S7 provided by the invention, the problems that the insulating layer 200 is remained on the top of the electrode 101 and the bottom of the electrode 101 is over-etched can be avoided.
Referring to fig. 1, 3 and 9, in another embodiment of the present invention, the number of the insulating layers 200 is, for example, 2, and the insulating layers 200 specifically include a first insulating layer 201 formed over the electrode 101 and a second insulating layer 202 formed over the first insulating layer 201. The material of the first insulating layer 201 is, for example, silicon dioxide (SiO 2), and the thickness of the first insulating layer 201 is, for example, 7.5 to 200 nm. The material of the second insulating layer 202 is, for example, silicon nitride (Si3N4), and the thickness of the second insulating layer 202 ranges from 7.5 nm to 120 nm. When the thicknesses of the insulating layer 200 at the top and the bottom of the electrode 101 are different, the steps S4 to S7 provided in the present invention can be used to avoid the problem that the insulating layer 200 remains at the top of the electrode 101 and the bottom of the electrode 101 is over-etched after the insulating layer 200 is etched.
Referring to fig. 1, fig. 3 and fig. 4, in an embodiment of the invention, the photoresist layer 300 formed in step S4 covers the insulating layer 200, and the photoresist layer 300 is higher than the electrode 101. In the present embodiment, the photoresist layer 300 covers the gap 102 between the electrodes 101. When the insulating layer 200 on top of the electrode 101 is etched, the insulating layer 200 on the bottom of the electrode 101 may be protected from being etched.
Referring to fig. 1 and 5, in step S5, the photoresist layer 300 is etched by dry etching, so that the photoresist layer 300 is flush with the insulating layer 200 on top of the electrode 101.
Referring to fig. 1 and 6, in step S6, the insulating layer 200 on top of the electrode 101 is etched back under the protection of the photoresist layer 300 until the thickness of the insulating layer 200 on top of the electrode 101 is equal to the thickness of the insulating layer 200 on bottom of the electrode 101. In the present embodiment, after the etching back in step S6, the thickness of the third insulating layer 203 on top of the electrode 101 ranges from 28 nm to 30nm, for example. If the insulating layer 200 is directly etched without adding the photoresist layer 300 in step S6, as shown in fig. 10 to 11, when the insulating layer 200 is etched for the first time, the thickness of the third insulating layer 203 on the top of the electrode 101 is, for example, 95 angstroms, the third insulating layer 203 on the bottom of the electrode 101 is completely etched, the second insulating layer 202 under the third insulating layer 203 is etched, for example, 80 angstroms, and more than half of the thickness of the second insulating layer 202 is etched. When the insulating layer 200 is etched again, the insulating layer 200 on the top of the electrode 101 may remain or the insulating layer 200 on the bottom of the electrode 101 may be excessively etched.
Referring to fig. 1, 6 to 8, in an embodiment of the present invention, the step S7 includes two steps of removing the photoresist layer 300 and etching the insulating layer 200. The invention is not limited to the etching type, and in the embodiment, as shown in fig. 7, the photoresist layer 300 may be removed by, for example, dry etching, specifically, oxygen plasma etching is used to remove the photoresist layer 300 in the chamber. After the photoresist layer 300 is etched, the insulating layer 200 is etched to form spacers 204, as shown in FIG. 8. In the present embodiment, after the second etching of the insulating layer 200, the second insulating layer 202 and the third insulating layer 203 on the top and bottom of the electrode 101 are completely etched, and only the first insulating layer 201 with a thickness ranging from 50 to 70 angstroms is remained. On the sidewall of the electrode 101, the formed spacer 204 includes the first insulating layer 201, the second insulating layer 202 and the third insulating layer 203, which are not completely etched, and the thickness of the spacer 204 is smaller on the side close to the top of the electrode 101, the thickness of the spacer 204 is gradually larger along the direction close to the bottom of the electrode 101, and when the spacer is close to the bottom of the electrode 101, the first insulating layer 201 and the second insulating layer 202 are not etched, and the third insulating layer 203 is partially etched to form the spacer 204 with better appearance and quality. Referring to fig. 12, in the present embodiment, the third insulating layers 203 on two sides of the electrode 101 have thicknesses of, for example, 25.6nm and 26.4nm, respectively, when approaching the bottom of the electrode 101.
Referring to fig. 3, fig. 7 to fig. 11, fig. 9 is a electron microscope image of the semiconductor structure corresponding to step S3 in this embodiment. In an embodiment of the present invention, the thickness of the third insulating layer 203 is, for example, 44.5nm on the top of the electrode 101, and the thickness of the third insulating layer 203 is, for example, 28.6nm on the sidewall of the electrode 101. On both sides of the electrode 101 on the substrate 100, the thickness of the third insulating layer 203 is, for example, 29.8nm and 29.2nm, respectively. The third insulating layer 203 on top of the electrode 101 and the third insulating layer 203 on the bottom of the electrode 101 have a difference in thickness of, for example, 14.7nm and 15.3nm, respectively. After the first direct etching of the insulating layer 200 without adding the photoresist layer as a mask, referring to fig. 10, the third insulating layer 203 on the top of the electrode 101 has a thickness of, for example, 95 angstroms, while the third insulating layer 203 on the bottom of the electrode 101 is completely etched, and the second insulating layer 202 is etched away by, for example, 80 angstroms. After the second direct etching of the insulating layer 200, referring to fig. 11, the top of the electrode 101 has a certain thickness of the first insulating layer 201, and the substrate 100 at the bottom of the electrode 101 is etched to a thickness of, for example, 31 angstroms. On the substrate 100 on both sides of the electrode 101, ions are typically doped to form doped regions, and the substrate is etched to damage the function of the semiconductor structure. Referring to fig. 12, when the insulating layers 200 on the top and bottom of the electrode 101 are first made to have a uniform thickness and then etched, the insulating layer 200 on the top of the electrode 101 is completely etched, and the bottom of the electrode 101 has a first insulating layer 201 with a thickness of, for example, 62 angstroms. The method for manufacturing the semiconductor structure provided by the embodiment ensures the quality of the semiconductor structure, and simultaneously, the shape of the spacer 204 is smooth.
In summary, the present invention provides a method for fabricating a semiconductor structure, which utilizes the photoresist mask and anisotropic etching characteristics to etch a portion of the insulating layer on the top of the electrode, so as to block the sidewall and the bottom, and then etch the insulating layer again after removing the photoresist in the chamber by oxygen plasma etching, so as to form the spacer, thereby solving the problem of non-uniform thickness of the film on the top and other portions of the gate and maintaining the shape of the spacer. The number of layers of the insulating layer is not limited, and when the insulating layer of the electrode side wall and the bottom is required to be protected from being etched, the insulating layer of the electrode side wall and the bottom can be shielded by adopting the light resistor to protect the electrode side wall and the bottom.
The embodiments of the invention disclosed above are intended merely to aid in the explanation of the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims (8)

1. A method of fabricating a semiconductor structure, comprising the steps of:
providing a substrate;
forming an electrode on the substrate;
forming an insulating layer on the electrode, wherein the insulating layer covers the top and the side wall of the electrode and the substrate;
forming a light resistance layer on the insulating layer, wherein a gap is formed between every two adjacent electrodes, the light resistance layer covers the insulating layer and the gap, and the light resistance layer is higher than the insulating layer;
etching the photoresist layer to the top of the insulating layer;
etching the insulating layer on top of the electrode to a thickness equal to the thickness of the insulating layer on the substrate; and
removing the photoresist layer and etching the insulating layer to form a gap wall;
wherein etching the insulating layer atop the electrode comprises: and etching back the insulating layer on the top of the electrode under the protection of the photoresist layer.
2. The method according to claim 1, wherein the insulating layer comprises a first insulating layer covering the top and sidewalls of the electrode and the substrate, and wherein the first insulating layer is made of silicon dioxide.
3. The method of claim 2, wherein the insulating layer comprises a second insulating layer covering the first insulating layer, and the second insulating layer is made of silicon nitride.
4. The method of claim 3, wherein the insulating layer comprises a third insulating layer covering the second insulating layer, and wherein the third insulating layer is made of silicon dioxide.
5. The method as claimed in claim 3, wherein the first insulating layer has a thickness of 7.5-20 nm, and the second insulating layer has a thickness of 15-25 nm.
6. The method of claim 1, wherein etching the photoresist layer to the top of the insulating layer comprises: and etching the photoresist layer by adopting a dry etching method to ensure that the photoresist layer is equal to the insulating layer on the top of the electrode in height.
7. The method of claim 4, wherein the first insulating layer is 50-70 angstroms thick on the substrate after the spacers are formed.
8. The method of claim 4, wherein the spacer comprises a first insulating layer, a second insulating layer, and a third insulating layer formed on the sidewall of the electrode.
CN202110816834.XA 2021-07-20 2021-07-20 Method for manufacturing semiconductor structure Active CN113284807B (en)

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US20150325445A1 (en) * 2014-05-06 2015-11-12 Globalfoundries Inc. Reduced silicon gouging during oxide spacer formation
CN106683990B (en) * 2015-11-06 2021-03-30 联华电子股份有限公司 Semiconductor element and manufacturing method thereof
US9887130B2 (en) * 2016-01-29 2018-02-06 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET device and method of forming the same
CN110444469B (en) * 2019-08-27 2021-08-13 北京智芯微电子科技有限公司 Method for relieving damage to lower layer part caused by etching of top layer of chip

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