KR20090020210A - Method of forming a gate structure in a semiconductor device - Google Patents

Method of forming a gate structure in a semiconductor device Download PDF

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Publication number
KR20090020210A
KR20090020210A KR1020070084767A KR20070084767A KR20090020210A KR 20090020210 A KR20090020210 A KR 20090020210A KR 1020070084767 A KR1020070084767 A KR 1020070084767A KR 20070084767 A KR20070084767 A KR 20070084767A KR 20090020210 A KR20090020210 A KR 20090020210A
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South Korea
Prior art keywords
tungsten silicide
film
gate
oxide film
pattern
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KR1020070084767A
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Korean (ko)
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배형빈
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삼성전자주식회사
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Priority to KR1020070084767A priority Critical patent/KR20090020210A/en
Publication of KR20090020210A publication Critical patent/KR20090020210A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate

Abstract

A method for manufacturing a gate structure of a semiconductor device is provided to adequately increase the electrical isolation between the contact and the gate structure by forming the thick oxide film pattern on the shoulder part of the gate structure. A doped poly silicon layer is formed on a substrate(100). The tungsten silicide film is formed on the doped poly silicon layer. The oxide film is formed on the top of the tungsten silicide film. A gate mask(150) is formed on the oxide film. A doped poly silicon film pattern(112), a tungsten silicide film pattern(122) , a tungsten silicide oxide film pattern(162), and an oxide film pattern(133) are formed through the etching process by using the gate mask as the etching mask. The oxide film is changed to the oxide film pattern while forming the tungsten silicide oxide film.

Description

Method of forming a gate structure in a semiconductor device

The present invention relates to a method of forming a gate structure of a semiconductor device. More specifically, the present invention relates to a method for forming a gate structure of a semiconductor device capable of improving the electrical insulation between the gate structure and the contact including a conductive film pattern.

In general, when fabricating highly integrated semiconductor devices such as DRAM and SRAM, as the design rules become smaller and smaller, contact between the gate structures and the conductive film pattern of the gate structures may cause short circuiting of the semiconductor devices. The likelihood of defects is increasing. Specifically, as the design rule becomes smaller, it is difficult to form a spacer thick enough to form on the sidewalls of the gate structures to minimize the defect because the gap between the patterns is narrowed. Therefore, securing a gate shoulder margin that forms a space for preventing a short circuit between the contact region and the conductive film pattern of the gate structure has become a very important issue. In this case, the gate shoulder is a corner portion of the upper portion of the gate structure, and represents the thinnest portion of the gate spacer located on both side walls of the gate structure.

In order to secure the gate shoulder margin in the related art, a portion of the upper portion of the gate structure is removed by wet etching, thereby reducing the possibility of an electrical short circuit by securing a gap between the exposed conductive layer pattern portion and the contact region of the gate structure. . For example, when the tungsten silicide layer pattern is used as the conductive layer pattern, a wet etching process using an etchant is applied to remove the exposed side surface of the tungsten silicide layer pattern.

However, it is difficult to selectively remove only a part of the upper portion of the gate structure due to difficulty in controlling the amount of the etchant through the above-described wet etching process. Specifically, the side portion of the tungsten silicide layer pattern is less removed and still have a bulging shape, or overetching and / or shoulder weakening of the gate shoulder due to excessive etching may occur. In particular, it is more difficult to precisely remove only a portion of the upper portion of the gate as the design rule of the semiconductor device is further reduced.

An object of the present invention for solving the above problems is to form a gate structure of a semiconductor device that can improve the gate shoulder portion to increase the electrical insulating properties between the gate structure including the tungsten silicide layer pattern and the adjacent contact To provide a method.

A method of forming a gate structure of a semiconductor device according to an embodiment of the present invention for achieving the above object is to form a doped polysilicon film on a substrate. A tungsten silicide film is formed on the doped polysilicon film. An oxide film is formed on the tungsten silicide film. A gate mask is formed on the oxide film. A portion of the oxide film and the tungsten silicide film exposed by the gate mask are oxidized to form a tungsten silicide oxide film. An etching process is performed using the gate mask as an etching mask to form a doped polysilicon layer pattern, a tungsten silicide layer pattern, a tungsten silicide oxide layer pattern, and an oxide layer pattern on the substrate.

At this time, the oxide film is changed into the oxide film pattern while the tungsten silicide oxide film is formed.

As an example of the present invention, the tungsten silicide oxide layer pattern has a thickness thicker than that of the oxide layer pattern. Here, the tungsten silicide oxide film may be formed using a thermal oxidation process, and may be formed under an atmosphere including oxygen and a temperature of 1,000 ° C. to 1,500 ° C.

In addition, a gate spacer may be further formed on sidewalls of the gate structure.

A method of forming a gate structure of a semiconductor device according to another embodiment of the present invention for achieving the above object is to form a doped polysilicon film on a substrate. A tungsten silicide film is formed on the doped polysilicon film. An oxide film is formed on the tungsten silicide film. A gate mask is formed on the oxide film. A portion of the oxide film and the tungsten silicide film exposed by the gate mask are etched to form an oxide film pattern. An etching process is performed using the gate mask as an etching mask to form a preliminary gate structure including a doped polysilicon pattern, a tungsten silicide layer pattern, the oxide layer pattern, and the gate mask on the substrate. A sidewall oxide film is formed on sidewalls of the preliminary gate structure.

As an example, the oxide layer and the tungsten silicide layer may be etched using a wet etching process. In this case, the wet etching process is performed using an etching solution including a hydrofluoric acid (HF) solution and an SC1 solution.

In addition, the sidewall oxide film may be formed using a thermal oxidation process, and the sidewall oxide film may be formed under an atmosphere including oxygen and a temperature of 1,000 ° C to 1,500 ° C.

According to the present invention, an oxide film is formed before the gate mask is formed and a thermal oxidation process is subsequently performed to form a thick oxide pattern on the shoulder portion of the gate structure, thereby forming a contact between the gate structure and the gate structure having the tungsten silicide film pattern. It is possible to increase the electrical insulation sufficiently. Therefore, the problem of a breakdown voltage between the contact and the word line formed of the gate structures is lowered.

According to the gate structure forming method of the semiconductor device of the present invention as described above, a polysilicon film, a tungsten silicide film and an oxide film are sequentially formed on a substrate. Subsequently, a gate mask is formed on the oxide layer, and a portion exposed by the gate mask is thermally oxidized to form a tungsten silicide oxide layer on an edge portion of the lower portion of the gate mask. Subsequently, the gate structure is patterned to form a polysilicon film pattern, a tungsten silicide film pattern, a thermal oxide, and an oxide film pattern having a thick edge portion and a gate mask pattern on the substrate.

According to the present invention, an oxide film is formed before the gate mask is formed and a thermal oxidation process is subsequently performed to form a thick oxide pattern on the shoulder portion of the gate structure, thereby electrically insulating the gate structure having the tungsten silicide layer pattern and the adjacent contact. Can be increased sufficiently.

In addition, an oxide film is formed before the gate mask is formed, a portion of the oxide film and the tungsten silicide film exposed to the gate mask are removed, and then a portion of the gate structure is thermally oxidized to form a silicon oxide film to form an electrical layer between the tungsten silicide film pattern and the contact. Solve the gate shoulder margin for insulation. Therefore, the problem of a breakdown voltage between the contact and the word line formed of the gate structures is lowered.

Hereinafter, embodiments of the method for forming a gate structure of a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited to the following embodiments, and has a general knowledge in the art. It will be apparent to those skilled in the art that the present invention may be embodied in various other forms without departing from the spirit of the invention. In the accompanying drawings, the dimensions of the substrate, film (layer), region, pattern or structure are shown to be larger than actual for clarity of the invention. In the present invention, a film (layer), region, pattern, or structure may be used as "on", "on", "on", "on" or "under" a substrate, film, region, pad or pattern, When referred to as "below", "below", it means that each film (layer), region, pattern or structure is formed directly over or below the substrate, film (layer), region or pattern, Other films (layers), other regions, other patterns or other structures may additionally be formed on the substrate. In addition, where a film (layer), region, pattern or structure is referred to as "first" and / or "second", it is not intended to limit these members, but only thickness, film (layer), region, pattern or structure To distinguish between them. Thus, "first" and / or "second" may be used selectively or interchangeably with respect to a film (layer), region, pattern or structure, respectively.

1 to 8 are cross-sectional views illustrating a method of forming a gate structure of a semiconductor device in accordance with embodiments of the present invention.

Referring to FIG. 1, a device isolation process is performed on a semiconductor substrate 100 to define an active region (not shown) and a device isolation region (not shown).

A gate insulating film (not shown) is formed on the substrate 100. The gate insulating film may be obtained by performing a thermal oxidation process on the substrate 100. Alternatively, the gate insulating layer may be formed by depositing a material having a high dielectric constant on the substrate 100 by a chemical vapor deposition process.

After the polysilicon layer is formed on the substrate 100 on which the gate insulating layer is formed, the polysilicon layer is doped with N-type impurities or P-type impurities. As a result, a polysilicon layer 110 doped with impurities is formed on the substrate 100 on which the gate insulating layer is formed. According to another embodiment of the present invention, the polysilicon film 110 doped with impurities on the gate insulating film is doped by doping N-type or P-type impurities in-situ during the deposition of polysilicon on the gate insulating film. It may be formed. For example, the P-type impurity may include indium (In), gallium (Ga), or boron (B), and the N-type impurity may include phosphorus (P) or arsenic (As).

Referring to FIG. 2, a tungsten silicide layer 120 may be formed on the doped polysilicon layer 110, which may function as an ohmic layer to reduce the resistance of the gate structure. The content ratio of silicon to tungsten in the tungsten silicide layer 120 may be about 1: 5 to about 1:15. For example, the silicon content ratio of tungsten in the tungsten silicide layer 120 may be about 1: 7 to about 1:10. The tungsten silicide layer 120 may be formed on the doped polysilicon layer 110 using a chemical vapor deposition process or a physical vapor deposition process.

When the tungsten silicide layer 120 is formed using a chemical vapor deposition process, the first source gas, which is a tungsten source gas, may include tungsten hexafluoride (WF 6 ), and the second source gas, which is a silicon source gas, may be dichlorochloride. Silane (SiH 2 Cl 2 ) and / or monosilane (SiH 4 ). According to the reaction of the first and second source gases, a tungsten silicide layer 120 may be formed on the doped polysilicon layer 110. In this case, in order to form the tungsten silicide film 120 having a content ratio between tungsten and silicon of about 1: 5 to about 1:15, the partial pressure of the first source gas is sufficiently higher than that of the second source gas. Should be low. In addition, a carrier gas for carrying the first and second source gases into the reaction chamber may include an inert gas. For example, the carrier gas may include argon gas. During the chemical vapor deposition process, the pressure in the reaction chamber may be maintained at about 0.5 Torr to about 5.0 Torr. For example, the pressure in the reaction chamber can be maintained at about 0.5 Torr s to 1.5 Torr.

Meanwhile, when the tungsten silicide layer 120 is formed using the physical vapor deposition process, the polysilicon layer 110 doped using a target having a content ratio of tungsten and silicon of about 1: 5 to about 1:15 is used. A tungsten silicide film can be formed on it.

Referring to FIG. 3, an oxide film 130 is formed on the tungsten silicide film 120. The oxide layer 130 is formed between the tungsten silicide layer 120 and the gate mask 140 (see FIG. 4), and a patterning process for forming a subsequent gate structure is performed, and then the exposed portions are removed by a wet etching process. Or thermally oxidized. For example, the oxide film 130 may be formed by depositing silicon oxide (SiO 2 ) by a low pressure chemical vapor deposition (LPCVD).

Referring to FIG. 4, a gate mask layer 140 is formed on the oxide layer 130. The gate mask layer 140 is formed of a nitride such as silicon nitride.

Referring to FIG. 5, the gate mask layer 140 is patterned to form the gate mask 150 on the oxide layer 130. According to an embodiment of the present invention, a first photoresist film (not shown) is coated on the gate mask layer 140, and then the first photoresist film is exposed and developed to expose a first photoresist pattern (not shown). Not formed). Subsequently, the gate mask layer 140 may be partially etched using the first photoresist pattern as an etching mask to form a gate mask 150 partially exposing the oxide layer 130.

Referring to FIG. 6, both sides of the oxide film 130 exposed by the gate mask 150 and the tungsten silicide film 120 below are oxidized to form a tungsten silicide oxide film 160 on the tungsten silicide film 120. Form. In this case, the oxide film 130 under the gate mask 150 is changed into the oxide film pattern 133. The tungsten silicide oxide layer 160 may be formed using a thermal oxidation process. For example, the tungsten silicide oxide layer 160 may be formed under an atmosphere containing oxygen while maintaining the temperature of the reaction chamber at about 1,000 ° C to about 1,500 ° C.

According to embodiments of the present invention, both sides of the oxide film 130, that is, the portion adjacent to the gate mask 150, are changed to the tungsten silicide oxide film 160 having a thick thickness. Accordingly, the tungsten silicide oxide film 160 is connected to the oxide film pattern 133 while having a thickness thicker than that of the oxide film pattern 133. For example, the tungsten silicide oxide layer 160 may be formed on both sides of the oxide layer pattern 133, such as a bird's beak. Therefore, the thickness between the tungsten silicide layer pattern 122 (see FIG. 7) and the gate mask 150 formed during the etching process using the gate mask 150 (see FIG. 7) is thicker than that of the oxide layer pattern 133. A tungsten silicide oxide film 160 can be formed to ensure sufficient insulating properties. As a result, it is possible to sufficiently secure the level of insulation characteristics required between the gate structures subsequently formed by the tungsten silicide oxide film 160, the contacts therebetween (not shown), and the tungsten silicide film pattern 122. . That is, according to the present invention, a problem of securing a shoulder margin for securing an insulation area at the gate shoulder region may be solved by the tungsten silicide oxide layer 160 thicker than the oxide layer pattern 133.

Referring to FIG. 7, the polysilicon layer pattern 112, the tungsten silicide layer pattern 122, and the oxide layer pattern 133 doped on the substrate 100 by performing an etching process using the gate mask 150 as an etching mask. ), A tungsten silicide oxide layer pattern 162 and a gate mask 150 are formed. In this case, the tungsten silicide oxide layer pattern 162 thicker than the oxide layer pattern 133 may be formed by patterning the tungsten silicide oxide layer 160. In the above-described gate structure 170, a tungsten silicide oxide layer pattern 162, which is an insulating layer pattern having a larger area than that of the oxide layer pattern 133 under the gate mask 150, is provided. Accordingly, a sufficient insulation area may be secured at the shoulder portion of the gate structure 170.

Referring to FIG. 8, after forming a nitride film (not shown) using silicon nitride on the semiconductor substrate 100 on which the gate structures 170 are formed, the nitride film is anisotropically etched to form side surfaces of the gate structures 170. Gate spacers 180 are formed on the substrates. As a result, a plurality of word lines (not shown) are formed on the semiconductor substrate 100 in parallel with each other. In this case, the word lines formed in the active region of the semiconductor substrate 200 are electrically separated from the adjacent word lines by the gate spacers 180 formed on the sidewalls thereof. In other words, the gate mask 150 made of an insulator, the oxide pattern 133, the tungsten silicide oxide pattern 162, and the gate spacer 180 are formed on upper and side surfaces of each word line, so that adjacent word lines are electrically connected to each other. Insulated by. Therefore, even when the gate spacer 180 is partially thin, a defect such as a short between the tungsten silicide layer pattern 122 of the gate structure 170 and a subsequent contact or plug formed between the gate structures 170 may not occur. Do not. In addition, the problem that the breakdown voltage between the contact or plug and the word line is lowered can be prevented.

Using the word lines as an ion implantation mask, an impurity is implanted into the semiconductor substrate 100 exposed between the word lines by an ion implantation process, and then a heat treatment process is performed to thereby source the semiconductor substrate 100. Form / drain regions (not shown). Accordingly, a MOS transistor including a source / drain region and a gate structure 170 is formed on the semiconductor substrate 100.

9 through 12 are cross-sectional views illustrating a method of forming a gate structure of a semiconductor device in accordance with some example embodiments of the present inventive concepts. The gate structure forming method described with reference to FIGS. 9 to 12 is substantially the same as the method of forming the gate structure described with reference to FIGS. 1 to 8 except for forming the gate structure by a thermal oxidation process and a dry etching process. similar. Therefore, repeated descriptions are omitted, and the same reference numerals are used in FIGS. 9 to 12 for components substantially the same as those described in FIGS. 1 to 8.

Referring to FIG. 9, a doped polysilicon layer 110, a tungsten silicide layer 210, an oxide layer (not shown), and a gate mask 150 are sequentially formed on the semiconductor substrate 100.

Both sides of the oxide film exposed by the gate mask 150 and a portion of the tungsten silicide film 210 below are etched through an etching process to form an oxide pattern 220 under the gate mask 150. The oxide layer pattern 220 may be formed using a wet etching process, and the tungsten silicide layer 210 around the oxide layer pattern 220 may be partially etched during the wet etching process. For example, the oxide layer pattern 220 may be formed using an etching solution including a hydrofluoric acid (HF) solution and a standard clean 1 (SC1) solution. Here, the volume ratio between hydrofluoric acid and pure water in the hydrofluoric acid (HF) solution may be about 100: 1 to about 400: 1, and the SC1 solution may include ammonium hydroxide, hydrogen peroxide and pure water.

By the above-described wet etching process, both side portions of the oxide film exposed by the gate mask 150 and a part of the tungsten silicide film 210 are removed. In this case, the oxide mask and the tungsten silicide layer 120 near the gate mask 150 and the lower edge portion are partially removed by the etching solution. Accordingly, a tungsten silicide layer 210 and an oxide layer pattern 220 having an upper portion partially removed between the doped polysilicon layer 110 and the gate mask 150 are formed.

Referring to FIG. 10, a polysilicon layer pattern 112 doped on a substrate 100 by performing an etching process using the gate mask 150 as an etching mask, and a tungsten silicide layer pattern 212 having an upper peripheral portion removed thereon ), A preliminary gate structure 230 including an oxide layer pattern 220 and a gate mask 150 is formed.

Referring to FIG. 11, the gate structure 240 is formed on the substrate 100 by forming the sidewall oxide layer 250 on the side surface of the preliminary gate structure 230. The sidewall oxide layer 250 may include silicon oxide and may be formed through a thermal oxidation process. As the sidewall oxide layer 250 is formed, the gate structure 240 having a substantially vertical sidewall is formed. For example, the sidewall oxide film 250 is formed under an oxygen atmosphere in a reaction chamber having a temperature of about 1,000 ° C to about 1,500 ° C.

The sidewall oxide layer 250 is formed to cover the tungsten silicide layer pattern 212 and the oxide layer pattern 222 having the upper peripheral portion partially removed from the side surface of the preliminary gate structure 230. In particular, the sidewall oxide film 250 has the thickest thickness on the sidewalls of the tungsten silicide film pattern 212 and the oxide film pattern 220. As such, the level of insulation properties required between the tungsten silicide layer pattern 212 and the contact or plug (not shown) formed subsequently between the gate structures 240 due to the partially thickened sidewall oxide layer 250. Can be provided effectively. As a result, the gate shoulder margin problem may be solved by securing a sufficient insulating area in the side portion of the gate structure 240 including the sidewall oxide layer 250.

Referring to FIG. 12, after forming a nitride film (not shown) on the substrate 100 while covering the gate structures 240, the nitride films are anisotropically etched to form gate spacers 180 on the side surfaces of the gate structures 240. ). Accordingly, a plurality of word lines (not shown) are formed on the substrate 100 to be parallel to each other.

 Word lines formed in the active region of the substrate 100 are electrically separated from each other by adjacent word lines by gate spacers 180 formed on sidewalls of the substrate 100. That is, since the top and side surfaces of each word line are formed of the gate mask 150, the oxide layer pattern 222, the sidewall oxide layer 250, and the gate spacer 180 formed of an insulating material, adjacent word lines are electrically connected to each other. Insulated. Accordingly, even when the gate spacer 180 is partially thinned on the sidewall of the gate structure 240, a short between the tungsten silicide layer pattern 212 of the gate structure 240 and a subsequent contact or plug is formed. Can be prevented. In addition, the problem that the breakdown voltage between the contact or plug and the word line is reduced can be prevented.

Source / drain regions (not shown) are formed on the substrate 100 by implanting impurities into predetermined portions of the substrate 100 between the word lines using the word lines as an ion implantation mask, and then performing a heat treatment process. To form. As a result, a MOS transistor is formed on the substrate 100 including the source / drain regions and the gate structure 240.

According to the present invention, an oxide film is formed between a tungsten silicide film and a nitride mask, and thermal oxidation of an exposed portion of the oxide film or wet etching of a side surface of the gate structure is followed by thermal oxidation, thereby sufficiently securing an insulating area of the gate structure. The electrical short circuit between the tungsten silicide pattern of the gate structure and an adjacent contact or plug may be prevented.

Although the above has been described with reference to the embodiments of the present invention, those skilled in the art may vary the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. It will be understood that modifications and changes can be made.

1 to 8 are cross-sectional views illustrating a method of forming a gate structure of a semiconductor device in accordance with embodiments of the present invention.

9 through 12 are cross-sectional views illustrating a method of forming a gate structure of a semiconductor device in accordance with some example embodiments of the present inventive concepts.

<Description of the symbols for the main parts of the drawings>

100 substrate 110 doped polysilicon film

112 doped polysilicon film pattern 120 tungsten silicide film

122, 212: tungsten silicide film pattern

130: oxide film 133, 220: oxide film pattern

140: gate mask film 150: gate mask

160, 210: tungsten silicide oxide film

170, 240: gate structure 180: gate spacer

230: preliminary gate structure 250: sidewall oxide film

Claims (11)

Forming a doped polysilicon film on the substrate; Forming a tungsten silicide film on the doped polysilicon film; Forming an oxide film on the tungsten silicide film; Forming a gate mask on the oxide film; Oxidizing a portion of the oxide film and the tungsten silicide film exposed by the gate mask to form a tungsten silicide oxide film; And Forming a doped polysilicon layer pattern, a tungsten silicide layer pattern, a tungsten silicide oxide layer pattern, and an oxide layer pattern on the substrate by performing an etching process using the gate mask as an etching mask; Way. The method of claim 1, wherein the oxide film is changed into the oxide film pattern while the tungsten silicide oxide film is formed. The method of claim 1, wherein the tungsten silicide oxide layer pattern has a thickness thicker than that of the oxide layer pattern. The method of claim 1, wherein the tungsten silicide oxide layer is formed using a thermal oxidation process. The method of claim 4, wherein the tungsten silicide oxide layer is formed under an atmosphere including oxygen and a temperature of 1,000 ° C. to 1,500 ° C. 6. The method of claim 1, further comprising forming a gate spacer on sidewalls of the gate structure. Forming a doped polysilicon film on the substrate; Forming a tungsten silicide film on the doped polysilicon film; Forming an oxide film on the tungsten silicide film; Forming a gate mask on the oxide film; Etching a portion of the oxide film and the tungsten silicide film exposed by the gate mask to form an oxide film pattern; Performing an etching process using the gate mask as an etching mask to form a preliminary gate structure including a doped polysilicon pattern, a tungsten silicide layer pattern, the oxide pattern, and the gate mask on the substrate; And Forming a sidewall oxide film on sidewalls of the preliminary gate structure. The method of claim 7, wherein the oxide layer and the tungsten silicide layer are etched using a wet etching process. The method of claim 8, wherein the wet etching process is performed using an etching solution including a hydrofluoric acid (HF) solution and an SC1 solution. 8. The method of claim 7, wherein the sidewall oxide film is formed using a thermal oxidation process. The method of claim 7, wherein the sidewall oxide layer is formed under an atmosphere including oxygen and a temperature of 1,000 ° C. to 1,500 ° C. 9.
KR1020070084767A 2007-08-23 2007-08-23 Method of forming a gate structure in a semiconductor device KR20090020210A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200001624A (en) * 2017-05-31 2020-01-06 어플라이드 머티어리얼스, 인코포레이티드 Methods for Wordline Separation in 3D-NAND Devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200001624A (en) * 2017-05-31 2020-01-06 어플라이드 머티어리얼스, 인코포레이티드 Methods for Wordline Separation in 3D-NAND Devices

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