KR101010106B1 - Method for manufacturing semiconductor device - Google Patents

Abstract

The present invention relates to a method of fabricating a semiconductor device, and after oxidizing and removing the nitride film at the bottom of the landing plug contact hole, selectively etching only the active region to minimize the loss of the device isolation layer to expose the lower gate polysilicon layer. And a technique capable of preventing SAC defects in which the gate and the landing plug are electrically shorted accordingly.

Pin Mask, Landing Plug

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a landing plug of a semiconductor device.

In general, a transistor having a horizontal channel widely applied to a transistor has various limitations as the design rule is reduced, thereby limiting the size of the transistor. The biggest problems of the reduced horizontal channel transistors include short channel effects and drain induced barrier lower (DIBL) effects caused by shorter channel lengths.

In order to overcome the problems of horizontal channel transistors, double gate transistors have been proposed. The double gate transistor has a channel having a thickness of 30 nm or less, and a structure surrounding the channel or having gates disposed on both sides of the channel. In the horizontal channel transistor, since the gate electrode is formed only on the upper portion of the horizontal channel, an electric field is applied asymmetrically to the channel, and thus there are many difficulties in effectively controlling the on / off operation of the transistor by the gate electrode. As a result, the smaller the channel size, the greater the influence of the short channel effect.

In contrast, in the double gate transistor having the vertical channel, since gate electrodes are formed on both sides of the thin channel, all regions of the channel are affected by the gate electrode. Therefore, since the charge flow between the source and the drain can be suppressed when the transistor is off, power consumption can be reduced, and the on / off operation of the transistor can be effectively controlled. Transistors having such vertical channels include fin transistors, recess transistors, and saddle fin transistors in which fin transistors and recess transistors are mixed.

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1A, an isolation layer 14 defining an active region 12 is formed in a semiconductor substrate 10. Next, the active region 12 and the device isolation layer 14 are etched to form a recess 16 by a photolithography process using a fin mask, and the etching process is performed to remove the etch residues. At this time, a bowing profile is formed in the middle portion of the recess 16 formed on the device isolation layer 14 by the cleaning process.

Referring to FIG. 1B, a gate oxide film (not shown) is formed on the entire surface of the semiconductor substrate 10 including the recess 16. Next, a gate polysilicon layer 18a, a barrier metal layer (not shown), a gate electrode layer 18b, and a gate hard mask layer 18c are formed on the gate oxide layer.

Here, the barrier metal layer is formed of a laminated structure of a titanium (Ti) film and a titanium nitride (TiN) film, the gate electrode layer 18b is formed of a tungsten (W) layer, and the gate hard mask layer 18c is formed of a nitride film. do.

Next, the gate 18 is formed by etching the gate hard mask layer 18c, the gate electrode layer 18b, the barrier metal layer, and the gate polysilicon layer 18a by a photolithography process using a gate mask (not shown). .

Next, a gate spacer film 20 is formed on the surface of the semiconductor substrate 10 including the gate 18. Here, the gate spacer film 20 is formed of a nitride film. Next, an interlayer insulating film 22 is formed on the gate spacer film 20 to fill the gap between the gates 18. Here, the interlayer insulating film 22 is formed of an oxide film.

Referring to FIG. 1C, the interlayer insulating layer 22 is etched by a photolithography process using a landing plug contact mask (not shown) to form a landing plug contact hole (not shown). Next, a landing plug contact spacer film 24 is formed on the landing plug contact hole and the gate spacer film 20, and a buffer oxide film (not shown) is formed on the landing plug contact spacer film 24. .

Here, the landing plug contact spacer 24 is formed of a nitride film, and the buffer oxide film is formed of a USG (Undoped Silicate Glass) film. At this time, the buffer oxide film is thickly deposited on the gate 18, and is thinly deposited between the narrow gates 18.

Referring to FIG. 1D, the landing plug contact spacer 24 and the gate spacer layer 20 between the gates 18 are etched using the buffer oxide layer as an etching mask. Here, the etching process of the landing plug contact spacer layer 24 and the gate spacer layer 20 is performed by an etch-back method and uses a florin series as a reaction gas. In this case, the semiconductor substrate 10 may be partially lost to prevent the landing plug contact hole from being opened during the etch back process. However, since the isolation rate of the device isolation layer 14 is faster than that of the active region 12, the loss of the device isolation layer 14 is greater. In this case, since a bowing profile is formed in the gate polysilicon layer 18a formed on the isolation layer 14, the gate polysilicon layer 18a is exposed by the loss of the isolation layer 14. In this case, there is a problem in that the landing plug to be formed in a subsequent process and the SAC failure that the gate 18 is electrically short (short) is caused.

2 is a photograph showing a problem of a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 2, a recess is formed in the device isolation layer 14 during the photolithography process using the fin mask. However, as shown in (a) during the cleaning process for removing the etch residue, it can be seen that a bowing profile A is formed in the middle portion of the recess formed on the device isolation layer 14. . In this state, when a subsequent buffer oxide etch back (BOEB) process is performed, the gate polysilicon layer 18a on the device isolation layer 14 is exposed. This causes a SAC failure in which the landing plug 28 and the gate 18 are electrically shorted (B), as shown in (b) and (c). In order to solve this problem, if the line width of the recess formed on the device isolation layer 14 is reduced, the line width of the gate is not secured and the characteristics of the transistor are deteriorated. If the cleaning process is not performed, the interface characteristics are deteriorated. have.

The present invention has the following object.

First, the nitride film of the bottom of the landing plug contact hole is oxidized and removed, and then only the active region is selectively etched to minimize the loss of the device isolation layer to prevent the lower gate polysilicon layer from being exposed, and thus the gate and the landing plug. The purpose of this is to prevent the SAC failure that is electrically shorted.

Second, since the formation, cleaning, and etching processes of the buffer oxide layer can be omitted, the purpose of the present invention is to shorten the turn around time (TAT).

A method of manufacturing a semiconductor device according to the present invention includes forming a device isolation film defining an active region on a semiconductor substrate; Etching the active region and the device isolation layer to form a recess; Forming a gate on the recess; Forming an insulating film filling the gate; Etching the insulating layer to form a landing plug contact hole; Forming a landing plug spacer layer on a surface of the landing plug contact hole; Forming an oxide layer by oxidizing the landing plug spacer layer on the gate and the bottom of the landing plug contact hole; And removing the oxide film.

The recess forming process may further include performing a process using a fin mask, performing a cleaning process for removing etch residue after the recess forming step, and performing the gate after the gate forming step. And forming a gate spacer film on the surface of the semiconductor substrate, wherein the gate spacer film is formed to have a thickness of about 30 to 60 microns (N ₃ ) of the nitride film (Si ₃ N ₄ ), and the spacer film for landing plug is a nitride film ( Si ₃ N ₄ ) to form a thickness of 20 ~ 40 20.

The oxide film forming step may be performed by a plasma process using oxygen radicals, and the oxide film forming step may be performed by mixing SiH ₄ , H ₂ , O _2, and He under a pressure of 0.3˜1.0 torr and a temperature of 400˜600 ° C. It is carried out using a gas, the thickness of the oxide film is 50 ~ 100Å, the oxide film removing process is carried out by a wet cleaning method, the oxide film removing process is DI water and HF 25 ~ 30: 1 It is characterized in that it is carried out for 5 to 10 seconds with a solution mixed in the ratio of.

The method may further include etching the exposed semiconductor substrate, and the etching process of the exposed semiconductor substrate may be performed for 5 to 10 seconds using 100 to 120 sccm of HBr gas and 3 to 5 sccm of O2 gas. It features.

The present invention provides the following effects.

First, the nitride film of the bottom of the landing plug contact hole is oxidized and removed, and then only the active region is selectively etched to minimize the loss of the device isolation layer to prevent the lower gate polysilicon layer from being exposed, and thus the gate and the landing plug. It provides an effect to prevent the SAC failure that is electrically shorted.

Second, the formation, cleaning, and etching processes of the buffer oxide layer may be omitted, thereby providing an effect of shortening the turn around time (TAT).

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Referring to FIG. 3A, an isolation layer 104 defining an active region 102 is formed in the semiconductor substrate 100. Next, the active region 102 and the device isolation layer 104 are etched to form a recess 106 by a photolithography process using a fin mask, and the etch residue is removed by performing a cleaning process. At this time, a bowing profile is formed in the middle portion of the recess 106 formed on the device isolation film 104 by the cleaning process.

Referring to FIG. 3B, a gate oxide film (not shown) is formed on the entire surface of the semiconductor substrate 100 including the recess 106. A gate polysilicon layer 108a, a barrier metal layer (not shown), a gate electrode layer 108b, and a gate hard mask layer 108c are formed on the gate oxide layer.

Here, the barrier metal layer is formed of a laminated structure of a titanium (Ti) film and a titanium nitride (TiN) film, the gate electrode layer 108b is formed of a tungsten (W) layer, and the gate hard mask layer 108c is formed of a nitride film. It is desirable to.

Next, the gate 108 is formed by etching the gate hard mask layer 108c, the gate electrode layer 108b, the barrier metal layer, and the gate polysilicon layer 108a by a photolithography process using a gate mask (not shown). .

Next, a gate spacer layer 110 is formed on the surface of the semiconductor substrate 100 including the gate 108. Here, the gate spacer film 110 forms a nitride film (Si ₃ N ₄ ) to a thickness of 30 ~ 60Å. Next, an interlayer insulating film 112 is formed on the gate spacer film 110 to fill the gap between the gates 108. Here, the interlayer insulating film 112 is preferably formed of an oxide film.

Referring to FIG. 3C, the interlayer insulating layer 112 is etched by a photolithography process using a landing plug contact mask (not shown) to form a landing plug contact hole (not shown). Next, the landing plug contact spacer layer 114 is formed on the surface of the landing plug contact hole and the gate spacer layer 110. Here, the landing plug contact spacer film 114 forms a nitride film (Si ₃ N ₄ ) to a thickness of 20 to 40 kPa.

Referring to FIG. 3D, an oxide film (SiO ₂ ) 116 is formed by oxidizing the gate spacer film 110 and the landing plug contact spacer film 114 by performing a plasma process using oxygen radicals. At this time, oxidation of the gate spacer film 110 and the landing plug contact spacer film 114 on the plane perpendicular to the injection direction of the plasma gas 115, that is, the upper portion of the gate 108 and the bottom of the landing plug contact hole is caused by the plasma gas. Is faster than the plane parallel to the injection direction, i.e., the gate 108 sidewall. Therefore, an oxide film (SiO ₂ ) 116 is formed only on the gate 108 and the bottom of the landing plug contact hole. Here, the plasma process is preferably performed using a mixed gas of SiH ₄ , H ₂ , O ₂ and He under a pressure of 0.3 ~ 1.0torr and a temperature of 400 ~ 600 ℃. Here, the reaction between the mixed gas, that is, the reaction between the gate spacer film 110 and the landing plug contact film 114, i.e., Si ₃ N ₄ and O ₂ , is more preferable than the reaction between SiH ₄ and O ₂ . ₃ N ₄ can be oxidized to SiO ₂ . At this time, it is preferable that the thickness of the oxide film 116 is 50-100 kPa.

Referring to FIG. 3E, the oxide film 116 is removed. Here, the removal process of the oxide film 116 is preferably performed by a wet cleaning process. In this case, the wet cleaning process is preferably performed for 5 to 10 seconds with a solution in which pure water (DI water) and HF are mixed at a ratio of 25 to 30: 1.

Referring to FIG. 3F, the semiconductor substrate 100 is partially etched to prevent the landing plug contact hole from being opened. In this case, the etching process of the semiconductor substrate 100 may be performed under conditions in which the etching selectivity to silicon is high. That is, the etching process of the semiconductor substrate 100 is preferably performed for 5 to 10 seconds using HBr gas of 100 ~ 120sccm and O2 gas of 3 ~ 5sccm. As a result, the loss of 100-200 GPa occurs in the active region 102, while the loss of the device isolation film 104 only 10 dB or less occurs. Accordingly, the gate polysilicon layer 108a may be exposed by the loss of the device isolation film 104, thereby preventing the SAC defect.

In addition, the preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and modifications are the following patents It should be regarded as belonging to the claims.

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

Figure 2 is a photograph showing a problem of the manufacturing method of a semiconductor device according to the prior art.

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Claims (13)

Forming an isolation layer defining an active region on the semiconductor substrate; Etching the active region and the device isolation layer to form a recess; Forming a gate on the recess; Forming an insulating film filling the gate; Etching the insulating layer to form a landing plug contact hole; Forming a landing plug spacer layer on a surface of the landing plug contact hole; Forming an oxide film by oxidizing the landing plug spacer layer on the gate and on the bottom of the landing plug contact hole; And Removing the oxide film to expose the semiconductor substrate, And etching the exposed semiconductor substrate after exposing the semiconductor substrate. The method of claim 1, wherein the recess forming process is performed using a fin mask. The method of claim 1, further comprising performing a cleaning process for removing etch residue after the recess forming step. The method of claim 1, further comprising forming a gate spacer film on the gate and the surface of the semiconductor substrate after the gate forming step. The method of manufacturing a semiconductor device according to claim 4, wherein the gate spacer film is formed of a nitride film (Si ₃ N ₄ ) having a thickness of 30 to 60 kPa. The method of manufacturing a semiconductor device according to claim 1, wherein the landing plug spacer film forms a nitride film (Si ₃ N ₄ ) having a thickness of 20 to 40 kPa. The method of claim 1, wherein the forming of the oxide film is performed by a plasma process using oxygen radicals. The semiconductor device of claim 1, wherein the forming of the oxide film is performed using a mixed gas of SiH ₄ , H ₂ , O _2, and He under a pressure of 0.3˜1.0 torr and a temperature of 400˜600 ° C. ₃ . Manufacturing method. The method of manufacturing a semiconductor device according to claim 1, wherein the oxide film has a thickness of 50 to 100 GPa. The method of claim 1, wherein the oxide film removing process is performed by a wet etching method. The method of claim 1, wherein the oxide film removing process is performed for 5 to 10 seconds using a solution in which DI water and HF are mixed at a ratio of 25 to 30: 1. delete The method of claim 1, wherein the etching process of the exposed semiconductor substrate is performed for 5 to 10 seconds using 100 to 120 sccm of HBr gas and 3 to 5 sccm of O 2 gas.

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