CN113272941A - Semiconductor module and method for manufacturing the same - Google Patents
Semiconductor module and method for manufacturing the same Download PDFInfo
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- CN113272941A CN113272941A CN201880100179.4A CN201880100179A CN113272941A CN 113272941 A CN113272941 A CN 113272941A CN 201880100179 A CN201880100179 A CN 201880100179A CN 113272941 A CN113272941 A CN 113272941A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Abstract
The invention provides a semiconductor module capable of suppressing damage to an electrode and a method for manufacturing the same. The method for manufacturing a semiconductor module of the present invention includes: a step of forming an electrode layer (23) at positions having different distances from an opposite surface (222) of the surfaces of the wiring layer (22) for each of the plurality of circuit modules (20), the opposite surface (222) being opposite to an opposite surface (221) that faces the substrate 21; a step of stacking circuit modules (20) in the order of increasing distance of the electrode layer (23) from the lowermost layer to the uppermost layer; and forming via holes (50) that penetrate the plurality of stacked circuit modules (20) to electrically connect the stacked circuit modules (20).
Description
Technical Field
The invention relates to a semiconductor module and a method of manufacturing the same.
Background
Conventionally, a volatile Memory (RAM) such as a DRAM (Dynamic Random Access Memory) is known as a Memory device. DRAM is required to have a large capacity so as to be able to withstand high performance of an arithmetic device (hereinafter referred to as a logic chip) and an increase in data volume. Therefore, the miniaturization of memories (memory cell arrays and memory chips) and the planar addition of cells have led to a large capacity. On the other hand, such a large capacity has reached a limit due to vulnerability to noise and an increase in a large area due to miniaturization.
Therefore, recently, a technique for increasing the capacity by three-dimensionally converting (3D converting) a memory in which a plurality of planes are stacked has been developed. As a device using such a technique, a method of electrically connecting stacked chips using electrodes penetrating in the thickness direction of a silicon substrate has been proposed (for example, see patent document 1).
Documents of the prior art
Patent document
Patent document 1: japanese patent laid-open publication No. 2016 + 46447.
Disclosure of Invention
Problems to be solved by the invention
However, in the method of patent document 1, the electrodes of the uppermost layer and the intermediate layer are used as a hard mask when forming the through hole. Therefore, the longer the upper electrode is etched. Therefore, the damage is accumulated as the upper electrode is. For example, the thickness of the upper electrode becomes thinner due to damage. In particular, when the number of stacked wafers is increased, the electrodes may disappear due to accumulation of damage.
The invention provides a semiconductor module and a method for manufacturing the same, which can prevent damage to an electrode.
Means for solving the problems
The present invention relates to a method for manufacturing a semiconductor module by stacking a plurality of circuit modules, comprising: a step of manufacturing a plurality of circuit modules having a substrate and a wiring layer adjacent to one surface of the substrate, the step including a step of forming an electrode layer for each of the plurality of circuit modules; a step of stacking a plurality of the circuit modules from the lowermost layer to the uppermost layer, the circuit modules being stacked such that the wiring layers and the substrates are alternately arranged from the lowermost layer to the uppermost layer; a step of forming via holes extending from an uppermost layer to a lowermost layer in a stacking direction of the circuit modules and exposing the electrode layers of the circuit modules, the step including a step of forming guide holes of via holes extending from the uppermost layer to the lowermost layer in the stacking direction of the circuit modules, and a step of exposing the electrode layers of the circuit modules of the lowermost layer and the electrode layers of the circuit modules other than the lowermost layer by enlarging the guide holes; and a step of forming via holes for penetrating the stacked plurality of circuit modules by disposing conductors in the via holes, thereby electrically connecting the electrode layers. Further, the step of manufacturing the circuit module may include: forming an electrode layer at each of the plurality of circuit modules at a position having a different distance from an opposite surface of a surface of the wiring layer, the opposite surface being an opposite surface to an opposite surface facing the substrate; and stacking the circuit modules in the order of increasing the distance between the electrode layers from the lowermost layer to the uppermost layer.
Further, the step of manufacturing the circuit module may include: forming an electrode layer at each of the plurality of circuit modules at a position having a different distance from an opposing surface of a surface of the wiring layer, the opposing surface being a surface opposing the substrate; and stacking the circuit modules in the order of increasing the distance between the electrode layers from the lowermost layer to the uppermost layer.
In the step of forming the passage hole, it is preferable that the passage hole is formed so as to be reduced in diameter from the uppermost layer to the lowermost layer.
In the step of forming the electrode layer, the electrode layer is preferably formed at a position matching a diameter reduction ratio of the via hole, among positions in a direction intersecting a lamination direction of the circuit modules to be laminated.
Furthermore, the present invention relates to a semiconductor module having: a plurality of circuit modules stacked on each other, and via holes extending in a stacking direction and electrically connecting the plurality of circuit modules, the circuit modules including: a substrate; a wiring layer arranged to face the substrate with one surface thereof being an opposing surface; and an electrode layer disposed inside the wiring layer, wherein the circuit module is stacked such that the wiring layer and the substrate are alternately disposed from a lowermost layer to an uppermost layer, the via holes are reduced in diameter from the uppermost layer to the lowermost layer, and a removal thickness of the electrode layer removed in a stacking direction when forming via holes for forming the via holes is 2 to 5 times a removal thickness of the electrode layer disposed on the lowermost layer side.
Furthermore, the present invention relates to a semiconductor module having: a plurality of circuit modules stacked on each other, and via holes extending in a stacking direction and electrically connecting the plurality of circuit modules, the circuit modules including: a substrate; a wiring layer arranged to face the substrate with one surface thereof being an opposing surface; and an electrode layer disposed inside the wiring layer, wherein the circuit module is stacked such that the wiring layers and the substrate are alternately disposed from a lowermost layer to an uppermost layer, and the circuit module is stacked in order from a distance from an opposite surface of surfaces of the wiring layers to the electrode layer, the opposite surface being an opposite surface to an opposite surface facing the substrate, and the via hole is reduced in diameter from the uppermost layer to the lowermost layer.
Furthermore, the present invention relates to a semiconductor module having: a plurality of circuit modules stacked on each other, and via holes extending in a stacking direction and electrically connecting the plurality of circuit modules, the circuit modules including: a substrate; a wiring layer disposed to face the substrate with one surface thereof being an opposing surface; and an electrode layer disposed inside the wiring layer, wherein the circuit modules are stacked such that the wiring layers and the substrate are alternately disposed from the lowermost layer to the uppermost layer, and are stacked in order from the lowermost layer to the uppermost layer in a distance from an opposing surface of the wiring layers, which is a surface opposing the substrate, to the electrode layer, and the via holes are reduced in diameter from the uppermost layer to the lowermost layer.
Preferably, the electrode layer is disposed at a position matching a diameter reduction ratio of the via hole, among positions in a direction intersecting a lamination direction of the circuit modules to be laminated.
The electrode layer is preferably formed in a ring shape or a tab shape in plan view.
Effects of the invention
According to the present invention, a semiconductor module and a method for manufacturing the same can be provided, in which damage to an electrode can be suppressed.
Drawings
Fig. 1 is a schematic cross-sectional view of a semiconductor module according to a first embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of a semiconductor module in which a plurality of circuit modules of the semiconductor module according to the first embodiment are stacked.
Fig. 3 is a schematic cross-sectional view of a semiconductor module in which a part of a via hole is formed in the semiconductor module according to the first embodiment.
Fig. 4 is a schematic cross-sectional view of a semiconductor module in which a part of a via hole is formed in the semiconductor module according to the first embodiment.
Fig. 5 is a schematic cross-sectional view of a semiconductor module in which a part of a via hole is formed in the semiconductor module according to the first embodiment.
Fig. 6 is a schematic cross-sectional view of a semiconductor module in which a part of a via hole is formed in the semiconductor module according to the first embodiment.
Fig. 7 is a schematic cross-sectional view of a semiconductor module in which a via hole is formed in the semiconductor module according to the first embodiment.
Fig. 8 is a schematic cross-sectional view of a semiconductor module in which an oxide film layer is formed in a via hole of the semiconductor module according to the first embodiment.
Fig. 9 is a schematic cross-sectional view of a semiconductor module in which a via hole is formed in the semiconductor module according to the first embodiment.
Fig. 10 is a schematic cross-sectional view of a semiconductor module according to a second embodiment of the present invention.
Fig. 11 is a schematic cross-sectional view of a semiconductor module in which a plurality of circuit modules of the semiconductor module according to the second embodiment are stacked.
Fig. 12 is a plan view showing an electrode layer formed in a circuit module at the lowermost layer of a semiconductor module according to a third embodiment of the present invention.
Fig. 13 is a plan view showing an electrode layer formed in a circuit module other than the lowermost layer of the semiconductor module according to the third embodiment.
Fig. 14 is a plan view showing another example of an electrode layer formed in a circuit module other than the lowermost layer of the semiconductor module according to the third embodiment.
Fig. 15 is a plan view showing another example of an electrode layer formed in a circuit module other than the lowermost layer of the semiconductor module according to the third embodiment.
Detailed Description
The semiconductor module 1 and the method for manufacturing the same according to each embodiment of the present invention will be described below with reference to fig. 1 to 15.
Before explaining the semiconductor module 1 and the method of manufacturing the same according to each embodiment, an outline of the semiconductor module 1 according to each embodiment will be described.
The semiconductor module 1 according to each embodiment is, for example, a memory module, and is configured by stacking a plurality of circuit modules 20 (RAMs) on an interface module 10 (e.g., an Active Interposer (AIP)). The interface module 10 is also an example of the circuit module 20. A structure that does not use the interface module 10 is also an example of the memory module. In the semiconductor module 1 according to each embodiment, the plurality of circuit modules 20 are electrically connected to each other through one through electrode (via hole (via) 50).
In the semiconductor module 1 according to each embodiment, it is preferable that the formation position of the electrode layer 23 exposed by etching is changed in consideration of the etching amount of the circuit module 20 to be stacked by etching for forming the via hole 50. For example, a case where the via holes 30, which are reduced in diameter in the thickness direction from the surface of the stacked circuit modules 20, are formed by intermittently etching the stacked circuit modules 20 is considered. In this case, the diameter of the via hole 30 on the front surface side is larger than that on the distal end side in the depth direction, and the etched area of the circuit module 20 is larger. Therefore, even when etching is performed for the same time, the amount of etching on the front surface side of the stacked circuit module 20 is larger than the amount of etching on the front end side in the depth direction of the stacked circuit module 20. In this case, in each embodiment, the formation position of the electrode layer 23 exposed by etching can be adjusted. In the following embodiments, the front side of the semiconductor module 1 is referred to as the upper layer side, and the distal end side in the depth direction is referred to as the lower layer side.
[ first embodiment ]
A semiconductor module 1 according to a first embodiment of the present invention and a method for manufacturing the same will be described below with reference to fig. 1 to 10.
As shown in fig. 1, the semiconductor module 1 includes an interface module 10, a plurality of circuit modules 20, via holes 30, an oxide film 40, via holes 50, and electrode terminals 60. The semiconductor module 1 is, for example, a DRAM (Dynamic Random Access Memory).
The interface module 10 is a plate-like body and is disposed at the lowermost layer of the semiconductor module 1. The interface module 10 includes an interface substrate 11, an interface wiring layer 12, and an interface electrode layer 13. The interface module 10 may be an example of the circuit module 20 described later. Therefore, in the following description, the interface board 11 may be referred to as a board 21. The interface wiring layer 12 may be also referred to as a wiring layer 22. The interface electrode layer 13 may be also referred to as an electrode layer 23.
The interface substrate 11 is, for example, a Si substrate.
The interface wiring layer 12 is disposed to face the interface substrate 11 on one of the facing surfaces 121 intersecting the stacking direction. The interface wiring layer 12 has, for example, an insulating layer (e.g., SiO)2Not shown) covers the electronic circuit (not shown).
The interface electrode layer 13 is, for example, an Al layer. The interface electrode layer 13 is disposed inside the interface wiring layer 12. In the present embodiment, the interface electrode layer 13 is disposed at the following positions: the interface wiring layer 12 is separated from an opposite surface 122 of the interface wiring layer 12, which is opposite to the opposite surface 121, by a predetermined distance in the thickness direction of the interface wiring layer 12. The interface electrode layer 13 is disposed at a position exposed at the bottom of a via hole 30 described later in a direction intersecting the stacking direction.
A plurality of circuit modules 20 are stacked on the interface module 10. Specifically, the plurality of circuit blocks 20 are disposed adjacent to the opposite surface 122 of the interface wiring layer 12 of the interface block 10. Each of the plurality of circuit modules 20 includes a substrate 21, a wiring layer 22, and an electrode layer 23.
The substrate 21 is, for example, a Si substrate. The substrate 21 is formed by polishing one surface, for example. In the present embodiment, one surface of the substrate 21 is disposed adjacent to the interface wiring layer 12 of the adjacent interface module 10 or the wiring layer 22 of the circuit module 20.
The wiring layer 22 is disposed on the other surface side of the substrate 21. Specifically, the wiring layer 22 is disposed to face the substrate 21 with one surface thereof being a facing surface 221. The wiring layer 22 is configured to cover an electronic circuit (not shown) with an insulating layer (not shown).
The electrode layer 23 is disposed inside the wiring layer 22. The electrode layer 23 is, for example, an Al layer. In the present embodiment, the electrode layer 23 may be formed at a position (for example, t1 to t5 in fig. 2) different in distance from the opposite surface 222 of the surface of the wiring layer 22, the opposite surface 222 being opposite to the facing surface 221 facing the substrate 21, in each circuit module 20. In the present embodiment, the electrode layer 23 is disposed so that the distance from the wiring layer 22 to the substrate 21 (or the facing surface 221) is the same as the distance between the electrode layer 23 and the substrate 21 in the other circuit module 20 (and the interface module 10) (e.g., t0 in fig. 2). The electrode layer 23 is disposed at a position exposed at a position of a via hole 30 described later in a direction intersecting the stacking direction.
According to the above interface module 10 and circuit module 20, as shown in fig. 2, the substrate 21 (interface substrate 11) is stacked in order from the lowermost layer to the uppermost layer, and the wiring layer 22 (interface wiring layer 12) is stacked in order from the lowermost layer to the uppermost layer. Thus, the interface module 10 and the circuit module 20 are stacked so that the substrate 21 and the wiring layer 22 are alternately arranged from the lowermost layer to the uppermost layer. The circuit module 20 at the uppermost layer is disposed with the opposite surface of the wiring layer 22 exposed.
In the present embodiment, four circuit modules 20 are arranged on the interface module 10. The interface module 10 and the four circuit modules 20 are preferably stacked in order of decreasing distance from the opposing surfaces 222(122) of the surfaces of the wiring layers 22(12), which are opposing surfaces 221(121) that face the substrates 21(11), to the uppermost layer from the lowermost layer, and the opposing surfaces 222(122) are opposing surfaces that face the substrates 21 (11). For example, the interface module 10 and the four circuit modules 20 may be stacked in the order of t1 > t2 > t3 > t4 > t5 from t1 to t5 shown in fig. 2.
The electrode layer 23 is disposed at a position matching the diameter reduction ratio of a via hole 50 described later in a direction intersecting the stacking direction of the stacked circuit modules 20. That is, the electrode layer 23 is disposed along a position along the formation surface of the via hole 50 described later.
The via holes 30 are disposed from the uppermost layer of the plurality of circuit modules 20 to the interface module 10. Specifically, the via holes 30 are arranged from the uppermost layer of the plurality of circuit modules 20 to the interface wiring layer 12 of the interface module 10. The passage hole 30 is formed in a tapered shape that decreases in diameter from the uppermost layer to the lowermost layer. Further, the via hole 30 exposes the interface electrode layer 13 of the interface module 10 at the tip end. The via hole 30 is formed in a stepped shape to expose the upper surface of the electrode layer 23 of the circuit module 20.
The oxide film 40 is, for example, SiO2The film of (1). The oxide film 40 is disposed along the formation surface of the via hole 30. The oxide film 40 is disposed so as to expose the upper surface of the electrode layer 23.
The via hole 50 is disposed at the position of the via hole 30. Specifically, the via hole 50 is disposed at a position where the via hole 30 is filled. The via hole 50 is, for example, metal. The via hole 50 is disposed at the position of the via hole 30, and is disposed adjacent to the oxide film 40. The via hole 50 electrically connects the plurality of circuit modules 20. More specifically, the via hole 50 electrically connects the electrode layers 23 of the plurality of circuit modules 20. Further, the via hole 50 electrically connects the interface electrode layer 13 of the interface module 10 and the electrode layers 23 of the plurality of circuit modules 20. In the present embodiment, the via hole 50 is reduced in diameter in a direction opposite to the direction in which the circuit modules 20 are stacked. In other words, the via hole 50 is formed in a tapered shape with a diameter decreasing from the uppermost layer to the lowermost layer.
According to the above via hole 30 and via hole 50, in the present embodiment, the interface electrode layer 13 and the electrode layer 23 are removed in the stacking direction when the via hole 30 for forming the via hole 50 is formed. It is considered that the removal thickness of the other electrode layer 23 in the stacking direction is, for example, 2 times to 5 times the removal thickness of the interface electrode layer 13 disposed on the lowermost layer side in the stacking direction.
The electrode terminals 60 are disposed above the wiring layer 22 of the circuit module 20. More specifically, the electrode terminals 60 are disposed on the surface of the circuit module 20 on the uppermost layer opposite to the wiring layer 22. The electrode terminal 60 is formed of the same metal as the via hole 50, for example. The electrode terminals 60 are disposed to electrically connect the respective electrode layers 23 (interface electrode layers 13) to the outside via the via holes 50.
Next, a method for manufacturing the semiconductor module 1 of the present embodiment will be described with reference to fig. 1 to 10.
The method of manufacturing the semiconductor module 1 includes: a step of manufacturing the circuit module 20, a step of laminating the circuit module 20, a step of forming the via hole 30, a step of electrically connecting the electrode layer 23 (interface electrode layer 13), and a step of forming the electrode terminal 60.
First, the steps of manufacturing the circuit module 20 are performed. The step of manufacturing the circuit module 20 includes a step of preparing the substrate 21 and the wiring layer 22 and a step of forming the electrode layer 23.
In the step of preparing the substrate 21 and the wiring layer 22, the circuit module 20 having the substrate 21 and the wiring layer 22 adjacent to one surface of the substrate 21 is prepared. Next, in the step of forming the electrode layer 23, the electrode layer 23 is formed for each of the plurality of circuit modules 20. In this case, the electrode layer 23 may be formed at a position having a different distance from the opposite surface 222 of the surface of the wiring layer 22, the opposite surface 222 being opposite to the opposite surface 221 facing the substrate 21. In the step of forming the electrode layer 23, the electrode layer 23 is formed at a position matching the diameter reduction ratio of the via hole 30 among positions in a direction intersecting the lamination direction of the circuit modules 20 to be laminated.
Next, a step of stacking the circuit modules 20 is performed. In the step of stacking the circuit modules 20, as shown in fig. 2, a plurality of circuit modules 20 are stacked on the opposite surface of the interface wiring layer 12 of the interface module 10. The circuit modules 20 may be stacked such that the wiring layers 22 and the substrates 21 are alternately arranged from the lowermost layer to the uppermost layer, and the distance between the electrode layers 23 is gradually increased from the lowermost layer to the uppermost layer. Then, a hard mask 70 having a thickness etched for substantially the same time as the time for etching the substrate 21 of the circuit module 20 is disposed on the surface opposite to the wiring layer 22 of the circuit module 20 on the uppermost layer.
Next, a step of forming the via hole 30 is performed. In the step of forming the via hole 30, the via hole 30 is formed so as to extend from the uppermost layer to the lowermost layer in the stacking direction of the circuit modules 20 and expose the electrode layer 23 (interface electrode layer 13) of each circuit module 20. The step of forming the via hole 30 includes a step of forming a guide hole of the via hole 30 and a step of exposing the electrode layer 23 (interface electrode layer 13).
In the step of forming the guide hole of the via hole 30, the guide hole of the via hole 30 extending in the lamination direction of the circuit module 20 from the uppermost layer to the lowermost layer is formed. For example, in the step of forming the guide hole of the via hole 30, the guide hole of the via hole 30 that is to expose the electrode layer 23 (interface electrode layer 13) disposed in the lowermost layer is formed. In the present embodiment, the guide hole having the through hole 30 is formed to a depth up to the facing surface 221 of the circuit module 20 (the circuit module 20 of the fourth layer) immediately above the interface module 10.
First, as shown in fig. 3, a guide hole of the via hole 30 is formed in the uppermost layer of the circuit module 20. Specifically, the photoresist 80 is disposed at a position other than the formation position of the guide hole of the via hole 30 in the exposed surface of the hard mask 70. Then, a guide hole is formed for the via hole 30 up to the position of the facing surface 221 of the uppermost wiring layer 22. At this time, the guide holes of the via holes 30 are formed with a diameter that does not expose the electrode layer 23 of the uppermost circuit module 20.
Next, as shown in fig. 4, a guide hole is formed up to the via hole 30 of the next layer (second layer) of the uppermost layer. Specifically, the photoresist 80 is disposed so as to enlarge the diameter of the formation position of the guide hole of the via hole 30 that has been formed. Then, a guide hole of the via hole 30 is formed up to the position of the facing surface 221 of the wiring layer 22 of the second layer. At this time, the guide holes of the via hole 30 are formed with a diameter that does not expose the electrode layers 23 of the circuit modules 20 of the uppermost layer and the second layer.
Next, as shown in fig. 5, a guide hole of the via hole 30 is formed up to the next layer (third layer) of the second layer. Specifically, the photoresist 80 having an enlarged diameter at the formation position of the guide hole of the via hole 30 is disposed. Then, a guide hole of the via hole 30 is formed up to the position of the facing surface 221 of the wiring layer 22 of the third layer. At this time, the guide holes of the via holes 30 are formed with a diameter that does not expose the electrode layers 23 of the circuit modules 20 of the uppermost layer to the third layer.
Next, as shown in fig. 6, a guide hole of the via hole 30 is formed up to the next layer (fourth layer) of the third layer. Specifically, the photoresist 80 having an enlarged diameter at the formation position of the guide hole of the via hole 30 is disposed. Then, a guide hole of the via hole 30 is formed up to the position of the facing surface of the wiring layer 22 of the fourth layer. At this time, the guide hole of the via hole 30 is formed with a diameter that can expose the end face of the electrode layer 23 in the direction intersecting the lamination direction of the circuit modules 20 of the uppermost layer to the fourth layer, but does not expose one face in the lamination direction. Thus, in the present embodiment, the guide hole is formed using the substrate 21 of the circuit module 20 immediately above the interface module 10 as the via hole 30 at the bottom. In the present embodiment, the guide hole of the via hole 30 having a diameter decreasing from the uppermost layer to the lowermost layer is formed to a diameter such that the electrode layer 23 (interface electrode layer 13) is not exposed in the stacking direction.
Next, a step of exposing the electrode layer 23 (interface electrode layer 13) is performed. In the step of exposing the electrode layer 23 (interface electrode layer 13), the electrode layer 23 (interface electrode layer 13) of the lowermost circuit module 20 and the electrode layer 23 of the circuit module 20 other than the lowermost circuit module are exposed by enlarging the guide hole of the via hole 30. For example, as shown in fig. 7, the guide hole of the via hole 30 is enlarged in the lamination direction until the interface electrode layer 13 of the interface module 10 is exposed. The guide hole of the via hole 30 is enlarged to a diameter that exposes the electrode layer 23 of each circuit module 20 arranged along the guide hole of the via hole 30. Specifically, first, the photoresist 80 having an enlarged diameter is disposed at the formation position of the via hole 30. Then, the via hole 30 is formed up to the position of the interface electrode layer 13 of the interface module 10. Through this step, the via hole 30 is formed with a diameter such that one surface in the stacking direction of the electrode layers 23 of the circuit modules 20 of the uppermost layer to the fourth layer and one surface in the stacking direction of the interface electrode layer 13 of the interface module 10 are exposed. Thus, the via hole 30 having a diameter decreasing from the uppermost layer to the lowermost layer is formed so as to expose the electrode layer 23 of each of the stacked circuit modules 20 and the interface electrode layer 13 of the interface module 10.
Next, a step of electrically connecting the electrode layer 23 (interface electrode layer 13) is performed. That is, a step of electrically connecting the electrode layers 23 (interface electrode layer 13) by forming via holes 50 penetrating the stacked plurality of circuit modules 20 is performed. The step of electrically connecting electrode layer 23 (interface electrode layer 13) includes a step of forming oxide film 40 and a step of forming via hole 50.
First, a step of forming the oxide film 40 is performed. In the step of forming the oxide film 40, the oxide film 40 is formed as shown in fig. 8. Specifically, the photoresist 80 and the hard mask 70 are removed. Then, an oxide film 40 is formed at the position of the formed via hole 30. After that, the oxide film 40 at the position where the interface electrode layer 13 of the interface module 10 and the electrode layer 23 of each circuit module 20 overlap in the stacking direction is removed by anisotropic etching. Thereby, the interface electrode layer 13 of the interface module 10 and the electrode layer 23 of the circuit module 20 are exposed.
Next, a step of forming a via hole 50 is performed. In the step of forming the via hole 50, the via hole 50 for connecting the electrode layers 23 (interface electrode layer 13) by disposing a conductor in the via hole 30 is formed. In the step of forming the via hole 50, for example, as shown in fig. 9, the via hole 50 is formed at the formation position of the via hole 30. The via hole 50 is formed by, for example, plating. The interface electrode layer 13 of the interface module 10 and the electrode layer 23 of each circuit module 20 are electrically connected.
Next, a step of forming the electrode terminal 60 is performed. In the step of forming the electrode terminal 60, the electrode terminal 60 is formed as shown in fig. 1. The electrode terminal 60 is formed in a plate shape along, for example, the opposite surface 222 of the uppermost wiring layer 22.
According to the semiconductor module 1 of the first embodiment as described above, the following effects can be obtained.
(1) A method of manufacturing a semiconductor module 1, the semiconductor module 1 being manufactured by stacking a plurality of circuit modules 20, the method of manufacturing the semiconductor module 1 comprising: a step of manufacturing a plurality of circuit modules 20 having a substrate 21 and a wiring layer 22 adjacent to one surface of the substrate 21, the step including a step of forming an electrode layer 23 for each of the plurality of circuit modules; a step of stacking a plurality of circuit modules 20 from the lowermost layer to the uppermost layer, the circuit modules 20 being stacked such that the wiring layers 22 and the substrates 21 are alternately arranged from the lowermost layer to the uppermost layer; a step of forming via holes 30 extending from the uppermost layer to the lowermost layer in the stacking direction of the circuit modules 20 and exposing the electrode layers 23 of the circuit modules 20, the step including a step of forming guide holes of the via holes 30 extending from the uppermost layer to the lowermost layer in the stacking direction of the circuit modules 20, and a step of exposing the electrode layers 23 of the circuit modules 20 at the lowermost layer and the electrode layers 23 of the circuit modules 20 not at the lowermost layer by enlarging the guide holes; and a step of forming via holes 50 penetrating the plurality of stacked circuit modules 20 by disposing conductors in the via holes 30 to electrically connect the electrode layers 23. Thus, after the guide hole of the via hole 30 is formed toward the lower layer side, the guide hole is enlarged to expose the electrode layer 23. Although the guide hole is formed in the circuit module 20 on the upper layer side as compared with the lower layer side, both the electrode layer 23 on the upper layer side and the electrode layer 23 on the lower layer side are exposed by enlarging the guide hole. Therefore, the electrode layer 23 of the circuit module 20 on the upper layer side can be suppressed from being etched. Further, the step of manufacturing the plurality of circuit modules 20 may include: a step of forming an electrode layer 23 on each of the plurality of circuit modules 20 at a position having a different distance from an opposite surface of the surfaces of the wiring layer 22, the opposite surface being an opposite surface to an opposite surface facing the substrate 21; and a step of stacking the circuit modules 20 in the order of increasing distance of the electrode layer 23 from the lowermost layer to the uppermost layer. This can further suppress etching of the electrode layer 23 of the circuit module 20 on the upper layer side. Therefore, the quality of the semiconductor module 1 can be improved, and the yield can be improved.
(2) In the step of forming the via hole 30, the via hole 30 is formed so as to be reduced in diameter from the uppermost layer to the lowermost layer. This makes it possible to form the via holes 30 more easily than in the case where the via holes 30 having the same diameter are formed in the stacking direction.
(3) In the step of forming the electrode layer 23, the electrode layer 23 is formed at a position matching the diameter reduction ratio of the via hole 30, among positions in a direction intersecting the lamination direction of the circuit modules 20 to be laminated. This can expose the upper surface of the electrode layer 23 of each circuit module 20, and thus can increase the contact area between the electrode layer 23 and the via hole 50.
(4) A semiconductor module 1, comprising: the circuit module 20 includes a plurality of circuit modules 20 stacked one on another, and via holes 50 extending in the stacking direction and electrically connecting the plurality of circuit modules 20, and the circuit module 20 includes: a substrate 21; a wiring layer 22 disposed so as to face the substrate 21 with one surface thereof being a facing surface 221; and an electrode layer 23 disposed inside the wiring layer 22, wherein the circuit module 20 is laminated such that the wiring layers 22 and the substrate 21 are alternately disposed from the lowermost layer to the uppermost layer, and the via holes 50 are reduced in diameter from the uppermost layer to the lowermost layer, and a removal thickness of the electrode layer removed in the laminating direction when forming the via holes 30 for forming the via holes 50 is 2 times to 5 times a removal thickness of the electrode layer 23 (interface electrode layer 13) disposed on the lowermost layer side. This can provide a semiconductor module in which damage to the electrode layer 23 is suppressed.
(5) A semiconductor module 1, comprising: the circuit module 20 includes a plurality of circuit modules 20 stacked one on another, and via holes 50 extending in the stacking direction and electrically connecting the plurality of circuit modules 20, and the circuit module 20 includes: a substrate 21; a wiring layer 22 disposed so as to face the substrate 21 with one of the faces thereof being a facing face; and an electrode layer 23 disposed inside the wiring layer 22, wherein the circuit module 20 is stacked such that the wiring layers 22 and the substrate 21 are alternately disposed from the lowermost layer to the uppermost layer, and the wiring layers 22 and the substrate 21 are stacked in order of increasing distance from an opposite surface of the surfaces of the wiring layers 22, which is opposite to the surface facing the substrate 21, to the electrode layer 23 from the lowermost layer to the uppermost layer, and the via holes 50 are reduced in diameter from the uppermost layer to the lowermost layer. This can suppress etching of the electrode layer 23 of the circuit module 20 on the upper layer side. Therefore, the quality of the semiconductor module 1 can be improved, and the yield can be improved.
(6) The electrode layer 23 is disposed at a position corresponding to the diameter reduction ratio of the via hole 50 among positions in a direction intersecting the lamination direction of the circuit module 20 to be laminated. This can expose the upper surface of the electrode layer 23 of each circuit module 20, and thus can increase the contact area between the electrode layer 23 and the via hole 50.
[ second embodiment ]
Next, a semiconductor module 1 according to a second embodiment of the present invention and a method for manufacturing the same will be described with reference to fig. 10 and 11. In describing the second embodiment, the same components are denoted by the same reference numerals, and the description thereof will be omitted or simplified.
The semiconductor module 1 and the method of manufacturing the same according to the second embodiment are different from the first embodiment in that the interface module 10 is formed only of the interface substrate 11 as shown in fig. 10 and 11. The semiconductor module 1 and the method of manufacturing the same according to the second embodiment are also different from the first embodiment in that the circuit module 20 is laminated by disposing the wiring layer 22 on the lower layer side and disposing the substrate 21 on the upper layer side. Accordingly, circuit modules 20 are stacked in the order of increasing the distance from the surface of wiring layer 22 facing substrate 21 to electrode layer 23 from the lowest layer to the highest layer, which is different from the first embodiment. Further, the thickness from the electrode layer 23 to the wiring layer 22 on the lower layer side is the same between the circuit modules 20, which is also different from the first embodiment. The method for manufacturing the semiconductor module 1 according to the second embodiment is also different from the first embodiment in that the hard mask 70 is not used. In the present embodiment, five circuit modules 20 are stacked on the interface board 11 (10).
According to the semiconductor module 1 of the second embodiment as described above, the following effects can be obtained.
(7) A manufacturing method of manufacturing a semiconductor module 1 by stacking a plurality of circuit modules 20, comprising: a step of manufacturing a plurality of circuit modules 20 having a substrate 21 and a wiring layer 22 adjacent to one surface of the substrate 21, the step including a step of forming an electrode layer 23 for each of the plurality of circuit modules; a step of stacking a plurality of circuit modules 20 from the lowermost layer to the uppermost layer, the circuit modules 20 being stacked such that the wiring layers 22 and the substrates 21 are alternately arranged from the lowermost layer to the uppermost layer; a step of forming via holes 30 extending in the stacking direction of the circuit modules 20 from the uppermost layer to the lowermost layer and exposing the electrode layers 23 of the circuit modules 20, the step including a step of forming guide holes of the via holes 30 extending in the stacking direction of the circuit modules 20 from the uppermost layer to the lowermost layer, and a step of exposing the electrode layers 23 of the circuit modules 20 at the lowermost layer and the electrode layers 23 of the circuit modules 20 at layers other than the lowermost layer by enlarging the guide holes; forming a via hole 30 exposing the electrode layer 23; and a step of forming via holes 50 penetrating the plurality of stacked circuit modules 20 by disposing conductors in the via holes 30 to electrically connect the electrode layers 23. Thus, after the guide hole of the via hole 30 is formed toward the lower layer side, the guide hole is enlarged to expose the electrode layer 23. Although the guide hole is formed in the circuit module 20 on the upper layer side as compared with the lower layer side, both the electrode layer 23 on the upper layer side and the electrode layer 23 on the lower layer side are exposed by enlarging the guide hole. Therefore, the electrode layer 23 of the circuit module 20 on the upper layer side can be suppressed from being etched. Further, the step of manufacturing the plurality of circuit modules 20 may include: forming an electrode layer 23 on each of the plurality of circuit modules 20 at a position having a different distance from an opposing surface of the wiring layer 22, the opposing surface being a surface opposing the substrate 21; and a step of stacking the circuit modules 20 in the order of increasing distance of the electrode layer 23 from the lowermost layer to the uppermost layer. This can further suppress etching of the electrode layer 23 of the circuit module 20 on the upper layer side. Therefore, the quality of the semiconductor module 1 can be improved, and the yield can be improved.
(8) A semiconductor module 1, comprising: the circuit module 20 includes a plurality of circuit modules 20 stacked one on another, and via holes 50 extending in the stacking direction and electrically connecting the plurality of circuit modules 20, and the circuit module 20 includes: a substrate 21; a wiring layer 22 disposed to face the substrate 21 with one of the faces thereof being a facing face; and an electrode layer 23 disposed inside the wiring layer 22, wherein the circuit module 20 is stacked such that the wiring layers 22 and the substrates 21 are alternately disposed from the lowermost layer to the uppermost layer, and the wiring layers 22 and the substrates are stacked in order from the lowermost layer to the uppermost layer in a distance from a surface of the wiring layer 22 facing the substrate 21 to the electrode layer 23 from smaller to larger, and the via hole 50 is reduced in diameter from the uppermost layer to the lowermost layer. This can suppress etching of the electrode layer 23 of the circuit module 20 on the upper layer side. Therefore, the quality of the semiconductor module 1 can be improved, and the yield can be improved.
[ third embodiment ]
Next, a semiconductor module 1 according to a third embodiment of the present invention and a method for manufacturing the same will be described with reference to fig. 12 to 15. In describing the third embodiment, the same components are denoted by the same reference numerals, and the description thereof will be omitted or simplified.
The semiconductor module 1 according to the third embodiment is a semiconductor module in which the shape of the electrode layer 23 is improved. In the semiconductor module 1 according to the third embodiment, as shown in fig. 12, the lowermost electrode layer 23 (or the interface electrode layer 13) is formed in a circular shape or a polygonal shape in plan view. As shown in fig. 13 and 14, the electrode layer 23 other than the lowermost layer is formed in a ring shape. As another example, as shown in fig. 15, the electrode layers 23 other than the lowermost layer are formed in a tab shape.
According to the semiconductor module 1 of the third embodiment as described above, the following effects can be obtained.
(9) The electrode layer 23 is formed in a ring shape or a tab shape in plan view. This allows the electrode layer 23 to be exposed to the via hole 30 even when the via hole 30 is misaligned. In the shapes of fig. 14 and 15, the via hole 30 and the via hole 50 are connected to only a part of the electrode layer 23 (for example, the upper side of the ring in fig. 14 and the lower side of the projection in fig. 15). As a result, the area occupied by the electrode 23 can be removed, and the arrangement density in the case where many electrode layers 23 and via holes 50 are arranged can be increased, so that the area of the semiconductor module 1 can be removed.
While the preferred embodiments of the semiconductor module and the method for manufacturing the same according to the present invention have been described above, the present invention is not limited to the above embodiments and can be modified as appropriate.
For example, in the above embodiment, the electrode layer 23 is formed at a position having a different distance from the facing surface 221 facing the substrate 21 or from the opposite surface 222 opposite to the facing surface 221 for each of the plurality of circuit modules 20, but the present invention is not limited thereto. For example, other methods may be employed as long as damage to the electrode layer 23 due to etching can be suppressed. For example, the distance from the facing surface 221 facing the substrate 21 or the distance from the opposite surface 222 opposite to the facing surface 221 may be the same or substantially the same for the formation position of a part of the electrode layer 23. The formation position of the electrode layer 23 in the direction intersecting the stacking direction may be adjusted according to the amount of etching predicted in each circuit module 20.
In the above embodiment, it is preferable that all the electrode layers 23 are not exposed in the step of forming the guide hole of the via hole 30, but the present invention is not limited thereto. In the step of forming the guide hole of the via hole 30, a part of the electrode layer 23 may be exposed. That is, in the step of exposing, the lowermost electrode layer 23 and at least one electrode layer 23 that is not the lowermost layer may be exposed.
In the step of forming the guide hole of the via hole 30, for example, a region of the surface of all the electrode layers 23 intersecting the stacking direction may be exposed. That is, in the step of exposing, the lowermost electrode layer 23 and at least one region other than a partial region of the lowermost electrode layer 23 may be exposed.
The structure and the operational effects of the above-described embodiments are achieved as long as damage to the electrode layer 23 can be reduced as compared with damage to the electrode layer 23 that occurs using the electrode layer 23 as a mask layer.
For example, in the above embodiment, the electrode layer 23 is disposed so that the end face in the direction intersecting the stacking direction is exposed when the via hole 30 is formed in the circuit module 20 immediately before the lowermost layer. In contrast, the electrode layer 23 may be disposed so that an end face in a direction intersecting the stacking direction is exposed when the via hole 30 is formed in the circuit module 20 in the lowermost layer. This can suppress the electrode layer 23 from being etched even in the direction intersecting the stacking direction of the electrode layer 23.
In the above embodiment, the example of forming one via hole 30 has been described, but the present invention is not limited to this. For example, the via holes 30 may be formed simultaneously at a plurality of positions.
Description of the reference numerals
1: semiconductor module
10: interface module
20: circuit module
11. 21: substrate
12. 22: wiring layer
13. 23: electrode layer
30: passage hole
50: conducting hole
121. 221: facing surface
122. 222: the opposite side.
Claims (10)
1. A method of manufacturing a semiconductor module in which a plurality of circuit modules are stacked to manufacture the semiconductor module, the method comprising:
a step of manufacturing a plurality of circuit modules having a substrate and a wiring layer adjacent to one surface of the substrate, the step including a step of forming an electrode layer for each of the plurality of circuit modules;
a step of stacking a plurality of the circuit modules from the lowermost layer to the uppermost layer, the circuit modules being stacked such that the wiring layers and the substrates are alternately arranged from the lowermost layer to the uppermost layer;
a step of forming via holes extending from an uppermost layer to a lowermost layer in a stacking direction of the circuit modules and exposing the electrode layers of the circuit modules, the step including a step of forming guide holes of via holes extending from the uppermost layer to the lowermost layer in the stacking direction of the circuit modules, and a step of exposing the electrode layers of the circuit modules of the lowermost layer and the electrode layers of the circuit modules other than the lowermost layer by enlarging the guide holes; and
and disposing a conductor in the via hole to form a via hole through which the plurality of stacked circuit blocks pass, thereby electrically connecting the electrode layers.
2. The method for manufacturing a semiconductor module according to claim 1, comprising:
a step of forming an electrode layer at a position having a different distance from an opposite surface of a surface of the wiring layer, the opposite surface being an opposite surface to an opposite surface facing the substrate, for each of the plurality of circuit modules; and
and a step of stacking the circuit modules in the order of decreasing distance between the electrode layers from the lowermost layer to the uppermost layer in the step of stacking the circuit modules from the lowermost layer to the uppermost layer.
3. The method for manufacturing a semiconductor module according to claim 1, comprising:
a step of forming an electrode layer at a position having a different distance from an opposing surface of a surface of the wiring layer, the opposing surface being a surface opposing the substrate, for each of the plurality of circuit modules; and
and a step of stacking the circuit modules in the order of decreasing distance between the electrode layers from the lowermost layer to the uppermost layer in the step of stacking the circuit modules from the lowermost layer to the uppermost layer.
4. The method for manufacturing a semiconductor module according to any one of claims 1 to 3,
in the step of forming the via hole, the via hole is formed so as to be reduced in diameter from the uppermost layer to the lowermost layer.
5. The method for manufacturing a semiconductor module according to claim 4, wherein,
in the step of forming the electrode layer, the electrode layer is formed at a position matching a diameter reduction ratio of the via hole, among positions in a direction intersecting a lamination direction of the circuit modules to be laminated.
6. A semiconductor module, comprising: a plurality of circuit modules stacked on each other, and via holes extending in the stacking direction and electrically connecting the plurality of circuit modules,
the circuit module has:
a substrate;
a wiring layer arranged to face the substrate with one of the faces thereof being an opposing face; and
an electrode layer disposed inside the wiring layer,
the circuit modules are stacked such that the wiring layers and the substrate are alternately arranged from the lowermost layer to the uppermost layer,
the via hole is reduced in diameter from the uppermost layer to the lowermost layer,
the removal thickness of the electrode layer removed in the stacking direction when forming the via hole for forming the via hole is 2 to 5 times the removal thickness of the electrode layer other than the removal thickness of the electrode layer disposed on the lowermost layer side.
7. A semiconductor module, comprising: a plurality of circuit modules stacked on each other, and via holes extending in the stacking direction and electrically connecting the plurality of circuit modules,
the circuit module has:
a substrate;
a wiring layer arranged to face the substrate with one of the faces thereof being an opposing face; and
an electrode layer disposed inside the wiring layer,
the circuit modules are stacked such that the wiring layers and the substrates are alternately arranged from the lowermost layer to the uppermost layer, and the wiring layers are stacked in order from the lowermost layer to the uppermost layer in such a manner that the distance from the electrode layer to the opposite surface of the surfaces of the wiring layers is gradually increased, the opposite surface being the opposite surface to the surface opposite to the substrate,
the via hole is reduced in diameter from the uppermost layer to the lowermost layer.
8. A semiconductor module, comprising: a plurality of circuit modules stacked on each other, and via holes extending in the stacking direction and electrically connecting the plurality of circuit modules,
the circuit module has:
a substrate;
a wiring layer arranged to face the substrate with one of the faces thereof being an opposing face; and
an electrode layer disposed inside the wiring layer,
the circuit modules are stacked such that the wiring layers and the substrates are alternately arranged from the lowermost layer to the uppermost layer, and are stacked in order from the lowermost layer to the uppermost layer in the order from the smaller to the larger of the distances from the facing surfaces of the wiring layers to the electrode layers, the facing surfaces being surfaces facing the substrates,
the via hole is reduced in diameter from the uppermost layer to the lowermost layer.
9. The semiconductor module according to claim 7 or 8,
the electrode layer is disposed at a position matching a diameter reduction ratio of the via hole, among positions in a direction intersecting a lamination direction of the laminated circuit modules.
10. The semiconductor module according to any one of claims 7 to 9,
the electrode layer is formed in a ring shape or a tab shape in a plan view.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2018/045920 WO2020121491A1 (en) | 2018-12-13 | 2018-12-13 | Semiconductor module and manufacturing method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN113272941A true CN113272941A (en) | 2021-08-17 |
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| CN201880100179.4A Pending CN113272941A (en) | 2018-12-13 | 2018-12-13 | Semiconductor module and method for manufacturing the same |
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| Country | Link |
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| JP (1) | JP6798730B2 (en) |
| CN (1) | CN113272941A (en) |
| WO (1) | WO2020121491A1 (en) |
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| JPH08167589A (en) * | 1994-12-12 | 1996-06-25 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JP2001044357A (en) * | 1999-07-26 | 2001-02-16 | Seiko Epson Corp | Semiconductor device and manufacture thereof |
| JP2006287211A (en) * | 2005-03-08 | 2006-10-19 | Sharp Corp | Semiconductor device, stacked semiconductor device and method of fabricating the devices |
| US9343392B2 (en) * | 2012-06-29 | 2016-05-17 | Sony Corporation | Semiconductor device, manufacturing method for semiconductor device, and electronic device |
| JP6391999B2 (en) * | 2014-06-13 | 2018-09-19 | 株式会社ディスコ | Manufacturing method of laminated device |
| JP6485897B2 (en) * | 2014-09-16 | 2019-03-20 | 国立大学法人東京工業大学 | Manufacturing method of semiconductor device |
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2018
- 2018-12-13 CN CN201880100179.4A patent/CN113272941A/en active Pending
- 2018-12-13 JP JP2019543136A patent/JP6798730B2/en active Active
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| JPWO2020121491A1 (en) | 2021-02-15 |
| JP6798730B2 (en) | 2020-12-09 |
| WO2020121491A1 (en) | 2020-06-18 |
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