CN113267989A - Time-to-digital conversion circuit, method and time measuring device - Google Patents
Time-to-digital conversion circuit, method and time measuring device Download PDFInfo
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Abstract
The invention discloses a time-to-digital conversion circuit, a method and a time measuring device, comprising: a multipath ring oscillator and a plurality of signal processing units; the signal processing units are connected with the multipath ring oscillator; the multipath ring oscillator is used for generating a periodic signal for coarse-grained timing and an encoded signal for fine-grained timing and sending the periodic signal and the encoded signal to each signal processing unit; each signal processing unit is used for carrying out time calculation according to the periodic signal and the coding signal to obtain a corresponding time measurement value. The invention greatly reduces the power consumption and the size of the traditional TDC array.
Description
Technical Field
The present invention relates to the field of time measurement technologies, and in particular, to a time-to-digital conversion circuit, a method, and a time measurement apparatus.
Background
In the current time-to-digital conversion chip, a time metering part generally comprises a coarse-grained timing unit and a fine-grained timing unit, specifically, in terms of a circuit structure, the coarse-grained timing is performed by using low-frequency clock pulses as counting signals, and the fine-grained timing is performed by using an oscillator. In addition, when multiple paths of Time measurement are performed simultaneously in the prior art, because the existing oscillator only supports single-path output, each path of TDC (Time-Digital converter) needs to be configured with a separate coarse-grained timing unit and a separate fine-grained timing unit, which may cause an excessive power consumption phenomenon, and especially when a TDC array (as shown in fig. 4) is applied, because oscillation of these timing pulses may generate a large dynamic power consumption, and the dynamic power consumption is linearly increased in relation to the number of cells of the array, such that the architecture is not suitable for application of a large-scale TDC array.
Disclosure of Invention
In view of the above, the present invention provides a time-to-digital conversion circuit, a method and a time measurement apparatus, so as to solve the problems of large size and large power consumption of a large-scale TDC array in the prior art.
One aspect of the present invention provides a time-to-digital conversion circuit, including: a multipath ring oscillator and a plurality of signal processing units; the plurality of signal processing units are all connected with the multipath ring oscillator;
the multipath ring oscillator is used for generating a periodic signal for coarse-grained timing and an encoded signal for fine-grained timing, and sending the periodic signal and the encoded signal to each signal processing unit;
each signal processing unit is used for carrying out time calculation according to the periodic signal and the coding signal to obtain a corresponding time measurement value.
Further, the multipath ring oscillator comprises a plurality of multipath delay units connected end to end; each multipath delay unit is also connected with one or more multipath delay units which are not adjacent to the multipath delay unit;
each multipath delay unit is used for receiving a delay signal of an adjacent multipath delay unit and a delay signal from one or more multipath delay units which are not adjacent to the multipath delay unit;
the delayed signals pass through a plurality of multipath delay units to obtain the periodic signals and the coded signals, and the periodic signals and the coded signals are output to each signal processing unit.
Further, the number of the multipath delay units is determined according to the time measurement precision requirement and/or the adopted chip process.
Further, each multipath delay unit comprises a plurality of cascaded inverters.
Further, the time-to-digital conversion circuit further includes an enable signal generation unit;
the enabling signal generating unit is used for generating an enabling signal and transmitting the enabling signal to each multipath delay unit; the multipath ring oscillator operates when the enable signal is at a first level and stops operating when the enable signal is at a second level.
Further, the time-to-digital conversion circuit further includes a plurality of buffer units; the input end of each buffer unit is connected with the output end of the multipath ring oscillator, and the output end of each buffer unit is correspondingly connected with the input end of each signal processing unit.
Further, each buffer unit includes: a coarse-grained buffer and a fine-grained buffer; the coarse-grained buffer and the fine-grained buffer are both connected with the corresponding signal processing units;
the coarse-grained buffer is configured to receive the periodic signal of the multipath ring oscillator and a corresponding first timing control signal of the signal processing unit, and buffer the periodic signal according to the first timing control signal to obtain coarse-grained time data;
the fine-grained buffer is used for receiving the coded signal of the multipath ring oscillator and a second time sequence control signal of the corresponding signal processing unit, and buffering the coded signal according to the second time sequence control signal to obtain fine-grained time data;
each signal processing unit is used for carrying out time calculation according to the coarse-grained time data and the fine-grained time data to obtain a corresponding time measurement value.
Another aspect of the present invention provides a time-to-digital conversion method applied to a time-to-digital conversion circuit including a multipath ring oscillator and a plurality of signal processing units, including:
generating, by the multipath ring oscillator, a periodic signal for coarse grain timing and an encoded signal for fine grain timing;
and each signal processing unit carries out time calculation according to the periodic signal and the coding signal to obtain a corresponding time measurement value.
Further, each signal processing unit performs time calculation according to the periodic signal and the encoded signal to obtain a corresponding time measurement value, including:
buffering the periodic signal according to the first timing control signal generated by each signal processing unit to obtain coarse-grained time data corresponding to the signal processing units;
buffering the coded signals according to the second time sequence control signals generated by each signal processing unit to obtain fine-grained time data corresponding to the signal processing units;
and each signal processing unit also carries out time calculation according to the coarse-grained time data and the fine-grained time data to obtain a corresponding time measurement value.
In still another aspect, the invention provides a time measuring apparatus including the time-to-digital conversion circuit.
Compared with the prior art, the time-to-digital conversion circuit, the method and the time measuring device have the advantages that: the circuit mainly comprises a shared multipath ring oscillator and a plurality of signal processing units, has a simple structure, and greatly reduces the size of the TDC array; the multi-path ring oscillator can simultaneously generate a periodic signal for coarse-grained timing and an encoding signal for fine-grained timing, then each signal processing unit obtains a corresponding time measurement value according to the periodic signal and the encoding signal, and each TDC does not need to be provided with a separate coarse-grained timing unit and a separate fine-grained timing unit, so that the size and the power consumption of the TDC array are greatly reduced while accurate time is obtained.
Drawings
Fig. 1 is a schematic structural diagram of a time-to-digital conversion circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another time-to-digital conversion circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a multipath ring oscillator according to an embodiment of the present invention.
Fig. 4 is a schematic diagram illustrating a structure of a related art TDC.
Detailed Description
The essence of the technical scheme of the invention is explained in detail in the following with the accompanying drawings.
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
Fig. 1 is a schematic structural diagram of the time-to-digital conversion circuit in this embodiment. For convenience of explanation, only the portions related to the present embodiment are shown.
The time-to-digital conversion circuit of the present embodiment mainly includes: a multipath ring oscillator 100 and a plurality of signal processing units 200, i.e., a time-to-digital conversion circuit of the present embodiment is a form of a TDC array; wherein the inputs of the plurality of signal processing units 200 are each connected to an output of the multipath ring oscillator 100.
Referring to fig. 4, each TDC in the prior art needs to configure a separate coarse-grained timing unit and a separate fine-grained timing unit, which may cause an excessive power consumption, and especially when a TDC array is applied, due to oscillation of the timing pulses, a large dynamic power consumption may be generated, and the number of the timing pulses and the number of the array elements are linearly increased, such that the architecture is not suitable for application of a large-scale TDC array. The present embodiment uses the multi-path ring oscillator 100 to generate the periodic signal for coarse-grained timing and the encoded signal for fine-grained timing, so as to reduce the usage of coarse-grained timing units and fine-grained timing units, which can further reduce the power consumption and the size of the TDC array.
For example, the multipath ring oscillator 100 may simultaneously generate a periodic signal for coarse-grained timing and an encoded signal for fine-grained timing, and transmit the periodic signal and the encoded signal to each signal processing unit 200; each signal processing unit 200 can perform time calculation according to the periodic signal and the encoded signal to obtain a corresponding time measurement value, that is, a plurality of signal processing units 200 share one multipath ring oscillator 100, and fig. 2 shows a case that all signal processing units 200 of this embodiment share one multipath ring oscillator 100.
Optionally, the present embodiment may further include a plurality of multipath ring oscillators, and each multipath ring oscillator may be used by a plurality of signal processing units. It should be understood that the present embodiments do not limit the number of multipath ring oscillators.
Referring to fig. 2, when the number of TDCs in the TDC array is N (N >2), the corresponding signal processing units 200 are arranged from 1 to N, and these signal processing units 200 are mainly used to perform data processing of coarse-grained time and fine-grained time, and obtain a final total time measurement value according to the coarse-grained time and the fine-grained time. It should be understood that the number of the signal processing units 200 is not limited in the present embodiment.
In one embodiment, multipath ring oscillator 100 may include a plurality of multipath delay elements connected end-to-end. Optionally, each multipath delay unit includes a plurality of cascaded inverters.
As shown in FIG. 2, multipath ring oscillator 100 may be constructed from N (N >1) multipath (Multi-path) delay elements connected end-to-end. As shown in fig. 3, the specific circuit structure of the multipath ring oscillator 100 is that a multipath delay unit can support input and output of a plurality of different delay signals, and a periodic oscillation link is formed by combining the multipath delay unit with other nearby multipath delay units, and a period of a periodic signal output after the delay signal passes through M multipath delay units is large, so that the multipath ring oscillator can be used for coarse-grained time measurement. The multi-path ring oscillator 100 outputs a coarse-grained periodic signal for coarse-grained time measurement, and outputs an encoded signal for fine-grained time measurement.
Furthermore, each multipath delay unit is further connected to one or more multipath delay units that are not adjacent to itself, may be connected to one or more multipath delay units that are not adjacent to itself in a clockwise direction, and may also be connected to one or more multipath delay units that are not adjacent to itself in a counterclockwise direction. By "not adjacent to itself" is meant spaced from itself by 1 or more multipath delay elements. In this embodiment, the number of the intervals is not limited, and may be 1 interval, 2 intervals, more intervals, or the like.
Illustratively, referring to fig. 3, the multipath delay unit 1 is connected to a multipath delay unit 4 spaced by 2 multipath delay units in a clockwise direction, the multipath delay unit 1 sends a delay signal to the multipath delay unit 4, the multipath delay unit 4 can receive the delay signals of the multipath delay unit 3 and the multipath delay unit 1, and the multipath delay unit 4 sends the output delay signal to the multipath delay unit 5.
Illustratively, the multipath delay unit 4 is connected to the multipath delay unit 2 spaced by 1 multipath delay unit in the counterclockwise direction, the multipath delay unit 4 sends a delay signal to the multipath delay unit 2, the multipath delay unit 2 can receive the delay signals of the multipath delay unit 1 and the multipath delay unit 4, and the multipath delay unit 2 sends the output delay signal to the multipath delay unit 3.
Each multipath delay unit can receive delay signals of adjacent multipath delay units and delay signals of multipath delay units with preset number at intervals; the delayed signals pass through a plurality of multi-path delay units to obtain the periodic signals and the encoded signals, and the periodic signals and the encoded signals are output to each signal processing unit 200.
It should be understood that, in the embodiment, the number of the multipath delay units is not limited, and in the actual use process, the specific number of the multipath delay units may be determined according to the measurement accuracy that the TDC needs to achieve and/or the chip process that is adopted, for example, the higher the measurement accuracy that the TDC needs to achieve, the more the multipath delay units are used; the larger the area of chip etching employed, the more multipath delay cells are used.
Optionally, referring to fig. 2, the time-to-digital conversion circuit of the present embodiment may further include a plurality of buffer units 300, such as a register file. The input end of each buffer unit 300 is connected to the output end of the multipath ring oscillator 100, and the output end of each buffer unit 300 is connected to the input end of each signal processing unit 200 in a one-to-one correspondence manner, that is, each signal processing unit 200 is provided with one buffer unit 300 for data buffering and registering. Specifically, the shared multipath ring oscillator 100 generates a coarse-grained periodic signal required for measuring time and a logic level of each tap of a fine-grained delay unit, and then enters the corresponding signal processing unit 200 through the buffer unit 300 to perform corresponding time analysis and calculation, and finally outputs a time test value.
Further, each buffer unit 300 includes: a coarse-grain buffer 310 and a fine-grain buffer 320; the coarse-grain buffer 310 and the fine-grain buffer 320 are each connected to a respective signal processing unit 200, i.e. each signal processing unit 200 is provided with one coarse-grain buffer 310 and one fine-grain buffer 320.
Referring to fig. 2, the coarse-granularity buffer 310 receives the periodic signal of the multipath ring oscillator 100 and the corresponding first timing control signal a of the signal processing unit 200, and buffers the periodic signal according to the first timing control signal to obtain coarse-granularity time data. The fine-grained buffer 320 receives the encoded signal of the multipath ring oscillator 100 and the corresponding second timing control signal b of the signal processing unit 200, and buffers the encoded signal according to the second timing control signal to obtain fine-grained time data. Correspondingly, each signal processing unit 200 performs time calculation according to the coarse-grained time data and the fine-grained time data to obtain a corresponding time measurement value.
In one embodiment, the time-to-digital conversion circuit may further include an enable signal generation unit 400; the enable signal generation unit 400 is connected to the multipath ring oscillator 100.
The enable signal generation unit 400 generates an enable signal, which is transmitted to each multipath delay unit in the multipath ring oscillator 100, the multipath ring oscillator 100 operates when the enable signal is at a first level, and the multipath ring oscillator 100 stops operating when the enable signal is at a second level. Illustratively, when the enable signal is at a high level, the multipath ring oscillator 100 starts to operate, and when the enable signal is at a low level, the multipath ring oscillator 100 stops operating, so that stable operation of the multipath ring oscillator 100 is ensured, an accurate delay signal can be obtained, and accuracy of time measurement is further ensured.
The time-to-digital conversion circuit of the above embodiment includes the shared multipath ring oscillator 100, the buffer unit 300 of the output signal, and the plurality of signal processing units 200, and has a simple structure, thereby greatly reducing the size of the TDC array; the multi-path ring oscillator 100 may generate a periodic signal for coarse-grained timing and an encoded signal for fine-grained timing at the same time, and then each signal processing unit 200 obtains a corresponding time measurement value according to the periodic signal and the encoded signal, without configuring a separate coarse-grained timing unit and a separate fine-grained timing unit for each TDC, thereby obtaining accurate time and greatly reducing the size and power consumption of the TDC array.
Based on the time-to-digital conversion circuit of the above embodiment, the present embodiment further provides a time-to-digital conversion method, which includes:
a periodic signal for coarse-grained timing and an encoded signal for fine-grained timing are generated by a multi-path ring oscillator.
And each signal processing unit carries out time calculation according to the periodic signal and the coding signal to obtain a corresponding time measurement value.
Further, referring to fig. 2, each of the signal processing units performs time calculation according to the periodic signal and the encoded signal to obtain a corresponding time measurement value, including:
and buffering the periodic signal according to the first time sequence control signal generated by each signal processing unit to obtain coarse-grained time data corresponding to the signal processing units.
And buffering the coded signals according to the second time sequence control signals generated by each signal processing unit to obtain fine-grained time data corresponding to the signal processing units.
And each signal processing unit also carries out time calculation according to the coarse-grained time data and the fine-grained time data to obtain a corresponding time measurement value.
In the time-to-digital conversion method of the embodiment, the multi-path ring oscillator may generate the periodic signal for coarse-grained timing and the encoded signal for fine-grained timing at the same time, and then each signal processing unit obtains the corresponding time measurement value according to the periodic signal and the encoded signal, and does not need to configure a separate coarse-grained timing unit and a separate fine-grained timing unit for each TDC, so that the size and power consumption of the TDC array are greatly reduced while obtaining the accurate time.
The present embodiment also provides a time measuring apparatus, which includes the time-to-digital conversion circuit as described in any of the above embodiments, and also has any of the beneficial effects of the time-to-digital conversion circuit described above.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (10)
1. A time-to-digital conversion circuit, comprising: a multipath ring oscillator and a plurality of signal processing units; the plurality of signal processing units are all connected with the multipath ring oscillator;
the multipath ring oscillator is used for generating a periodic signal for coarse-grained timing and an encoded signal for fine-grained timing, and sending the periodic signal and the encoded signal to each signal processing unit;
each signal processing unit is used for carrying out time calculation according to the periodic signal and the coding signal to obtain a corresponding time measurement value.
2. The time-to-digital conversion circuit of claim 1, wherein the multipath ring oscillator comprises a plurality of multipath delay elements connected end-to-end; each multipath delay unit is also connected with one or more multipath delay units which are not adjacent to the multipath delay unit;
each multipath delay unit is used for receiving a delay signal of a multipath delay unit adjacent to the multipath delay unit and a delay signal from one or more multipath delay units which are not adjacent to the multipath delay unit;
the delayed signals pass through a plurality of multipath delay units to obtain the periodic signals and the coded signals, and the periodic signals and the coded signals are output to each signal processing unit.
3. The time-to-digital conversion circuit of claim 2, wherein the number of said multipath delay elements is determined according to time measurement accuracy requirements and/or chip processes employed.
4. The time-to-digital conversion circuit of claim 2, wherein each of the multipath delay cells comprises a plurality of cascaded inverters.
5. The time-to-digital conversion circuit of claim 2, further comprising an enable signal generation unit;
the enabling signal generating unit is used for generating an enabling signal and transmitting the enabling signal to each multipath delay unit; the multipath ring oscillator operates when the enable signal is at a first level and stops operating when the enable signal is at a second level.
6. The time-to-digital conversion circuit according to any one of claims 1 to 5, further comprising a plurality of buffer units; the input end of each buffer unit is connected with the output end of the multipath ring oscillator, and the output end of each buffer unit is correspondingly connected with the input end of each signal processing unit.
7. The time-to-digital conversion circuit of claim 6, wherein each of the buffer units comprises: a coarse-grained buffer and a fine-grained buffer; the coarse-grained buffer and the fine-grained buffer are both connected with the corresponding signal processing units;
the coarse-grained buffer is configured to receive the periodic signal of the multipath ring oscillator and a corresponding first timing control signal of the signal processing unit, and buffer the periodic signal according to the first timing control signal to obtain coarse-grained time data;
the fine-grained buffer is used for receiving the coded signal of the multipath ring oscillator and a second time sequence control signal of the corresponding signal processing unit, and buffering the coded signal according to the second time sequence control signal to obtain fine-grained time data;
each signal processing unit is used for carrying out time calculation according to the coarse-grained time data and the fine-grained time data to obtain a corresponding time measurement value.
8. A time-to-digital conversion method applied to a time-to-digital conversion circuit including a multipath ring oscillator and a plurality of signal processing units, comprising:
generating, by the multipath ring oscillator, a periodic signal for coarse grain timing and an encoded signal for fine grain timing;
and each signal processing unit carries out time calculation according to the periodic signal and the coding signal to obtain a corresponding time measurement value.
9. The time-to-digital conversion method of claim 8, wherein each of said signal processing units performs a time calculation based on said periodic signal and said encoded signal to obtain a corresponding time measurement, comprising:
buffering the periodic signal according to the first timing control signal generated by each signal processing unit to obtain coarse-grained time data corresponding to the signal processing units;
buffering the coded signals according to the second time sequence control signals generated by each signal processing unit to obtain fine-grained time data corresponding to the signal processing units;
and each signal processing unit also carries out time calculation according to the coarse-grained time data and the fine-grained time data to obtain a corresponding time measurement value.
10. A time measuring device comprising the time-to-digital conversion circuit according to any one of claims 1 to 7.
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