CN113261096A - Chip packaging structure - Google Patents

Chip packaging structure Download PDF

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Publication number
CN113261096A
CN113261096A CN201980013126.3A CN201980013126A CN113261096A CN 113261096 A CN113261096 A CN 113261096A CN 201980013126 A CN201980013126 A CN 201980013126A CN 113261096 A CN113261096 A CN 113261096A
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China
Prior art keywords
chip
protective layer
structure according
layer
protection layer
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CN201980013126.3A
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Chinese (zh)
Inventor
杨科
秦培
刘伟
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Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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Publication of CN113261096A publication Critical patent/CN113261096A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A chip packaging structure comprises a chip (1) and a first protective layer (2); the mechanical property of the first protective layer (2) is higher than that of the epoxy molding compound; the mechanical properties include one or both of elastic modulus and strength; the first protective layer (2) is arranged above the chip (1). This application can reduce the slight deformation that stress brought to a certain extent, stabilizes the operating frequency of chip (1), in addition, also can save the cost.

Description

Chip packaging structure Technical Field
The application relates to the field of chip packaging, in particular to a chip packaging structure.
Background
The unstable working frequency of the chip will affect the performance of the chip, if the working frequency of the chip is stabilized by the optimization of the material, the optimization of the material will cause the cost of the chip to increase, because the inherent property of the material limits, and the material can not be optimized unlimitedly to stabilize the working frequency of the chip; in addition, if the operating frequency of the chip is stabilized by optimizing the wafer process, a problem of cost increase is also caused.
Disclosure of Invention
Aiming at the problem of cost increase in the prior art of stabilizing the working frequency of a chip, the embodiment of the application provides a chip packaging structure, a method and application.
A first aspect of embodiments of the present application provides a chip packaging structure, including a chip and a first protection layer; the mechanical property of the first protective layer is higher than that of the epoxy molding compound; the mechanical properties include one or both of elastic modulus and strength; the first protection layer is arranged above the chip.
With reference to the first aspect, in an implementation manner of the first aspect, the protective layer further includes a second protective layer; the first protective layer is arranged on the upper surface of the second protective layer; the second protective layer covers the chip; the second protective layer includes an epoxy resin.
In addition, with reference to the first aspect and the foregoing implementation manner of the first aspect, in another implementation manner of the first aspect, the second protection layer is formed by dispensing or die-on-die film FOD.
In addition, with reference to the first aspect and the foregoing implementation manner of the first aspect, in another implementation manner of the first aspect, the first protection layer is further disposed around the chip.
In addition, with reference to the first aspect and the foregoing implementation manner of the first aspect, in another implementation manner of the first aspect, a third protective layer is further included; the third protective layer is arranged between the first protective layer and the chip; the third protective layer covers the chip.
In addition, with reference to the first aspect and the foregoing implementation manner of the first aspect, in another implementation manner of the first aspect, the mechanical property of the third protective layer is lower than that of the first protective layer.
In addition, with reference to the first aspect and the foregoing implementation manner of the first aspect, in another implementation manner of the first aspect, the third protective layer includes an epoxy resin or a gas.
In addition, with reference to the first aspect and the foregoing implementation manner of the first aspect, in another implementation manner of the first aspect, the first protection layer covers the chip.
In addition, with reference to the first aspect and the foregoing implementation manner of the first aspect, in another implementation manner of the first aspect, the first protection layer is formed by dispensing or die-coating a film FOD.
In addition, with reference to the first aspect and the foregoing implementation manner of the first aspect, in another implementation manner of the first aspect, the apparatus further includes a plastic package layer, and the plastic package layer covers the first protection layer or is disposed around the first protection layer.
In addition, with reference to the first aspect and the foregoing implementation manner of the first aspect, in another implementation manner of the first aspect, the elastic modulus of the first protection layer is higher than 30 Gpa.
In addition, with reference to the first aspect and the foregoing implementation manner of the first aspect, in another implementation manner of the first aspect, the elastic modulus of the first protection layer is higher than 50 Gpa.
In addition, with reference to the first aspect and the foregoing implementation manner of the first aspect, in another implementation manner of the first aspect, the strength of the first protection layer is higher than 150 Mpa.
In addition, with reference to the first aspect and the foregoing implementation manner of the first aspect, in another implementation manner of the first aspect, the strength of the first protection layer is higher than 210 MPa.
Additionally, with reference to the first aspect and the foregoing implementation manners of the first aspect, in another implementation manner of the first aspect, the first protection layer includes one or more metal materials, and the metal materials include iron, copper, aluminum, steel, tungsten, and molybdenum.
In addition, with reference to the first aspect and the foregoing implementation manner of the first aspect, in another implementation manner of the first aspect, the first protection layer includes one or more non-metallic materials, and the non-metallic materials include silicon and oxide.
In addition, with reference to the first aspect and the foregoing implementation manner of the first aspect, in another implementation manner of the first aspect, the chip is an MCU chip.
In addition, with reference to the first aspect and the foregoing implementation manner of the first aspect, in another implementation manner of the first aspect, the chip includes a clock circuit.
In addition, with reference to the first aspect and the foregoing implementation manner of the first aspect, in another implementation manner of the first aspect, the chip further includes a printed circuit hard board or a flexible circuit board, and the chip is disposed on the printed circuit hard board or the flexible circuit board.
Compared with the prior art, the beneficial effects of the embodiment of the application lie in that: the embodiment of the application provides a chip packaging structure, through set up first protective layer above the chip, the mechanical properties of first protective layer is higher than epoxy molding compound to mechanical properties is injectd to one or two in elastic modulus and intensity, in order to reach the purpose of stabilizing chip operating frequency, even introduce stress, because the existence of first protective layer, also can reduce the slight deformation that the stress brought to a certain extent, stabilize the operating frequency of chip, in addition, also can save cost.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a first structural diagram of a chip and a first protection layer according to an embodiment of the present disclosure;
fig. 2 is a second structural diagram of the chip and the first protective layer according to the embodiment of the disclosure;
FIG. 3 is a third structural diagram of the chip and the first passivation layer according to the embodiment of the present disclosure;
FIG. 4 is a first structural diagram of a first passivation layer and a molding layer according to an embodiment of the present disclosure;
FIG. 5 is a second structural diagram of the first passivation layer and the plastic sealing layer according to the embodiment of the disclosure;
FIG. 6 is a third structural diagram of the first passivation layer and the molding compound layer according to the embodiment of the present disclosure;
FIG. 7 is a fourth structural diagram of the first passivation layer and the molding compound layer according to the embodiment of the disclosure;
fig. 8 is a fifth structural diagram of the first protective layer and the molding compound layer according to the embodiment of the disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, some embodiments of the present application will be described in detail by way of example with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the examples, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.
The embodiment of the application provides a chip packaging structure for stabilizing the working frequency of a chip, as shown in fig. 1, 2 and 3, the chip packaging structure for stabilizing the working frequency of the chip comprises a chip 1 and a first protective layer 2, and the mechanical property of the first protective layer 2 is higher than that of an epoxy molding compound; in this embodiment, the epoxy molding compound may generally include a thermosetting resin, such as an epoxy resin, and may further include other fillers such as an additive, a curing agent, or a colorant. The mechanical properties include one or two of elastic modulus and strength, the mechanical properties can also be referred to as mechanical properties, the elastic modulus and strength of the epoxy molding compound are mentioned in the standard, generally, the elastic modulus of the epoxy molding compound can be 13Gpa, 14Gpa, 15Gpa and the like, and the strength can be 120Mpa, 130Mpa, 140Mpa, 150Mpa and the like, which are not described herein again. In this embodiment, the elastic modulus includes a tensile modulus and a flexural modulus, and the specific elastic modulus or elastic moduli may depend on the deformation form of the material, and may also be a compressive modulus, a shear modulus, a bulk modulus, and the like; in this embodiment, the strength refers to the maximum ability of the material to resist damage caused by external force (load), and the value is expressed by the force borne by the material per unit stressed area when the material is damaged by stress. The first protective layer 2 is disposed above the chip 1. In addition, the first protection layer 2 in this embodiment may be in direct contact with the chip 1, for example, as shown in fig. 1, the first protection layer 2 may cover the chip 1, and the covering in this embodiment refers to the first protection layer 2 being in contact with the chip; the first protective layer 2 in the present embodiment may not be in contact with the chip 1, for example, as shown in fig. 2 and 3. In addition, when the first protection layer 2 is disposed above the chip 1, the first protection layer 2 may be disposed entirely above the chip 1, that is, the first protection layer is not disposed around the chip 1; the first protection layer 2 may also be partially disposed above the chip 1, i.e. the first protection layer 2 is disposed both above the chip 1 and around the chip 1. The first protection layer 2 may be formed by mechanical stamping or other processes, which is not limited in this embodiment.
It should be noted that, the thickness of the first protection layer is not limited in this embodiment, and those skilled in the art can select the thickness of the first protection layer according to the requirement. Theoretically, the operating frequency of the chip or die (die) is affected by the internal capacitance value, and the related formula is: f is K1/(r c), where f is frequency, K is coefficient, r is resistance, and c is internal capacitance, so it can be understood that the operating frequency is affected by internal capacitance and resistance, where c is ∈ S/4 π kd, where ε is dielectric constant, S is plate facing area, K is electrostatic force constant, and d is plate distance, it can be seen that internal capacitance c is affected by plate distance, and plate distance is affected by deformation caused by stress, and chip may induce stress to cause fine deformation when packaging or using the chip.
The embodiment of the application provides a chip packaging structure for stabilizing the working frequency of a chip, the chip packaging structure can be applied to any chip needing to consider the working frequency, the type of the chip is not limited by the embodiment, the first protective layer is arranged above the chip, the mechanical property of the first protective layer is higher than that of an epoxy molding compound, and the mechanical property is limited to one or two of elastic modulus and strength, so that the purpose of stabilizing the working frequency of the chip is achieved, even if stress exists inevitably, due to the existence of the first protective layer, fine deformation caused by the stress can be reduced to a certain extent, the working frequency of the chip is stabilized, and in addition, the cost can be saved.
Based on the disclosure of the above embodiments, in the present embodiment, please refer to fig. 3, which further includes a second protection layer 4; the first protection layer 2 is disposed on the upper surface of the second protection layer 4, and the second protection layer 4 covers the chip 1, where the covering in this embodiment means that the first protection layer 2 is in contact with the chip. The first protective layer 2 may be partially provided on the upper surface of the second protective layer 4, or may be entirely provided on the upper surface of the second protective layer 4. In this embodiment, the second protective layer 4 is disposed between the first protective layer 2 and the chip 1, and the second protective layer 4 covers the chip 1, and the second protective layer 4 may include a resin material, such as an epoxy resin, and in addition, the second protective layer may further include other materials, such as a filler, a reinforcing agent, or a colorant, which is not limited in this embodiment. The scheme disclosed by the embodiment can further reduce the deformation of the chip caused by the stress, and further improve the working frequency of the chip.
Based on the disclosure of the above embodiment, in this embodiment, the second protection layer may be formed by dispensing or die-coating the film FOD (film over die), and compared with the molding process, the dispensing or FOD process does not require high temperature and high pressure requirements as the molding process, so that when the second protection layer covers the chip, the dispensing or FOD process is used to reduce the stress borne by the chip, and further stabilize the working frequency of the chip. It should be noted that, based on the disclosure of the above embodiments, in other embodiments, the second protection layer may be formed by other mounting processes besides FOD.
Based on the disclosure of the above embodiments, in this embodiment, please refer to fig. 1 and 2, the first protection layer 2 may also be disposed around the chip 1, and on this basis, if the die pressing or other packaging processes are performed subsequently or the chip is stressed during transportation and use, the stress on the chip 1 will be greatly reduced because the top and the periphery of the chip 1 are protected by the first protection layer 2, thereby further stabilizing the operating frequency of the chip 1.
Based on the disclosure of the above embodiments, in the present embodiment, please refer to fig. 2, further including a third passivation layer 5; the third protective layer 5 is arranged between the first protective layer 2 and the chip 1; the third protective layer 5 covers the chip 1. Set up third protective layer 5 between first protective layer 2 and chip 1, when external force was applyed in first protective layer 2, third protective layer 5 can play the effect of buffering to reduce the stress that chip 1 received, further stabilize the operating frequency of chip 1.
Based on the disclosure of the above embodiments, in this embodiment, both the second protective layer and the third protective layer may be referred to as an intermediate protective layer, that is, the intermediate protective layer includes the second protective layer or the third protective layer, and the intermediate protective layer covers the chip. In this embodiment, the second passivation layer covers the chip, and the first passivation layer is disposed on the upper surface of the second passivation layer, that is, the second passivation layer is also disposed between the first passivation layer and the chip, as is the third passivation layer.
Based on the disclosure of the above embodiments, in this embodiment, the mechanical property of the third passivation layer 5 is lower than that of the first passivation layer 2, so that the connection line 7 is convenient to fix or protect in the manufacturing process flow of the third passivation layer 5, it should be noted that the position of the connection line 7 in fig. 2 is only an exemplary illustration, and the position of the connection line 7 in this embodiment is not necessarily limited to the position shown in fig. 2, but may be in other positions.
Based on the disclosure of the above embodiment, in the present embodiment, as shown in fig. 2, the third protective layer 5 includes the epoxy resin or the gas; the third protection layer 5 may include a resin material, such as epoxy resin, when the third protection layer 5 includes epoxy resin, the epoxy resin may protect and fix the connection line 7, when the third protection layer is a gas, the gas between the first protection layer 2 and the chip 1 may largely act as a buffer stress, and when the first protection layer is subjected to a stress, the stress is generally not transmitted to the chip, so that the chip 1 may be hardly affected by the stress; in addition, when the first protective layer is a gas, the connecting wire 7 is placed in the gas, and thus the connecting wire 7 is protected to a certain extent. It should be noted that, in this embodiment, the type of the gas is not limited, and the gas may be air, vacuum, nitrogen, or an inert gas, and the gas may be a single component or a mixed component, and those skilled in the art may select the type of the gas based on an application scenario or a cost consideration, in addition, in this embodiment, the first protection layer 2 may be fixed on the substrate 3 by dispensing, and under a condition that the second protection layer includes epoxy resin, the first protection layer 2 may also be fixed on the second protection layer by dispensing, and this embodiment does not limit the fixing form of the first protection layer 2.
Based on the disclosure of the above embodiment, in this embodiment, as shown in fig. 1, the first protection layer 2 covers the chip 1, and the chip 1 is covered by the first protection layer with mechanical property higher than that of the epoxy molding compound, and the stress applied to the chip 1 will be greatly reduced, so as to further stabilize the working frequency of the chip 1.
Based on the disclosure of the above embodiments, in this embodiment, the first protection layer is implemented by dispensing or film-on-die FOD, and compared with the molding process, the dispensing or FOD process does not require high temperature and high pressure requirements as the molding process, so that when the first protection layer covers the chip, the dispensing or FOD process is used to reduce the stress borne by the chip and further stabilize the operating frequency of the chip.
Based on the disclosure of the above embodiment, in this embodiment, the package structure further includes a plastic package layer 6, where the plastic package layer 6 covers the first protection layer 2 or is disposed around the first protection layer 2. As shown in fig. 4-6, the plastic package layer 6 covers the first protection layer 2, and the covering in this embodiment means that the plastic package layer 6 is in contact with the first protection layer 2; as shown in fig. 7 and 8, the molding compound layer 6 may also be disposed around the first protection layer 2. On the basis of the first protective layer, the plastic packaging layer is added to further reduce the stress borne by the chip so as to stabilize the working frequency of the chip.
Based on the disclosure of the above embodiments, in this embodiment, when the elastic modulus of the first protection layer is higher than 30Gpa and the strain is smaller under the same stress action, the stress borne by the chip is advantageously reduced, and the operating frequency of the chip can be stabilized, for example, the first protection layer may use glass with an elastic modulus of 50-90Gpa, copper with an elastic modulus of about 117Gpa, silicon with an elastic modulus of about 185Gpa, iron with an elastic modulus of about 200Gpa, or the like.
Based on the disclosure of the above embodiments, in this embodiment, the elastic modulus of the first protection layer may also be higher than 50 Gpa.
Based on the disclosure of the above embodiments, in this embodiment, under the condition that the loaded area is fixed, the greater the strength of the material is, the greater the breaking load is, and the strength of the first protection layer is higher than 150Mpa, which is beneficial to further reducing the stress borne by the chip to stabilize the working frequency of the chip, for example, the first protection layer may use a steel material with a strength of 200-.
Based on the disclosure of the above embodiments, in the present embodiment, the strength of the first protection layer may also be higher than 210 MPa. In addition, in other embodiments, the strength of the first protective layer may also be higher than 300 MPa.
Based on the disclosure of the above embodiments, in this embodiment, the first protection layer includes one or more metal materials, and the metal materials include iron, copper, aluminum, steel, tungsten, molybdenum, and the like, and the first protection layer in this embodiment may also use alloy materials, for example, copper alloy, aluminum alloy, and the like, and the mechanical properties of the metal materials are generally better, and if the first protection layer is made of one or more metal materials, it is beneficial to further reduce the stress borne by the chip, so as to stabilize the operating frequency of the chip.
Based on the disclosure of the above embodiments, in the present embodiment, the first protection layer includes one or more non-metal materials, and the non-metal materials include silicon, oxide, and the like. The first protective layer may also be a glass material or a ceramic material containing silicon, and if the first protective layer is made of one or more non-metallic materials with better mechanical properties, it is beneficial to further reduce the stress borne by the chip to stabilize the working frequency of the chip.
Based on the disclosure of the above embodiment, in this embodiment, the chip 1 may be an MCU chip, and for chips with higher requirement on stability of operating frequency, such as MCU chips and CPU chips, a chip package structure for stabilizing the operating frequency of the chip is used, so as to stabilize the operating frequency of the chip and improve the performance of the chip.
Based on the disclosure of the above embodiments, in this embodiment, the chip 1 may further include a clock circuit, the clock circuit is generally used to generate a clock signal with a predetermined frequency, and the stabilization of the operating frequency is particularly important for a chip having the clock circuit. In addition, for a circuit with a capacitive element, the capacitance value of the capacitive element has influence on the operating frequency, so that a chip comprising the capacitive element can also play a role in stabilizing the operating frequency by using the scheme, such as a filter chip and the like.
Based on the disclosure of the above embodiments, in this embodiment, please refer to fig. 1 to 8, further including a substrate 3, where the chip 1 is disposed on the substrate 3, the substrate may be a flexible circuit board or a printed circuit board, and the substrate may provide electrical connection, protection, support, and the like for the chip, and in addition, the substrate 3 may also be other chip carriers, which is not limited in this embodiment, and the first protection layer 2 may be in contact with the substrate or not in contact with the substrate. As shown in fig. 2, when the first passivation layer 2 contacts the substrate, the first passivation layer 2 may be connected to the substrate by dispensing, or other connection methods, which is not limited in this embodiment.
It should be understood that in the embodiment of the present application, "B corresponding to a" means that B is associated with a, from which B can be determined. It should also be understood that determining B from a does not mean determining B from a alone, but may be determined from a and/or other information.
In addition, the term "and/or" herein is only one kind of association relationship describing an associated object, and means that there may be three kinds of relationships, for example, a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (19)

  1. A chip packaging structure is characterized by comprising a chip and a first protective layer;
    the mechanical property of the first protective layer is higher than that of the epoxy molding compound; the mechanical properties include one or both of modulus of elasticity and strength;
    the first protective layer is arranged above the chip.
  2. The chip package structure according to claim 1, further comprising a second protective layer;
    the first protective layer is arranged on the upper surface of the second protective layer;
    the second protective layer coats the chip;
    the second protective layer includes an epoxy resin.
  3. The chip package structure according to claim 2, wherein the second protection layer is formed by dispensing or die-on-film FOD.
  4. The chip package structure according to claim 1, wherein the first protection layer is further disposed around the chip.
  5. The chip package structure according to claim 4, further comprising a third protective layer;
    the third protective layer is arranged between the first protective layer and the chip;
    the third protective layer covers the chip.
  6. The chip packaging structure according to claim 5, wherein the mechanical property of the third protective layer is lower than the mechanical property of the first protective layer.
  7. The chip package structure according to claim 5, wherein the third protective layer comprises an epoxy or a gas.
  8. The chip package structure according to claim 4, wherein the first protection layer covers the chip.
  9. The chip package structure according to claim 8, wherein the first protection layer is formed by dispensing or Film On Die (FOD).
  10. The chip packaging structure according to any one of claims 1 to 9, further comprising a molding compound layer, wherein the molding compound layer covers the first protection layer or is disposed around the first protection layer.
  11. The chip packaging structure according to any one of claims 1 to 10, wherein the elastic modulus of the first protective layer is higher than 30 Gpa.
  12. The chip package structure according to claim 11, wherein the elastic modulus of the first protective layer is higher than 50 GPa.
  13. The chip packaging structure according to any one of claims 1 to 12, wherein the strength of the first protective layer is higher than 150 Mpa.
  14. The chip packaging structure according to claim 13, wherein the strength of the first protective layer is higher than 210 MPa.
  15. The chip package structure according to any one of claims 1 to 14, wherein the first protective layer comprises one or more metallic materials comprising iron, copper, aluminum, steel, tungsten, molybdenum.
  16. The chip package structure according to any one of claims 1 to 14, wherein the first protection layer comprises one or more non-metallic materials, and the non-metallic materials comprise silicon and oxide.
  17. The chip packaging structure according to any one of claims 1 to 16, wherein the chip is an MCU chip.
  18. The chip packaging structure according to any one of claims 1 to 17, wherein the chip comprises a clock circuit.
  19. The chip packaging structure according to any one of claims 1 to 18, further comprising a printed circuit board or a flexible circuit board, the chip being disposed on the printed circuit board or the flexible circuit board.
CN201980013126.3A 2019-12-13 2019-12-13 Chip packaging structure Pending CN113261096A (en)

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PCT/CN2019/125078 WO2021114213A1 (en) 2019-12-13 2019-12-13 Chip packaging structure

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CN115102513B (en) * 2022-08-25 2022-12-09 广东大普通信技术股份有限公司 Clock chip and packaging method thereof

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