CN100382291C - Semiconductor device and making method thereof - Google Patents
Semiconductor device and making method thereof Download PDFInfo
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- CN100382291C CN100382291C CNB2005100709080A CN200510070908A CN100382291C CN 100382291 C CN100382291 C CN 100382291C CN B2005100709080 A CNB2005100709080 A CN B2005100709080A CN 200510070908 A CN200510070908 A CN 200510070908A CN 100382291 C CN100382291 C CN 100382291C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/14104—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to a semiconductor device and a making method thereof. The semiconductor device comprises semiconductor base materials, a first and a second protective layers, a metal layer, a third protective layer, openings and welding lugs, wherein the semiconductor base materials are provided with welding pads; the first and the second protective layers are orderly stacked on the semiconductor base materials, and the welding pads are exposed; the second protective layer is combined at the welding pads; the periphery of the welding pads is locally covered with the second protective layer; the second protective layer and local part of the metal layer are covered with the third protective layer. The local part of the metal layer is exposed by the openings; the space between the center of the openings and the center deviation of the welding pads is smaller than the radius of the welding pads; the welding lugs are combined on the metal layer which is exposed by the openings. The present invention can prevent the phenomena that the welding lugs are cracked, or metals at the base layer of the welding lugs are disengaged from the base layer; the present invention can be applied to chips of low dielectric constant; the present invention has the advantages of simple structure and making process, and low manufacturing cost; the procedure is simplified by the present invention, and heavy configuration procedure does not need, so the problem of reserving capacitance can not happen, and the defects in the prior art are overcome by the present invention.
Description
Technical field
The invention relates to a kind of semiconductor packaging, particularly about a kind of semiconductor device and method for making thereof of low-k.
Background technology
Along with the progress of semiconductor technology and improving constantly of chip circuit function, be accompanied by increasing substantially of various portable (Portable) products such as communication, network and computer, can dwindle integrated circuit (IC) area and have high density and the spherical grid array type of multitube pin characteristic (BGA), flip-chip (Flip Chip) have become main flow with wafer-level package semiconductor packagings such as (CSP, Chip Size Package).
Wherein, flip-chip (Flip Chip) semiconductor packaging is for example to go up at the contact (normally weld pad) of semiconductor substrates such as wafer or chip to form solder projection (Solder Bump), directly electrically connect by solder projection again with for example substrate (Substrate) equivalent-load spare, compare with wire bond (Wire Bonding) mode, the circuit paths of flip chip technology (fct) is shorter, has electrical quality preferably, simultaneously can be designed to chip back naked form, therefore the chip cooling that can improve.For these reasons, make the flip chip technology (fct) widespread usage in the semiconductor packages industry.
Above-mentioned flip chip technology (fct) before semiconductor substrate forms solder projection, as the 6th, 111, No. 321, the 6th, 229, No. 220, the 6th, 107, No. 180 and the 6th, wait for 586, No. 323 and disclosed in the United States Patent (USP), need to form earlier welding block underlying metal (Under Bump Metallurgy; UBM), this solder projection can be bonded on the semiconductor substrate securely.Yet, when the solder projection that utilizes this semiconductor substrate during directly with the substrate electric connection, the stress that produces because of thermal expansion coefficient difference (CTE mismatch) between semiconductor substrate and the substrate, be concentrated on the solder projection and welding block underlying metal (UBM) on, cause the be full of cracks (crack) or the delamination of solder projection, welding block underlying metal easily, influence electrical quality.In order to improve above-mentioned be full of cracks or delamination problems, existing way is as the 5th, 720, No. 100, the 6th, 074, No. 895 and the 6th, 372, No. 544 United States Patent (USP) is described, fill glue-line (Under fill) and alleviate, cushion stress between the semiconductor substrate of for example chip and substrate, but this step is not only consuming time and difficult repetition.
Another way that repeats sheath (Re-Passivation) is before forming the welding block underlying metal, is pre-formed for example to be phenylpropyl alcohol cyclobutane (Benzo-Cyclo-Butene on protective layer; BCB), the dielectric layer of polyimides (polyimide), absorb stress by this dielectric layer, reduce above-mentioned be full of cracks or delamination problems, this process is shown in Figure 1A to Fig. 1 E.
At first shown in Figure 1A, the semiconductor substrate 10 of (the I/O contact) 11 that have a plurality of weld pads is provided, and forms the local protective layers 12 that expose each weld pad 11 on these semiconductor substrate 10 surfaces.Among each figure all the single weld pad 11 with semiconductor substrate 10 parts be the example explanation.Then shown in Figure 1B, forming in these protective layer 12 surface coverage for example is polyimides (Polyimide, dielectric layer 13 PI), and local this weld pad 11 that exposes.Then shown in Fig. 1 C, for example adopt sputter technology (Sputtering) and electroplating technology (Plating) form a welding block underlying metal (UBM) 14 on this weld pad 11.Afterwards, will for example be that the layer 15 of refusing of dry film (Dry Film) covers on this dielectric layer 13 shown in Fig. 1 D, and expose this welding block underlying metal 14 with coating scolder 16.At last, through the reflow first time (Reflow), remove and refuse layer 15 and reflow for the second time, make scolder 16 form the solder projection (Solder Ball) 17 of spheroidization shown in Fig. 1 E.
Above-mentionedly absorbing the technology of stress by set up dielectric layer 13 between welding block underlying metal 14 and protective layer 12, is more than 0.13 micron the time in the semiconductor process techniques level in live width, can reduce be full of cracks or delamination problems really.Yet, below live width is 90 nanometers (nm) even during the technology of 65 nanometers, 45 nanometers, 32 nanometers, dwindle the resistance time delay (RC Time Delay) that causes in order to overcome live width, must import the dielectric layer material of low-k (Low k), can closely press close to mutually to allow the plain conductor in the chip, and prevent the problem of signal leakage and interference, and improve transmission rate relatively.Along with low-k (Low k) requirement of these dielectric layer material, related hard, the easy crisp characteristic of dielectric layer material matter that derives easily causes the delamination of dielectric layer all the better, influences the electrical quality of product.This mainly is because be formed on the interface that the stress overwhelming majority on the solder projection 17 still acts on welding block underlying metal 14, the dielectric layer 13 that is positioned at its base side only provides local lateral force, can't provide enough pooling features, so the be full of cracks of solder projection 17 or the delamination of welding block underlying metal 14 still easily take place.
For this reason, the 6th, 492, No. 198, the 6th, 287, No. 893, the 6th, 455, wait for No. 408 United States Patent (USP) to develop circuit to reconfigure technology, overcome the be full of cracks of above-mentioned solder projection or the delamination problems of welding block underlying metal, i.e. a layer (Re-Distribution Layer reshuffled in utilization; RDL) form the conducting circuit,, reconfigure to suitable position and form the welding block underlying metal again chip contact originally.This is reshuffled the solder projection below that the operation technology disposed and has a dielectric layer, utilizes this dielectric layer that to a certain degree buffering effect can be provided the stress of solder projection, reduces problems such as be full of cracks or delamination.Yet, uses and to reshuffle complexity, difficulty and the cost that operation can significantly increase operation, and the plain conductor of reshuffling also caused the problem of many parasitic capacitances, thus influenced chip electrically.
Therefore, how to develop a kind of semiconductor device and method for making thereof that can solve above-mentioned prior art shortcoming, can reduce solder projection stress, prevent to chap with delamination, simplify working process, prevent to produce parasitic capacitance, do not use the technology of reshuffling operation, be applied in the low-k chip, real is the problem of being badly in need of solution at present.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, main purpose of the present invention is providing a kind of semiconductor device and method for making thereof that can reduce the stress of solder projection.
A time purpose of the present invention be to provide a kind of operation simply, semiconductor device and method for making thereof cheaply.
Another object of the present invention is to provide a kind of semiconductor device and method for making thereof that can not produce parasitic capacitance problems.
An also purpose of the present invention is to provide a kind of semiconductor device and method for making thereof of reshuffling operation of not using.
A further object of the present invention is to provide a kind of semiconductor device and method for making thereof that prevents to chap with delamination.
Another purpose of the present invention is to provide a kind of semiconductor device and method for making thereof that is applied in the low-k chip.
For achieving the above object and other purpose, the invention provides a kind of semiconductor device, this device comprises at least: the semiconductor substrate with weld pad; First, second protective layer stacks gradually on this semiconductor substrate, and exposes this weld pad; Metal level is combined in this weld pad and covers its this local second protective layer on every side; The 3rd protective layer covers this second protective layer and this local metal level, have the local opening that exposes this metal level, and the spacing of this open centre and this weld pad misalignment is less than the weld pad radius; And solder projection, be combined on the metal level that this opening exposes.
For reaching identical purpose, the present invention also can provide another kind of semiconductor device, and this device comprises at least: the semiconductor substrate with weld pad; First, second protective layer stacks gradually on this semiconductor substrate, and exposes this weld pad; The first metal layer is combined in this weld pad and covers its this local second protective layer on every side; The 3rd protective layer covers this second protective layer and this local the first metal layer, have the local opening that exposes this first metal layer, and the spacing of this open centre and this weld pad misalignment is less than the weld pad radius; Second metal level is combined in this first metal layer and covers its 3rd local protective layer on every side; And solder projection, be combined on this second metal level.
Above-mentioned gap length be between the weld pad radius to the weld pad radius 1/3rd between.This gap length is preferably in 1/2nd of weld pad radius.Applied semiconductor substrate can be the semiconductor chip or the wafer of low-k.
This first protective layer can be a silicon nitride layer.This second protective layer can be phenylpropyl alcohol cyclobutane (Benzo-Cyclo-Butene; BCB) or polyimides (Polyimide) dielectric layer.The 3rd protective layer can be dielectric layer or refuses layer.This dielectric layer is phenylpropyl alcohol cyclobutane or polyimides preferably.This metal level or first, second metal level can be welding block underlying metal (UBM), for example comprise the combination of metallic aluminium, nickel-vanadium alloy, metallic copper and Titanium.
For realizing above-mentioned semiconductor device, the method for making that the invention provides a kind of semiconductor device comprises: the semiconductor substrate with weld pad is provided; On this semiconductor substrate, form first, second protective layer successively, and expose this weld pad; One metal level is combined in this weld pad and covers its this local second protective layer on every side; The 3rd protective layer is covered this second protective layer and this local metal level, and define an opening and expose this metal level, and the spacing of this open centre and this weld pad misalignment is less than the weld pad radius with the part; And on the metal level of this opening exposure, form a solder projection.
Comprise in the step that forms solder projection on this metal level: on the 3rd protective layer, cover one deck and refuse layer, and corresponding this opening that exposes; In this opening, insert scolder and carry out the reflow first time; Removing this refuses layer and carries out the reflow second time to form solder projection.This scolder is preferably inserted in the opening with mode of printing.
For realizing above-mentioned semiconductor device, the present invention also provides the method for making of another kind of semiconductor device, and this method for making comprises: the semiconductor substrate with weld pad is provided; On this semiconductor substrate, form first, second protective layer successively, and expose this weld pad; The first metal layer is combined in this weld pad and covers its this local second protective layer on every side; The 3rd protective layer is covered on this second protective layer and local this first metal layer, and define an opening and expose this first metal layer, and the spacing of this open centre and this weld pad misalignment is less than the weld pad radius with the part; On this first metal layer in conjunction with second metal level and cover the 3rd local around it protective layer; And on this second metal level, form a solder projection.
The step that should form solder projection on this second metal level comprises: cover one deck and refuse layer on the 3rd protective layer; Defining this refuses layer and exposes this opening with correspondence; In this opening, form scolder; Remove this and refuse layer and remove, and carry out reflow to form solder projection not by this second metal level that scolder covered.This scolder preferably is formed in this opening with plating mode.
In sum; semiconductor device provided by the invention and method for making thereof mainly are between the metal level of solder projection and for example welding block underlying metal (UBM); be pre-formed the 3rd protective layer with opening; utilize this metal level of the local exposure of this opening, and the spacing of this open centre and this weld pad misalignment is less than the weld pad radius.The location-appropriate that makes solder projection be combined on this metal level whereby is offset; be positioned at relatively on the bigger protective layer of area; be meant second protective layer especially; and then provide buffering effect preferably to concentrate on the stress of solder projection with minimizing; therefore the present invention can prevent as welding block be full of cracks or welding block underlying metal delamination, and can be applicable to the chip of low-k.In addition,, simplified operation relatively and reduced manufacturing cost, need not use and reshuffle (RDL) operation, therefore also can not produce the problem of parasitic capacitance, therefore overcome the various shortcoming of above-mentioned prior art because structure of the present invention and operation are simple.
Description of drawings
Figure 1A to Fig. 1 E is the operation schematic diagram of existing semiconductor device;
Fig. 2 A to Fig. 2 F is the operation schematic diagram of semiconductor device embodiment 1 of the present invention; And
Fig. 3 A to Fig. 3 G is the operation schematic diagram of semiconductor device embodiment 2 of the present invention.
Embodiment
Embodiment 1
Fig. 2 F is the schematic diagram of semiconductor device of the present invention.As shown in the figure, this semiconductor device comprises at least: semiconductor substrate 20, first protective layer 22, second protective layer 23, metal level 24, the 3rd protective layer 25 and solder projection 281.
This semiconductor substrate 20 mainly is a silicon base material, and for example low-k (Low k) semiconductor chip or comprise the wafer of a plurality of chip units has a plurality of weld pads 21 (the zone explanation of only being contained with single weld pad 21 among the figure) on its acting surface.At these semiconductor substrate 20 surface coverage first protective layers (Passivation Layer) 22, and also this weld pad 21 of cover part of this first protective layer 22.The material of this first protective layer 22 can be a nitride, and for example a silicon nitride layer is used to protect this semiconductor substrate 20 and part of solder pads 21.
This second protective layer 23 covers on this first protective layer 22, and corresponding this weld pad 21 that exposes.This second protective layer 23 can be phenylpropyl alcohol cyclobutane (Benzo-Cyclo-Butene; BCB) or polyimides (Polyimide), but not as limit.
This metal level 24 is incorporated into this weld pad 21, and comprises this local second protective layer 23 of this weld pad 21 of covering on every side.This metal level 24 for example is welding block underlying metal (UBM), can be selected from the combination that comprises metallic aluminium, nickel-vanadium alloy, metallic copper and Titanium, but not as limit.
The 3rd protective layer 25 covers this second protective layer 23 and this local metal level 24, and it has the local opening 26 that exposes this metal level 24, and the interval S of these opening 26 centers and this weld pad 21 misalignments is less than weld pad 21 radiuses.Show among the figure that this interval S equals 1/2nd of these weld pad 21 radiuses, but be not as limit, the interval S length of all skews between weld pad 21 radiuses 1/3rd, all belongs to enforceable scope between weld pad 21 radiuses, this gap length S preferably weld pad 21 radiuses 1/2nd.The 3rd protective layer 25 is dielectric layers or refuses layer (Solder Mask), and this dielectric layer can be phenylpropyl alcohol cyclobutane (BCB) or polyimides (PI), but not as limit.
This solder projection 281 is combined on the metal level 24 of these opening 26 exposures, and the material of this solder projection 281 for example is a leypewter.
Because semiconductor device of the present invention is to be pre-formed the 3rd protective layer 25 with opening 26 between solder projection 28 and metal level 24; utilize this opening 26 local these metal levels 24 of exposure, and the interval S of these opening 26 centers and this weld pad 21 misalignments is less than weld pad 21 radiuses.The location-appropriate that can make solder projection 281 be combined on this metal level 24 whereby is offset; be positioned at relatively on the larger area protective layer; be meant second protective layer 23 especially; and then can borrow this second protective layer 23 that buffering effect preferably is provided; reduce the stress that concentrates on solder projection; therefore can prevent existing welding block be full of cracks or welding block underlying metal delamination, can be applicable to the chip of low-k.
Below cooperate Fig. 2 A to Fig. 2 F to describe the method for making of semiconductor device of the present invention in detail.
At first, shown in Fig. 2 A, prepare a semiconductor substrate 20 with a plurality of weld pads 21 (the zone explanation of only being contained among the figure) in advance, for example low-k (Low k) semiconductor chip or comprise the wafer of multicore blade unit with single weld pad 21.Also form first protective layer 22 on these semiconductor substrate 20 surfaces, and also this weld pad 21 of cover part of this first protective layer 22.The material of this first protective layer 22 can be a nitride, is a silicon nitride layer for example, is used to protect this semiconductor substrate 20 and part of solder pads 21.
Then shown in Fig. 2 B, on this first protective layer 22, form second protective layer 23, and corresponding this weld pad 21 that exposes.This second protective layer 23 can be phenylpropyl alcohol cyclobutane (BCB) or polyimides (PI), but not as limit.On address aftermentioned and make in the step, can adopt technology such as for example etching, deposition, patterning, these technology are semiconductor and make common technology in the technology, are no longer narrated, only so that main manufacture methods of the present invention to be described.
Then, shown in Fig. 2 C, on this weld pad 21,, this metal level 24 is comprised cover this local second protective layer 23 of this weld pad 21 on every side in conjunction with a metal level 24.This metal level 24 for example is welding block underlying metal (UBM), can be selected from the combination that comprises metallic aluminium, nickel-vanadium alloy, metallic copper and Titanium, but not as limit.
Then, shown in Fig. 2 D, the 3rd protective layer 25 is covered this second protective layer 23 and this local metal level 24, and defines an opening 26, locally expose this metal level 24, and these opening 26 centers and this weld pad 21 centers depart from interval S less than weld pad 21 radiuses.This shown interval S equals 1/2nd of these weld pad 21 radiuses among the figure, but be not as limit, all its skew interval S length between weld pad 1/21st 3 radius, all belong to enforceable scope between weld pad 21 radiuses, this gap length S preferably weld pad 21 radiuses 1/2nd.The 3rd protective layer 25 can be selected from dielectric layer or refuse layer (Solder Mask), and this dielectric layer can be phenylpropyl alcohol cyclobutane (BCB) or polyimides (PI), but not as limit.
Afterwards; shown in Fig. 2 E; on the 3rd protective layer 25, cover one deck and for example refuse layer 27 for dry film (Dry Film); and corresponding this opening 26 that exposes; then in this opening 26, insert the scolder 28 of leypewter for example; and carry out the reflow first time, scolder 28 and this metal level 24 are combined closely.
At last, shown in Fig. 2 F, remove this and refuse layer 27 and carry out the reflow second time, make this scolder 27 form the solder projection 281 of spheroidization.The scolder 28 of present embodiment is to adopt printing process to insert in the opening 26, but also can use the operation of electroplating deposition.
Though present embodiment is to be that example describes to distinguish the 3rd protective layer 25 with the step of refusing layer 27; but will be appreciated that; also can and refuse layer 27 and be incorporated into same process, just replace the 3rd protective layer 25 and refuse layer 27 with a layer of refusing that has defined opening with the 3rd protective layer 25.Therefore, the 3rd protective layer 25 also can be to refuse layer.
Owing to the invention provides the method for making of semiconductor device; compare with existing sheath (Re-Passivation) technology that repeats; the present invention only needs by the definition position that forms the 3rd protective layer 25 hour offset openings; can overcome the be full of cracks or the delamination of prior art, and can be applicable to the chip of low-k.In addition, compare with reshuffling (RDL) operation, operation of the present invention is then more simplified and is easy to implement, has simplified operation relatively and has reduced manufacturing cost, and reshuffled (RDL) operation owing to need not use, therefore also can not produce the problem of parasitic capacitance.
Embodiment 2
See also Fig. 3 G, the semiconductor device of present embodiment 2 comprises at least: semiconductor substrate 30, first protective layer 32, second protective layer 33, the first metal layer 34, the 3rd protective layer 35, second metal level 37 and solder projection 391.Compare with the foregoing description 1, present embodiment is to form this solder projection 391 with plating mode, has therefore increased one deck second metal level 37, and all the other structures are all identical with embodiment 1, therefore no longer repeats to give unnecessary details.
In the present embodiment 2, these opening 36 centers and this weld pad 31 centers are that the interval S that departs from is less than weld pad 21 radiuses equally.Can make the location-appropriate skew of solder projection 391 whereby with respect to this first metal layer 34; therefore can be positioned on the larger area protective layer; be meant second protective layer 33 especially; and then can borrow this second protective layer 33 that buffering effect preferably is provided; reduce the stress that concentrates on solder projection; therefore can prevent for example welding block be full of cracks or welding block underlying metal delamination, but and better application at the chip of low-k.
Below cooperate Fig. 3 A to Fig. 3 G to describe the method for making of semiconductor device of the present invention in detail.The no longer repeat specification of the same section of technology of being used and material and embodiment 1 is with the content of simplified illustration book.
At first, as shown in Figure 3A, preparation in advance has the semiconductor substrate 30 (the zone explanation of only being contained with single weld pad 31 among the figure) of a plurality of weld pads 31, and also forms first protective layer 32 on these semiconductor substrate 30 surfaces.
Then shown in Fig. 3 B, on this first protective layer 32, form second protective layer 33, and corresponding this weld pad 31 that exposes.
Then, shown in Fig. 3 C, on this weld pad 31,, make this first metal layer 34 cover this weld pad 31 and this local second protective layer 33 on every side in conjunction with the first metal layer 34.
Then; shown in Fig. 3 D; the 3rd protective layer 35 is covered this second protective layer 33 and this local the first metal layer 34, and define an opening 36 and expose this first metal layer 34, and the interval S of these opening 36 centers and this weld pad 31 misalignments is less than weld pad 31 radiuses with the part.This shown interval S equals 1/2nd of these weld pad 31 radiuses equally among the figure, but be not as limit, the interval S length of all skews between weld pad 31 radiuses to weld pad 31 radiuses 1/3rd between, all belong to enforceable scope, this gap length S preferably weld pad 31 radiuses 1/2nd.
Afterwards, shown in Fig. 3 E, on this first metal layer 34,, provide the conductive path of follow-up electroplating work procedure, and this second metal level 37 covers its 3rd local protective layer 35 on every side in conjunction with second metal level 37.
Then; shown in Fig. 3 F figure, on the 3rd protective layer 35, cover one deck and for example be photoresistance (Photoresist, PR) refuse layer 38; and define this and refuse layer 38 and expose this opening 36 with correspondence, then electroplating deposition for example is the scolder 39 of leypewter in this opening 36.
Then, remove this and refuse layer 38 and be the etching that light shield carries out second metal level 37, second metal level 37 is not removed by the part that scolder 39 covers with this scolder 39.At last, shown in Fig. 3 G, carry out reflow, make this scolder 39 form the solder projection 391 of spheroidization.The scolder 39 of present embodiment 2 is to deposit in the opening 36 with plating mode, but also can use printing process that scolder 39 is inserted in this opening 36.
By above-mentioned two embodiment as can be known; because semiconductor device of the present invention; can borrow the opening of the 3rd protective layer to depart from; make solder projection be positioned at relatively on the bigger protective layer of area; and then provide buffering effect preferably; reduce the stress that concentrates on solder projection, therefore can prevent existing welding block be full of cracks or welding block underlying metal delamination, and can be applicable to the chip of low-k.The invention provides the method for making of semiconductor device, compare, only need to overcome the be full of cracks or the delamination of prior art by the definition position that forms the 3rd protective layer 25 hour offset openings with the existing technology that repeats sheath (Re-Passivation); Compare with reshuffling (RDL) operation, operation of the present invention is then more simplified and is easy to implement, has simplified operation relatively and has reduced manufacturing cost, and reshuffled (RDL) operation owing to need not use, also can therefore not produce the problem of parasitic capacitance.Hence one can see that, and semiconductor device of the present invention and method for making thereof can solve the various shortcoming of prior art, and have above-mentioned multiple essence effect enhancement and high industrial utilization concurrently.
Claims (50)
1. a semiconductor device is characterized in that, this device comprises at least:
Semiconductor substrate with weld pad;
First, second protective layer stacks gradually on this semiconductor substrate, and exposes this weld pad;
Metal level is combined in this weld pad and covers its this local second protective layer on every side;
The 3rd protective layer covers this second protective layer and this local metal level, have the local opening that exposes this metal level, and the spacing of this open centre and this weld pad misalignment is less than the weld pad radius; And
Solder projection is combined on the metal level that this opening exposes.
2. semiconductor device as claimed in claim 1 is characterized in that, this gap length between the weld pad radius to the weld pad radius 1/3rd between.
3. semiconductor device as claimed in claim 1 is characterized in that, this gap length is 1/2nd of a weld pad radius.
4. semiconductor device as claimed in claim 1 is characterized in that, this semiconductor substrate is the semiconductor chip of low-k.
5. semiconductor device as claimed in claim 1 is characterized in that, this semiconductor substrate is the wafer of low-k.
6. semiconductor device as claimed in claim 1 is characterized in that, this first protective layer is a silicon nitride layer.
7. semiconductor device as claimed in claim 1 is characterized in that, this second protective layer is phenylpropyl alcohol cyclobutane or polymide dielectric layer.
8. semiconductor device as claimed in claim 1 is characterized in that, the 3rd protective layer is dielectric layer or refuses layer.
9. semiconductor device as claimed in claim 8 is characterized in that, this dielectric layer is phenylpropyl alcohol cyclobutane or polyimides.
10. semiconductor device as claimed in claim 1 is characterized in that, this metal level is a welding block underlying metal.
11. semiconductor device as claimed in claim 1 is characterized in that, this metal level comprises the combination of metallic aluminium, nickel-vanadium alloy, metallic copper and Titanium.
12. a semiconductor device is characterized in that, this device comprises at least:
Semiconductor substrate with weld pad;
First, second protective layer stacks gradually on this semiconductor substrate, and exposes this weld pad;
The first metal layer is combined in this weld pad and covers its this local second protective layer on every side;
The 3rd protective layer covers this second protective layer and this local the first metal layer, have the local opening that exposes this first metal layer, and the spacing of this open centre and this weld pad misalignment is less than the weld pad radius;
Second metal level is combined in this first metal layer and covers its 3rd local protective layer on every side; And
Solder projection is combined on this second metal level.
13. semiconductor device as claimed in claim 12 is characterized in that, this gap length between the weld pad radius to the weld pad radius 1/3rd between.
14. semiconductor device as claimed in claim 12 is characterized in that, this gap length is 1/2nd of a weld pad radius.
15. semiconductor device as claimed in claim 12 is characterized in that, this semiconductor substrate is the semiconductor chip of low-k.
16. semiconductor device as claimed in claim 12 is characterized in that, this semiconductor substrate is the wafer of low-k.
17. semiconductor device as claimed in claim 12 is characterized in that, this first protective layer is a silicon nitride layer.
18. semiconductor device as claimed in claim 12 is characterized in that, this second protective layer is phenylpropyl alcohol cyclobutane or polymide dielectric layer.
19. semiconductor device as claimed in claim 12 is characterized in that, the 3rd protective layer is dielectric layer or refuses layer.
20. semiconductor device as claimed in claim 19 is characterized in that, this dielectric layer is phenylpropyl alcohol cyclobutane or polyimides.
21. semiconductor device as claimed in claim 12 is characterized in that, this first, second metal level is the welding block underlying metal.
22. semiconductor device as claimed in claim 12 is characterized in that, this first, second metal level comprises the combination of metallic aluminium, nickel-vanadium alloy, metallic copper and Titanium respectively.
23. the method for making of a semiconductor device is characterized in that, this method for making comprises:
Semiconductor substrate with weld pad is provided;
On this semiconductor substrate, form first, second protective layer successively, and expose this weld pad;
One metal level is combined in this weld pad and covers its this local second protective layer on every side;
The 3rd protective layer is covered this second protective layer and this local metal level, and define an opening and expose this metal level, and the spacing of this open centre and this weld pad misalignment is less than the weld pad radius with the part; And
On the metal level that this opening exposes, form a solder projection.
24. method for making as claimed in claim 23 is characterized in that, this gap length between the weld pad radius to the weld pad radius 1/3rd between.
25. method for making as claimed in claim 23 is characterized in that, this gap length is 1/2nd of a weld pad radius.
26. method for making as claimed in claim 23 is characterized in that, this semiconductor substrate is the semiconductor chip of low-k.
27. method for making as claimed in claim 23 is characterized in that, this semiconductor substrate is the wafer of low-k.
28. method for making as claimed in claim 23 is characterized in that, this first protective layer is a silicon nitride layer.
29. method for making as claimed in claim 23 is characterized in that, this second protective layer is phenylpropyl alcohol cyclobutane or polymide dielectric layer.
30. method for making as claimed in claim 23 is characterized in that, the 3rd protective layer is dielectric layer or refuses layer.
31. method for making as claimed in claim 30 is characterized in that, this dielectric layer is phenylpropyl alcohol cyclobutane or polyimides.
32. method for making as claimed in claim 23 is characterized in that, this metal level is the welding block underlying metal.
33. method for making as claimed in claim 23 is characterized in that, this metal level comprises the combination of metallic aluminium, nickel-vanadium alloy, metallic copper and Titanium.
34. method for making as claimed in claim 23 is characterized in that, the step that should form solder projection on this metal level comprises:
On the 3rd protective layer, cover one deck and refuse layer, and corresponding this opening that exposes;
In this opening, insert scolder and carry out the reflow first time;
Removing this refuses layer and carries out the reflow second time to form solder projection.
35. method for making as claimed in claim 34 is characterized in that, this refuses layer is dry film.
36. method for making as claimed in claim 34 is characterized in that, this scolder is to insert in the opening with mode of printing.
37. the method for making of a semiconductor device is characterized in that, this method for making comprises:
Semiconductor substrate with weld pad is provided;
On this semiconductor substrate, form first, second protective layer successively, and expose this weld pad;
The first metal layer is combined in this weld pad and covers its this local second protective layer on every side;
The 3rd protective layer is covered on this second protective layer and local this first metal layer, and define an opening and expose this first metal layer, and the spacing of this open centre and this weld pad misalignment is less than the weld pad radius with the part;
On this first metal layer in conjunction with second metal level and cover the 3rd local around it protective layer; And
On this second metal level, form a solder projection.
38. method for making as claimed in claim 37 is characterized in that, this gap length between the weld pad radius to the weld pad radius 1/3rd between.
39. method for making as claimed in claim 37 is characterized in that, this gap length is 1/2nd of a weld pad radius.
40. method for making as claimed in claim 37 is characterized in that, this semiconductor substrate is the semiconductor chip of low-k.
41. method for making as claimed in claim 37 is characterized in that, this semiconductor substrate is the wafer of low-k.
42. method for making as claimed in claim 37 is characterized in that, this first protective layer is a silicon nitride layer.
43. method for making as claimed in claim 37 is characterized in that, this second protective layer is phenylpropyl alcohol cyclobutane or polymide dielectric layer.
44. method for making as claimed in claim 37 is characterized in that, the 3rd protective layer is dielectric layer or refuses layer.
45. method for making as claimed in claim 44 is characterized in that, this dielectric layer is phenylpropyl alcohol cyclobutane or polyimides.
46. method for making as claimed in claim 37 is characterized in that, this first, second metal level is the welding block underlying metal.
47. method for making as claimed in claim 37 is characterized in that, this first, second metal level comprises the combination of metallic aluminium, nickel-vanadium alloy, metallic copper and Titanium respectively.
48. method for making as claimed in claim 37 is characterized in that, the step that should form solder projection on this second metal level comprises:
On the 3rd protective layer, cover one deck and refuse layer;
Defining this refuses layer and exposes this opening with correspondence;
In this opening, form scolder;
Remove this and refuse layer and remove, and carry out reflow to form solder projection not by this second metal level that scolder covered.
49. method for making as claimed in claim 48 is characterized in that, this refuses layer is photoresistance.
50. method for making as claimed in claim 48 is characterized in that, this scolder is to be formed in this opening with plating mode.
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| CNB2005100709080A CN100382291C (en) | 2005-05-17 | 2005-05-17 | Semiconductor device and making method thereof |
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| CNB2005100709080A CN100382291C (en) | 2005-05-17 | 2005-05-17 | Semiconductor device and making method thereof |
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| CN101241866B (en) * | 2007-02-05 | 2010-12-01 | 南茂科技股份有限公司 | Making method of protrusion block structure with reinforced object |
| TWI419242B (en) | 2007-02-05 | 2013-12-11 | Chipmos Technologies Inc | Bump structure having a reinforcement member and manufacturing method therefore |
| TWI445147B (en) | 2009-10-14 | 2014-07-11 | Advanced Semiconductor Eng | Semiconductor device |
| CN102339767A (en) * | 2010-07-26 | 2012-02-01 | 矽品精密工业股份有限公司 | Semiconductor element and manufacturing method thereof |
| TWI478303B (en) | 2010-09-27 | 2015-03-21 | Advanced Semiconductor Eng | Chip having metal pillar and package having the same |
| CN102064135B (en) * | 2010-10-21 | 2015-07-22 | 日月光半导体制造股份有限公司 | Chip with metal post and encapsulating structure of chip with metal post |
| TWI451546B (en) | 2010-10-29 | 2014-09-01 | Advanced Semiconductor Eng | Stacked semiconductor package, semiconductor package thereof and method for making a semiconductor package |
| US8624404B1 (en) * | 2012-06-25 | 2014-01-07 | Advanced Micro Devices, Inc. | Integrated circuit package having offset vias |
| US8884443B2 (en) | 2012-07-05 | 2014-11-11 | Advanced Semiconductor Engineering, Inc. | Substrate for semiconductor package and process for manufacturing |
| US8686568B2 (en) | 2012-09-27 | 2014-04-01 | Advanced Semiconductor Engineering, Inc. | Semiconductor package substrates having layered circuit segments, and related methods |
| US8772950B2 (en) * | 2012-11-07 | 2014-07-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for flip chip substrate with guard rings outside of a die attach region |
| CN103745936B (en) * | 2014-02-08 | 2016-08-17 | 华进半导体封装先导技术研发中心有限公司 | The manufacture method of fan-out square chip level package |
| TWI651819B (en) * | 2016-11-28 | 2019-02-21 | 矽品精密工業股份有限公司 | Substrate structure and its preparation method |
| CN113261096A (en) * | 2019-12-13 | 2021-08-13 | 深圳市汇顶科技股份有限公司 | Chip packaging structure |
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