CN113258892A - 差动放大器 - Google Patents

差动放大器 Download PDF

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Publication number
CN113258892A
CN113258892A CN202110153510.2A CN202110153510A CN113258892A CN 113258892 A CN113258892 A CN 113258892A CN 202110153510 A CN202110153510 A CN 202110153510A CN 113258892 A CN113258892 A CN 113258892A
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voltage
differential amplifier
gate
source
pmos transistor
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CN202110153510.2A
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椎名美臣
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Ablic Inc
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Ablic Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45026—One or more current sources are added to the amplifying transistors in the differential amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45342—Indexing scheme relating to differential amplifiers the AAC comprising control means on a back gate of the AAC
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45508—Indexing scheme relating to differential amplifiers the CSC comprising a voltage generating circuit as bias circuit for the CSC
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45674—Indexing scheme relating to differential amplifiers the LC comprising one current mirror

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

本发明涉及差动放大器。差动放大器具备：第一导电型的第一及第二MOS晶体管，它们构成差动输入电路；偏置电流源，其使偏置电流流过第一及第二MOS晶体管；第一导电型的第三MOS晶体管，其在偏置电流源与第一及第二MOS晶体管之间，限制第一及第二MOS晶体管的背栅电压。

Description

差动放大器
技术领域
本发明涉及差动放大器。
背景技术
图3是表示以往的差动放大器的电路图。
以往的差动放大器具备：构成差动输入电路的PMOS晶体管31和32；起到负载作用的NMOS晶体管33和34；作为偏置电流源的恒流源35；以及NMOS晶体管36。NMOS晶体管36限制PMOS晶体管31和32的背栅与源极间电压。
如上所述，差动放大器具备NMOS晶体管36，因此，即使将高电压设定为电源电压，由于PMOS晶体管31和32的背栅与源极间电压成为NMOS晶体管36的栅极与源极间电压，所以PMOS晶体管31的互导也不会减少到必要以上，能够在确保较宽的同相输入电压范围的同时，抑制偏移电压的增加(例如，参照专利文献1)。
现有技术文献
专利文献
专利文献1：日本特开平11-41037号公报
发明内容
发明要解决的课题
但是，以往的差动放大器具备进行了二极管连接的NMOS晶体管36，因此，作为电源电压，需要比将PMOS晶体管31和32的栅极与源极间电压和NMOS晶体管36的栅极与源极间电压相加而得的电压高的电压。即，以往的差动放大器难以进行低电压动作。
本发明是鉴于上述课题而完成的，其目的在于提供一种能够在确保较宽的同相输入电压范围的同时，进行低电压动作的差动放大器。
用于解决课题的手段
为了解决上述课题，本发明的实施例的差动放大器的特征在于，具备：第一导电型的第一及第二MOS晶体管，它们构成差动输入电路；偏置电流源，其使偏置电流流过所述第一及第二MOS晶体管；以及第一导电型的第三MOS晶体管，其在所述偏置电流源与所述第一及第二MOS晶体管之间，限制所述第一及第二MOS晶体管的背栅电压。
发明效果
根据本发明的差动放大器，能够在确保较宽的同相输入电压范围的同时，以低电压进行动作。
附图说明
图1是表示本发明的实施方式的差动放大器的电路图。
图2是表示本发明的实施方式的差动放大器的另一例的电路图。
图3是表示以往的差动放大器的电路图。
标号说明
11、12、16：PMOS晶体管
13、14：NMOS晶体管
15：恒流源
17：恒压源
具体实施方式
图1是表示本发明的实施方式的差动放大器的电路图。
本实施方式的差动放大器具备：构成差动输入电路的PMOS晶体管11和12；起到负载作用的NMOS晶体管13和14；作为偏置电流源的恒流源15；以及PMOS晶体管16。
PMOS晶体管16的源极和背栅连接于恒流源15，栅极连接于差动放大器的输入端子例如输入端子INN。PMOS晶体管11的源极与PMOS晶体管16的漏极连接，栅极与输入端子INP连接，背栅与恒流源15连接。PMOS晶体管12的源极与PMOS晶体管16的漏极连接，栅极与输入端子INN连接，背栅与恒流源15连接。NMOS晶体管13的栅极和漏极连接于PMOS晶体管11的漏极，源极和背栅连接于接地端子。NMOS晶体管14的栅极与NMOS晶体管13的栅极连接，漏极连接于PMOS晶体管12的漏极和输出端子OUT，源极和背栅连接于接地端子。
以下，对如上所述构成的差动放大器的动作进行说明。
PMOS晶体管16的栅极与差动放大器的输入端子INN连接，因此，PMOS晶体管16的与源极连接的背栅的电压成为对输入端子INN的电压加上栅极与源极间电压而得的值。另外，PMOS晶体管16的源极连接于PMOS晶体管11和12的背栅，因此，PMOS晶体管16限制PMOS晶体管11和12的背栅与源极间电压。即，PMOS晶体管11和12的背栅的电压成为对输入端子的电压加上PMOS晶体管16的栅极与源极间电压而得的值。
这里，PMOS晶体管16的尺寸设定为使得栅极与源极间电压比PMOS晶体管11和12高。例如，使PMOS晶体管16的L比PMOS晶体管11和12大。
若这样构成PMOS晶体管16，则PMOS晶体管11和12的背栅电位变高，因此，能够通过背栅效应扩大同相输入电压范围，进而，电源电压只要是比PMOS晶体管16的栅极与源极间电压高的电压即可，因此，差动放大器能够以比以往的差动放大器低的电压进行动作。
如上所述，根据本发明的差动放大器，在限制构成差动输入电路的PMOS晶体管的背栅与源极间电压的电路中，具备了栅极与输入端子连接并且栅极与源极间电压比构成差动输入电路的PMOS晶体管高的PMOS晶体管，因此，能够在确保较宽的同相输入电压范围的同时，以低电压进行动作。
图2是表示本发明实施方式的差动放大器的另一例的电路图。
图2的差动放大器从图1追加了与PMOS晶体管16的栅极连接的恒压源17。恒压源17对PMOS晶体管16的栅极施加偏置电压。
当将恒压源17的偏置电压设定得比输入端子的电压高时，PMOS晶体管16的栅极与源极间电压高于PMOS晶体管11和12的栅极与源极间电压。因此，如果将恒压源17的偏置电压设定为适当的值，则PMOS晶体管16能够以与PMOS晶体管11和12相同的尺寸构成。
即，图2的差动放大器即使通过将恒压源17的偏置电压设定为适当的值来以与PMOS晶体管11和12相同的尺寸构成PMOS晶体管16，也能够得到与图1的差动放大器同样的效果。
以上，对本发明的实施方式进行了说明，但本发明并不限定于上述实施方式，在不脱离本发明的主旨的范围内能够进行各种变更。
例如，在本实施方式中，说明了差动放大器为PMOS晶体管构成差动输入电路、且PMOS晶体管限制其背栅与源极间电压的电路，但也可以为NMOS晶体管构成差动输入电路、且NMOS晶体管限制其背栅与源极之间的电压的电路。该情况下的差动放大器在电源端子和接地端子之间的关系上，电路被反转而构成。

Claims (3)

1.一种差动放大器，其特征在于，其具备：
第一导电型的第一及第二MOS晶体管，它们构成差动输入电路；
偏置电流源，其使偏置电流流过所述第一及第二MOS晶体管；以及
第一导电型的第三MOS晶体管，其在所述偏置电流源与所述第一及第二MOS晶体管之间，限制所述第一及第二MOS晶体管的背栅电压。
2.根据权利要求1所述的差动放大器，其特征在于，
所述第三MOS晶体管的栅极与所述第一及第二MOS晶体管中的任意晶体管的栅极连接，所述第三MOS晶体管的栅极与源极间电压比所述第一及第二MOS晶体管的栅极与源极间电压高。
3.根据权利要求1所述的差动放大器，其特征在于，
对所述第三MOS晶体管的栅极输入比输入端子的电压高的偏置电压。
CN202110153510.2A 2020-02-07 2021-02-04 差动放大器 Pending CN113258892A (zh)

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JP2020-019244 2020-02-07
JP2020019244A JP7479753B2 (ja) 2020-02-07 2020-02-07 差動増幅器

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Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5764101A (en) 1995-08-23 1998-06-09 National Semiconductor Corporation Rail-to-rail input common mode range differential amplifier that operates with very low rail-to-rail voltages
JPH1141037A (ja) 1997-07-15 1999-02-12 Toshiba Corp ボルテージフォロワ・オペアンプ
JP2005136473A (ja) 2003-10-28 2005-05-26 Nec Electronics Corp 演算増幅回路
JP2016187123A (ja) 2015-03-27 2016-10-27 株式会社東芝 コンパレータ回路

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US11482976B2 (en) 2022-10-25
JP7479753B2 (ja) 2024-05-09
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