CN113257959B - Preparation method of micro light-emitting diode chip, micro light-emitting diode chip and display module - Google Patents
Preparation method of micro light-emitting diode chip, micro light-emitting diode chip and display module Download PDFInfo
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- CN113257959B CN113257959B CN202110382593.2A CN202110382593A CN113257959B CN 113257959 B CN113257959 B CN 113257959B CN 202110382593 A CN202110382593 A CN 202110382593A CN 113257959 B CN113257959 B CN 113257959B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
Abstract
The invention discloses a preparation method of a micro light-emitting diode chip, the micro light-emitting diode chip and a display module. The preparation method of the micro light-emitting diode chip comprises the following steps: providing a first miniature light-emitting diode chip semi-finished product; forming a passivation layer on the first miniature light-emitting diode chip semi-finished product; arranging a photoresist layer with a p-type through hole and an n-type through hole on the passivation layer, and etching to form a corresponding p-contact through hole and a corresponding n-contact through hole on the passivation layer; reserving the photoresist layer, and sequentially forming an electrode layer and an electric connection layer; and removing the photoresist layer and the substrate to obtain the micro light-emitting diode chip. According to the preparation method of the micro light-emitting diode chip, the electrode layer and the electric connection layer can be directly formed by reserving the photoresist layer, so that the n electrode, the p electrode, the first electric connection block and the second electric connection block are obtained, photoetching of the first electric connection block and the second electric connection block is omitted, and the using number of photoetching plates is reduced.
Description
Technical Field
The invention relates to the technical field of processing of a micro light-emitting diode chip, in particular to a preparation method of the micro light-emitting diode chip, the micro light-emitting diode chip and a display module.
Background
The Micro light-emitting diode generally comprises Micro LED, nano LED and other Micro LED structures, has long service life, high brightness, low power consumption, small volume and ultrahigh resolution, and can be applied to extreme environments such as high temperature or radiation and the like.
The micro light-emitting diode generally comprises a Mesa structure (Mesa), a transparent conducting layer, a p electrode, an n electrode, a passivation layer and an In layer of flip metal, 5 to 6 photoetching plates are needed for carrying out the process, a single micro light-emitting diode can be further etched to a substrate to isolate the device, and then the laser stripping is carried out to obtain an independent device.
That is to say, 5 to 6 photolithography masks are needed to be used for the process when the traditional micro light-emitting diode is manufactured, and the number of the used photolithography masks is large, so that the photolithography alignment difficulty of each process is increased, the structure and performance of a device are easily affected by inaccuracy, and the yield of the product is affected.
Disclosure of Invention
Therefore, there is a need for a method for fabricating micro led chips that can reduce the number of photolithography boards used.
In addition, it is necessary to provide a micro led chip and a display module including the same.
A preparation method of a micro light-emitting diode chip comprises the following steps:
providing a first miniature light-emitting diode chip semi-finished product, wherein the first miniature light-emitting diode chip semi-finished product comprises a substrate and an n-type material layer arranged on the substrate, the n-type material layer comprises an n region and a p region which are separated from each other, and the first miniature light-emitting diode chip semi-finished product further comprises a quantum well light-emitting layer, a p-type material layer and a conducting layer which are sequentially stacked and are all arranged in the p region;
forming a passivation layer on the first miniature light-emitting diode chip semi-finished product;
arranging a photoresist layer with a p-type through hole and an n-type through hole on the passivation layer, and then etching to remove the passivation layer in the corresponding region of the p-type through hole and the n-type through hole, so as to form a corresponding p-contact through hole and a corresponding n-contact through hole on the passivation layer, thereby obtaining a second miniature light-emitting diode chip semi-finished product, wherein the projections of the p-type through hole and the p-contact through hole on the n-type material layer fall into the p region, and the projections of the n-type through hole and the n-contact through hole on the n-type material layer fall into the n region; and
reserving the photoresist layer, and sequentially forming an electrode layer and an electric connection layer on the second micro light-emitting diode chip semi-finished product, wherein the electrode layer falling in the n contact through hole forms an n electrode, the electric connection layer falling on the n electrode forms a first electric connection block, the electrode layer falling in the p contact through hole forms a p electrode, and the electric connection layer falling on the p electrode forms a second electric connection block; and
and removing the photoresist layer and the substrate to obtain the required micro light-emitting diode chip.
A micro light emitting diode chip, comprising:
an n-type material layer including an n region and a p region thereon, the n region and the p region being spaced apart from each other;
the n electrode and the first electric connection block are sequentially stacked and are arranged in the n region, and the n electrode is directly contacted with the n-type material layer;
the quantum well light-emitting layer, the p-type material layer, the conducting layer, the p electrode and the second electric connection block are sequentially stacked and arranged in the p region, and the quantum well light-emitting layer is in direct contact with the n-type material layer; and
a passivation layer disposed on the n-type material layer, the passivation layer being between the n-region and the p-region, thereby separating the n-region and the p-region.
A display module comprises the micro light-emitting diode chip.
According to the preparation method of the micro light-emitting diode chip, the photoresist layer is reserved, so that the electrode layer and the electric connection layer can be directly formed, the n electrode, the p electrode, the first electric connection block and the second electric connection block are obtained, and photoetching of the first electric connection block and the second electric connection block is omitted.
Compared with the traditional preparation method of the micro light-emitting diode chip, the preparation method of the micro light-emitting diode chip can reduce the number of used photoetching plates and reduce the alignment times of photoetching alignment, thereby reducing errors and improving the yield of products.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Wherein:
fig. 1 is a flowchart of a method for manufacturing the micro light emitting diode chip shown in fig. 1.
Fig. 2a, 2b and 2c are schematic diagrams illustrating a method for manufacturing the micro light emitting diode chip shown in fig. 1.
Fig. 3 is a schematic structural diagram of a micro led chip manufactured by the method for manufacturing a micro led chip shown in fig. 1.
Fig. 4 is an assembly diagram of a micro led chip and a driving panel according to an embodiment.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
With reference to fig. 1, fig. 2a, fig. 2b and fig. 2c, the present invention discloses a method for manufacturing a micro light emitting diode chip, comprising the following steps:
s10, providing a first micro light-emitting diode chip semi-finished product.
Referring to fig. 2a (3), the first micro light emitting diode chip semi-finished product includes a substrate 101 and an n-type material layer 10 disposed on the substrate 101, an n-type material layer 20 including an n region 22 and a p region 24 spaced apart from each other, and a quantum well light emitting layer 50, a p-type material layer 60, and a conductive layer 70 sequentially stacked and disposed on the p region 24.
Specifically, with reference to fig. 2a and fig. 2b, in this embodiment, the step of providing the first micro light emitting diode chip semi-finished product is:
providing a substrate 101, and sequentially forming an n-type material layer, a quantum well light-emitting layer and a p-type material layer on the substrate 101, wherein the n-type material layer 20 comprises an n region and a p region which are separated from each other;
forming a conductive layer 70 on the p-type material layer 60;
forming an etching mask layer 701 on the conductive layer 70, and then etching, so that a region which is not covered by the etching mask layer 701 is etched to the n-type material layer 20, and the projection of the etching mask layer 701 on the n-type material layer 20 falls into the p region 24;
the etch mask layer 701 is removed.
The substrate 101 may be sapphire (Al) 2 O 3 ) Silicon (Si), silicon carbide (SiC), and the like.
In the present invention, the substrate 101 is a sapphire substrate.
In the operation of forming the conductive layer 70 on the p-type material layer 60, deposition may be employed to form the conductive layer 70.
In particular, the deposition method can be magnetron sputtering, chemical vapor deposition, vacuum reactive evaporation, pulsed laser deposition and the like.
In this embodiment, the conductive layer 70 may be ITO (indium tin oxide), nickel gold, or the like, so that the current diffusion is more uniform.
After deposition, the conductive layer 70 is brought into ohmic contact with the surface of the p-type material layer 60 by RTA rapid thermal annealing.
Preferably, in S10, forming an etching mask layer on the conductive layer 70, and then etching, so that the region not covered by the etching mask layer 701 is etched to the n-type material layer 20:
an etching mask layer 701 is formed on the conductive layer 70, the conductive layer 70 in the region not covered with the etching mask layer 701 is removed by the conductive layer etching solution, and then the region not covered with the etching mask layer 701 is etched to the n-type material layer 20.
The etch mask layer 701 may be photoresist, metal, ferroelectric oxide such as SiO 2 And the like, or combinations of such materials.
And photoetching and defining a mask layer pattern by using a Mesa photoetching plate, wherein the Mesa area size is less than 100 mu m.
The conductive layer etching solution is a reagent that can be used to etch the conductive layer 70.
In this embodiment, the conductive layer 70 is ITO, and in this case, the conductive layer etching solution is an ITO etching solution.
The conductive layer 70 is etched to have a Mesa shape and size by using an ITO etchant, so that the photolithography step for the conductive layer 70 can be omitted.
The operation of etching the region not covered with the etching mask layer 701 to the n-type material layer 20 may be etching to the n-type material layer 20 layer by ICP, thereby forming a Mesa (Mesa) that emits light.
The shape of the table top can be in different shapes such as square, circle, polygon, ellipse and the like. The gas type differs depending on the type of substrate, e.g. BCl for GaAs and GaN substrates 3 And Cl 2 A process gas.
And S20, forming a passivation layer 100 on the first micro light-emitting diode chip semi-finished product.
In conjunction with fig. 2b, in particular, a passivation layer 100 is deposited on the first micro light emitting diode chip semi-finished product. The passivation layer 100 may be SiO 2 、Si 3 N 4 、Al 2 O 3 And the deposition method can be a thin film deposition technique such as PECVD, ALD and the like.
In the mass production stage, S20 specifically includes:
and depositing a passivation layer 100 by using a thin film deposition method such as PECVD (plasma enhanced chemical vapor deposition), photoetching by using a Substrate photoetching plate to define the position of an isolation channel, and etching to the Substrate by using an ICP (inductively coupled plasma) or RIE (reactive ion etching) mode to enable the single Micro-LED to be respectively and independently insulated.
In this embodiment, only the preparation of a single micro led chip is shown, so that the above steps can be omitted.
And S30, arranging a photoresist layer 702 with an n-type through hole 7022 and a p-type through hole 7024 on the passivation layer 100, and then etching to remove the passivation layer 100 in the region corresponding to the p-type through hole 7024 and the n-type through hole 7022, so as to form a corresponding n-contact through hole 1002 and a corresponding p-contact through hole 1004 on the passivation layer 100, thereby obtaining a second semi-finished product of the micro light-emitting diode chip.
Referring to (6) of fig. 2b, in the second half-finished micro light emitting diode chip, the projections of the p-type via 7024 and the p-contact via 1004 on the n-type material layer 20 fall into the p region 24, and the projections of the n-type via 7022 and the n-contact via 1002 on the n-type material layer 20 fall into the n region 22.
Specifically, in S30, an Elec photolithography plate is used for photolithography, the opening position and the electrode position are defined at the same time, the photolithography step of opening is omitted, the contact hole is opened by wet etching or dry etching, and then the photoresist is left without removal to prepare for the next step.
S40, the photoresist layer 702 is remained, and an electrode layer 703 and an electrical connection layer 704 are sequentially formed on the second micro light emitting diode chip semi-finished product.
In connection with (7) and (8) in fig. 2c, the electrode layer 703 falling within the n-contact via 1002 forms the n-electrode 30, the electrical connection layer 704 falling on the n-electrode 30 forms the first electrical connection block 40, the electrode layer 703 falling within the p-contact via 1004 forms the p-electrode 80, and the electrical connection layer 704 falling on the p-electrode 80 forms the second electrical connection block 90.
In this embodiment, the first and second electrical connection blocks 40 and 90 are both made of indium material, so that an indium flip-chip structure can be formed.
Specifically, in S40, the photoresist layer 702 in the previous step is left, and evaporation of the metal electrode and the indium flip-chip structure is performed. The electrode material can be Ti/Al/Ti/Au, or other metals (Ni/Fe/Pt/Pd, etc.) or conductive materials, and the shape of the electrode can be square, round corner square, etc.
The indium flip structure is used for forming indium balls through subsequent backflow, and the LED chip is conveniently flipped. And indium is directly evaporated on the electrode, so that the photoetching step of an indium flip-chip structure is omitted.
That is, in S40, the electrode layer 703 and the electrical connection layer 704 can be prepared only by using an Elec photolithography board, and the photolithography step of the indium flip-chip structure is omitted compared with the conventional process.
S50, removing the photoresist layer 702, and removing the substrate 101 to obtain the required micro light-emitting diode chip.
In this embodiment, the operation of removing the photoresist layer 702 is: the photoresist layer 702 is removed by dissolving the photoresist layer 702 with an organic solvent (acetone, etc.).
In this embodiment, the substrate 101 may decompose the intrinsic n-type material layer 10 by using laser energy, so as to separate a single micro led chip from the substrate 101.
Referring to fig. 4, the micro light emitting diode chip may be flip-chip bonded to the driving panel 200.
According to the preparation method of the micro light-emitting diode chip, the photoresist layer 702 is reserved, so that the electrode layer 703 and the electric connection layer 704 can be directly formed, the n electrode 30, the p electrode 80, the first electric connection block 40 and the second electric connection block 90 are obtained, and the photoetching of the first electric connection block 40 and the second electric connection block 90 is omitted.
Compared with the traditional preparation method of the micro light-emitting diode chip, the preparation method of the micro light-emitting diode chip can reduce the number of used photoetching plates and reduce the alignment times of photoetching alignment, thereby reducing errors and improving the yield of products.
In S10, mesa shapes and the conductive layer 70 are defined by a Mesa photolithography plate, and photolithography of the conductive layer 70 is omitted.
To sum up, according to the preparation method of the micro light emitting diode chip, when the micro light emitting diode chip is produced in large scale, only 3 photolithography boards Mesa, substrate and Elec are needed to prepare the single micro light emitting diode chip with the inverted structure, and compared with the conventional process flow, the photolithography steps of the transparent conducting layer, the contact hole and the indium metal are saved, so that the alignment error of photolithography alignment at each time is reduced, the process flow is optimized, and the product yield is improved.
In the invention, the Micro light-emitting diode generally comprises Micro LED, nano LED and other Micro LED structures. The preparation method of the Micro light-emitting diode chip can be used for preparing LED structures including Micro LED structures, nano LED structures and other Micro LED structures.
With reference to fig. 3, the present invention also discloses a micro light emitting diode chip manufactured by the above method for manufacturing a micro light emitting diode chip, comprising: intrinsic n-type material layer 10, n-type material layer 20, n-electrode 30, first electrical connection block 40, quantum well light emitting layer 50, p-type material layer 60, conductive layer 70, p-electrode 80, and second electrical connection block 90 and passivation layer 100.
In the invention, the Micro light-emitting diode generally comprises Micro LED, nano LED and other Micro LED structures.
To improve the quality of the n-type material layer 20, an intrinsic n-type material layer 10 is typically formed prior to forming the n-type material layer 20.
In other embodiments, the intrinsic n-type material layer 10 may also be eliminated.
In conjunction with the dashed portions in fig. 3, the n-type material layer 20 includes thereon an n-region 22 and a p-region 24 that are spaced apart from each other.
The n-electrode 30 and the first electrical connection block 40 are stacked in this order and are each disposed in the n-region 22, and the n-electrode 30 is in direct contact with the n-type material layer 20.
The quantum well light-emitting layer 50, the p-type material layer 60, the conductive layer 70, the p-electrode 80, and the second electrical connection block 90 are sequentially stacked and all disposed in the p region 24, and the quantum well light-emitting layer 50 is in direct contact with the n-type material layer 20.
A passivation layer 100 is disposed on the n-type material layer 20, the passivation layer 100 being located between the n-region 22 and the p-region 24, thereby separating the n-region 22 and the p-region 24.
Preferably, the conductive layer 70 is a transparent conductive layer, and the conductive layer 70 is a Ni/Au conductive layer or an Indium Tin Oxide (ITO) conductive layer.
In this embodiment, the conductive layer 70 is an indium tin oxide conductive layer.
Preferably, the n-electrode 30 and the p-electrode 80 are identical.
Specifically, the n-electrode 30 may be a Ti/Al/Ti/Au electrode or a Ni/Fe/Pt/Pd electrode, and the p-electrode 80 may be a Ti/Al/Ti/Au electrode or a Ni/Fe/Pt/Pd electrode.
In the present embodiment, both the n-electrode 30 and the p-electrode 80 are Ti/Al/Ti/Au electrodes.
Preferably, the material of the passivation layer 100 may be SiO 2 、Si 3 N 4 Or Al 2 O 3 。
The first and second electrical connection blocks 40 and 90 are both indium metal electrodes.
With reference to fig. 4, the first electrical connection block 40 and the second electrical connection block 90 can be reflowed into the first indium ball 40 'and the second indium ball 90', so that the micro light emitting diode chip can be flip-chip bonded to the driving panel 200.
And by doing so, the photolithography step of the indium flip-chip structure is omitted.
Preferably, in other embodiments, the micro light emitting diode chip may further include a carrier confining layer disposed between the quantum well light emitting layer 50 and the p-type material layer 60.
Preferably, in other embodiments, the micro light emitting diode chip may further include a carrier transport layer disposed between the p-type material layer 60 and the conductive layer 70.
In this embodiment, the n-type material layer 20, the quantum well light-emitting layer 50, and the p-type material layer 60 are all GaN-based materials.
That is, n-type material layer 20 is n-GaN, quantum well light-emitting layer 50 is an MQW quantum well, and p-type material layer 60 is p-GaN.
In other embodiments, the n-type material layer 20, quantum well light emitting layer 50, and p-type material layer 60 may also be other group III-V semiconductor materials, for example, alGaInP based materials.
The invention also discloses a display module of an embodiment, which comprises the micro light-emitting diode chip.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (9)
1. A preparation method of a micro light-emitting diode chip is characterized by comprising the following steps:
providing a first miniature light-emitting diode chip semi-finished product, wherein the first miniature light-emitting diode chip semi-finished product comprises a substrate and an n-type material layer arranged on the substrate, the n-type material layer comprises an n region and a p region which are separated from each other, and the first miniature light-emitting diode chip semi-finished product further comprises a quantum well light-emitting layer, a p-type material layer and a conducting layer which are sequentially stacked and are all arranged in the p region;
forming a passivation layer on the first miniature light-emitting diode chip semi-finished product;
arranging a photoresist layer with a p-type through hole and an n-type through hole on the passivation layer, and then etching to remove the passivation layer in the region corresponding to the p-type through hole and the n-type through hole and keep the conductive layer in the region corresponding to the p-type through hole, so that a corresponding p-contact through hole and a corresponding n-contact through hole are formed in the passivation layer, and a second semi-finished product of the micro light-emitting diode chip is obtained, wherein the projections of the p-type through hole and the p-contact through hole on the n-type material layer fall into the p region, and the projections of the n-type through hole and the n-contact through hole on the n-type material layer fall into the n region; and
reserving the photoresist layer, and sequentially forming an electrode layer and an electric connection layer on the second micro light-emitting diode chip semi-finished product, wherein the electrode layer falling in the n contact through hole forms an n electrode, the electric connection layer falling on the n electrode forms a first electric connection block, the electrode layer falling in the p contact through hole forms a p electrode, and the electric connection layer falling on the p electrode forms a second electric connection block; and
removing the photoresist layer and the substrate to obtain a required micro light-emitting diode chip;
the first electric connection block and the second electric connection block are both indium metal electrodes, and the operation of reflowing the first electric connection block and the second electric connection block into indium balls is further included.
2. The method for manufacturing a micro light emitting diode chip as claimed in claim 1, wherein the step of providing the first semi-finished micro light emitting diode chip comprises:
providing a substrate, and sequentially forming an n-type material layer, a quantum well light-emitting layer and a p-type material layer on the substrate, wherein the n-type material layer comprises an n region and a p region which are separated from each other;
forming a conductive layer on the p-type material layer;
forming an etching mask layer on the conducting layer, and then etching, so that the region which is not covered by the etching mask layer is etched to the n-type material layer, and the projection of the etching mask layer on the n-type material layer falls into the p region; and
and removing the etching mask layer.
3. The method for manufacturing a micro light-emitting diode chip as claimed in claim 2, wherein the steps of forming an etching mask layer on the conductive layer and etching the conductive layer to etch the region not covered by the etching mask layer to the n-type material layer are as follows:
and forming an etching mask layer on the conducting layer, removing the conducting layer in the area which is not covered by the etching mask layer through conducting layer corrosive liquid, and etching the area which is not covered by the etching mask layer to the n-type material layer.
4. The method for manufacturing a micro light emitting diode chip according to any one of claims 1 to 3, wherein the removing of the photoresist layer comprises: and dissolving the photoresist layer by using an organic solvent, thereby removing the photoresist layer.
5. A micro light-emitting diode chip manufactured by the method for manufacturing a micro light-emitting diode chip as claimed in any one of claims 1 to 4, comprising:
an n-type material layer including an n region and a p region thereon, the n region and the p region being spaced apart from each other;
the n electrode and the first electric connection block are sequentially stacked and are arranged in the n region, and the n electrode is directly contacted with the n-type material layer;
the quantum well light-emitting layer, the p-type material layer, the conducting layer, the p electrode and the second electric connection block are sequentially stacked and arranged in the p region, and the quantum well light-emitting layer is in direct contact with the n-type material layer; and
a passivation layer disposed on the n-type material layer, the passivation layer being between the n-region and the p-region, thereby separating the n-region and the p-region;
the first electric connection block and the second electric connection block are indium metal electrodes.
6. The micro light-emitting diode chip of claim 5, wherein the conductive layer is a transparent conductive layer, and the conductive layer is a Ni/Au conductive layer or an indium tin oxide conductive layer;
the P electrode is a Ti/Al/Ti/Au electrode or a Ni/Fe/Pt/Pd electrode;
the N electrode is a Ti/Al/Ti/Au electrode or a Ni/Fe/Pt/Pd electrode;
the passivation layer is made of SiO 2 、Si 3 N 4 Or Al 2 O 3 。
7. The micro light-emitting diode chip of claim 5, further comprising an intrinsic n-type material layer disposed on a side of the n-type material layer remote from the n-electrode;
the micro light-emitting diode chip also comprises a current carrier limiting layer arranged between the quantum well light-emitting layer and the p-type material layer;
the micro light-emitting diode chip further comprises a carrier transmission layer arranged between the p-type material layer and the conducting layer.
8. The micro light-emitting diode chip according to any one of claims 5 to 7, wherein the n-type material layer, the quantum well light-emitting layer, and the p-type material layer are GaN-based material or AlGaInP-based material.
9. A display module comprising the micro light emitting diode chip as claimed in any one of claims 5 to 8.
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| CN101350381A (en) * | 2007-07-18 | 2009-01-21 | 晶科电子（广州）有限公司 | Salient point LED and manufacturing method thereof |
| CN107331749A (en) * | 2017-05-27 | 2017-11-07 | 华灿光电（浙江）有限公司 | A kind of preparation method of light-emitting diode chip for backlight unit |
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