CN113253085A - Power cycle test method and system for power semiconductor device - Google Patents
Power cycle test method and system for power semiconductor device Download PDFInfo
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Abstract
The application discloses a power cycle test method and a power cycle test system for a power semiconductor device, so that a test result can reflect the power cycle capability of a tested device more truly. The system comprises: a test circuit and a controller; the main loop of the test circuit is connected with a direct current power supply, a first switch unit, an inductive device and a device to be tested in series, and the test circuit also comprises a follow current loop of the inductive device; the controller is used for controlling the first switch unit to be switched on and off in a circulating mode, controlling the tested device to be switched on and off in a circulating mode during the on period of the first switch unit, and cooling the tested device through the cooling system during the off period of the first switch unit so that junction temperature fluctuation of the tested device can meet the regulation.
Description
Technical Field
The invention relates to the technical field of power electronics, in particular to a power cycle test method and a power cycle test system for a power semiconductor device.
Background
A power semiconductor device (e.g., an IGBT) is designed to withstand tens of thousands or even millions of power cycles, and therefore needs to be power cycle tested to confirm its power cycle capability.
In a conventional power cycle test scheme, a device under test is kept normally on, a large current with a certain duty cycle is applied to the device under test, and the device under test is cyclically heated and cooled (the heat for heating the device under test is from conduction loss of the device under test) in cooperation with a cooling system until the device under test fails.
However, the above-mentioned test scheme does not consider the on-off loss of the device under test, and the difference from the actual operating state of the device under test is large, and the test result cannot truly reflect the power cycle capability of the device under test.
Disclosure of Invention
In view of this, the present invention provides a power cycle testing method and system for a power semiconductor device, so that the testing result can reflect the power cycle capability of the device under test more truly.
A power semiconductor device power cycle test system, comprising: a test circuit and a controller; the main loop of the test circuit is connected with a direct current power supply, a first switch unit, an inductive device and a device to be tested in series, and the test circuit also comprises a follow current loop of the inductive device;
the controller is used for controlling the first switch unit to be switched on and off in a circulating mode, controlling the tested device to be switched on and off in a circulating mode during the on period of the first switch unit, and cooling the tested device through the cooling system during the off period of the first switch unit so that junction temperature fluctuation of the tested device can meet the regulation.
Optionally, junction temperature measurement of the device under test is obtained based on the controller and the probing current generating circuit;
the detection current generation circuit is connected in parallel to the device to be detected and is used for introducing detection current when the device to be detected is conducted, and meanwhile, an energy backflow prevention device is further arranged on the detection current generation circuit;
the controller is specifically configured to control the device under test to be kept normally on during the period when the first switching unit is turned off, and calculate the junction temperature according to the saturation voltage drop value and the saturation voltage drop temperature coefficient of the device under test at the detection current.
Optionally, the detection current generation circuit includes a voltage source, an energy backflow prevention device, and a current limiting device connected in series.
Optionally, the detection current generation circuit includes a current source, an energy backflow prevention device, and a second switch unit connected in series, and a switching timing sequence of the second switch unit is complementary to a switching timing sequence of the first switch unit.
Optionally, the freewheel loop includes a diode and a resistor connected in series.
Optionally, the output voltage of the dc power supply is equal to the dc bus voltage to be borne by the device under test during actual operation.
Optionally, the magnitude of the inductive value of the inductive device is equal to the magnitude of the inductive load in the circuit when the device to be tested actually operates.
Optionally, the test circuit further includes: the drive circuit of the device to be tested is used for changing the gate resistance value of the device to be tested, so that the on-off process of the device to be tested is adjusted, and the heating efficiency of the device to be tested is changed.
A power semiconductor device power cycle test method is applied to a test circuit; the main loop of the test circuit is connected with a direct current power supply, a first switch unit, an inductive device and a device to be tested in series, and the test circuit also comprises a follow current loop of the inductive device;
the method comprises the following steps: and controlling the first switch unit to be switched on and off in a circulating way, controlling the tested device to be switched on and off in a switching-on period of the first switch unit, and cooling the tested device through a cooling system in a switching-off period of the first switch unit so as to enable junction temperature fluctuation of the tested device to be in accordance with regulations.
Optionally, the test circuit further includes: a probe current generating circuit connected in parallel with the device under test; the detection current generation circuit is used for introducing detection current when the device to be detected is conducted, and meanwhile, an energy backflow prevention device is further arranged on the detection current generation circuit;
the cooling of the device under test by the cooling system during the turn-off period of the first switching unit so as to make the junction temperature fluctuation of the device under test meet the specification specifically includes:
determining a saturation voltage drop temperature coefficient of the tested device under the detection current;
controlling the tested device to be kept normally on during the turn-off period of the first switching unit, and acquiring a saturation voltage drop value of the tested device under the detection current;
and calculating junction temperature according to the saturation voltage drop value and the saturation voltage drop temperature coefficient of the tested device under the detection current, and cooling the tested device through a cooling system to enable the junction temperature fluctuation of the tested device to be in accordance with the specification.
Optionally, the test is ended until the device under test fails or a failure determination criterion is reached or the required number of power cycles is completed.
According to the technical scheme, the high-frequency on-off, high-voltage bearing and large current flowing through of the tested device are considered in the testing process, and compared with a traditional power cycle testing scheme, the power cycle testing method is closer to the actual operation condition of the tested device, so that the power cycle capability of the tested device can be reflected more truly.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a power cycle test circuit of a power semiconductor device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a power cycle test circuit of another power semiconductor device according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a specific topology of the circuit shown in FIG. 2;
FIG. 4 shows the main switch T of the circuit shown in FIG. 31And a device under test TdutThe on-off timing diagram of (1);
FIG. 5a shows the main switch T of the circuit shown in FIG. 31And a device under test TdutA schematic diagram of the corresponding current paths when all are conducted;
FIG. 5b shows the main switch T of the circuit shown in FIG. 31Conducting and tested device TdutA corresponding current path schematic diagram when the circuit is switched off;
FIG. 5c shows the main switch T of the circuit shown in FIG. 31Shut down and device under test TdutA corresponding current path schematic diagram when conducting;
FIG. 6 shows the inductor Lcurrent and the device under test T of the circuit of FIG. 3dutA current waveform diagram;
FIG. 7 is a schematic diagram of yet another specific topology of the circuit of FIG. 2;
FIG. 8 is a schematic diagram of yet another specific topology of the circuit of FIG. 2;
fig. 9 is a flowchart of a method for cooling a device under test by a cooling system during the turn-off period of the first switching unit to make the junction temperature fluctuation of the device under test meet the specification, according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The power cycle capability of the power semiconductor device refers to the capability of the power semiconductor device to bear temperature change caused by alternating current load during operation without failure. In order to test the power cycle capability of a power semiconductor device, the embodiment of the invention discloses a power semiconductor device power cycle test system, which comprises: a test circuit and a controller; after the device under test is connected to the test circuit, the controller starts to control the test circuit to cooperate with the cooling system to circularly heat and cool the device under test (i.e. after the device under test is heated to a certain temperature, the device under test enters a cooling stage, and then enters a heating stage after being cooled to a certain temperature, … …, and the circulation is repeated), and the test is finished until the device under test fails or reaches a failure determination standard or the required power circulation number is completed, so as to evaluate the power circulation capability of the device under test.
In the traditional test scheme, a tested device is kept normally on, a switching process is not carried out, and on-off loss is not generated; however, when the device to be tested actually works in systems such as a converter and the like, under the control of a PWM wave, the device to be tested is in a high-frequency on-off state, and junction temperature (junction temperature is the actual working temperature of the power semiconductor device) fluctuation is generated under the influence of factors such as power fluctuation, ambient temperature change, output frequency and the like, so that the difference between the test environment under the conventional test scheme and the actual operating condition of the device to be tested is too large. In order to enable the test environment to be closer to the actual operation condition of the device to be tested and reflect the power circulation capability of the device to be tested more truly, the embodiment of the invention considers the high-frequency on-off, high voltage bearing and large current flowing of the device to be tested when designing the test circuit and the controller.
The test circuit and the controller are designed as follows: the main loop of the test circuit is connected in series with a direct current power supply, a first switch unit, an inductive device and a device under test TdutThe test circuit further comprises a freewheeling loop for the inductive device, as shown in fig. 1; the controller is used for controlling the first switch unit to be switched on and off in a circulating way and controlling a tested device T during the switching-on period of the first switch unitdutCycling on and off the device under test T through a cooling system during the first switching unit is turned offdutCooling is performed to make the device under test TdutThe junction temperature fluctuation of the semiconductor device is in accordance with the specification.
In the design, the first switch unit is switched on and off at a low frequency; device under test TdutSwitching on and off at high frequency during the switching-on period of the first switch unit; when the first switch unit and the device under test TdutWhen the current is switched on, the current output by the direct current power supply is led into a tested device T through the inductive devicedut(ii) a When the first switch unit is turned on, the device under test TdutWhen the inductive device is disconnected, the inductive device continues current through the follow current loop, the current of the main loop is attenuated to the level before rising, and the device T to be tested next time is preventeddutAfter the circuit is switched on, the current of the main loop continuously rises; due to the device under test TdutThe device T to be tested is switched on and off at high frequency during the switching-on period of the first switch unitdutWill be heated to heat the device under test TdutThe heat comes from the tested device TdutConduction loss and on-off loss. After the first switch unit is disconnected, the tested device TdutStopping heating, and starting cooling system to the device under test TdutCooling is performed to make the device under test TdutThe junction temperature fluctuation of the semiconductor device is in accordance with the specification.
Wherein the output voltage of the DC power supply can be designed as the device under test TdutThe main loop current can be designed as the tested device T under the DC bus voltage and the main loop current born by the practical operation in the system such as the converterdutThe high current is introduced into the system such as a converter during actual operation, and the device T to be testeddutSwitching on/off at high frequency under DC bus voltage to the tested device TdutThe high-frequency chopping is carried out on the high current, the high-frequency on-off, high voltage bearing and high current flowing through of the tested device are fully considered in the test environment, and compared with a traditional test scheme, the high-frequency chopping test method is closer to the actual operation condition of the tested device, and can reflect the power circulation capacity of the tested device more truly.
Optionally, in the device under test TdutDuring the cyclic heating and cooling process, the device T to be testeddutThe junction temperature measurement of (a) may be obtained based on the controller and the probe current generation circuit;
as shown in FIG. 2, the probe current generating circuit is connected in parallel to the device under test TdutFor in a device under test TdutWhen the circuit is conducted, the detection current is introduced, and meanwhile, an energy backflow prevention device is also arranged on the detection current generation circuit;
the controller is specifically configured to control the device under test T during the turn-off of the first switching unitdutIs kept normally on according to the device under test TdutAnd calculating junction temperature according to the saturation voltage drop value and the saturation voltage drop temperature coefficient under the detection current.
Specifically, the main loop current is a large current, and the probing current is a small current, and the probing current is applied to the device to be tested in the cooling stage to calculate the junction temperature. The saturation voltage drop value of the tested device under the detection current can be directly obtained by sampling. And the saturation voltage drop temperature coefficient of the tested device under the detection current is obtained in advance before the tested device is heated and cooled circularly, and the obtaining mode is as follows: putting the tested device into a temperature control box, introducing a certain current to the tested device, keeping the tested device in a normally-on state, setting the temperature of the temperature control box to a certain value, and heating for a long time, so that the junction temperature of the tested device is consistent with the temperature of the temperature control box, and the junction temperature of the tested device can be changed by changing the temperature of the temperature control box; under the fixed current, the saturation voltage drop of the tested device and the junction temperature are in a linear relation, and the saturation voltage drop of the tested device under the set temperature is measured, so that the saturation voltage drop temperature coefficient of the tested device can be obtained.
Besides, the saturation voltage drop temperature coefficient of the device under test under the detection current can also be obtained by mounting the device under test on a temperature control plate (internal fluid temperature change), and the coefficient obtaining mode is more numerous and is not listed as the same.
Next, the switching device is used as a main switch T1The inductive device is an inductor L, for example, as shown in fig. 3, to explain the testing principle after the probe current generating circuit is introduced:
in the heating phase, the main switch T1Kept normally on, the device under test TdutSwitching on and off at high frequency; in the cooling phase, the main switch T is controlled1Keep normally off, the device under test TdutAnd kept always on. Main switch T1And a device under test TdutThe on-off timing of (c) is shown in fig. 4.
Wherein, when the main switch T1And a device under test TdutWhen all are conducted, the corresponding current path is as shown in FIG. 5a, and the main loop current outputted by the DC power supply is introduced into the device under test T through the inductor LdutAt the same time, because the device under test T is at this timedutThe voltage drop across the two terminals is low, so that the probing current is also injected into the device under test TdutBut with a smaller current amplitude, the heating effect is negligible compared to the main loop current.
When the main switch T1Conducting and tested deviceTdutWhen turned off, the corresponding current path is as shown in fig. 5 b: the inductor L current flows through the follow current loop to prevent the next tested device TdutAfter the device is switched on, the current continuously rises, and meanwhile, the device T to be tested is prevented because the energy backflow preventing device is arranged on the detection current generating circuitdutWhen the circuit is turned off, the inductor L current flows into the detection current generation circuit to cause the damage of devices in the detection current generation circuit.
When the main switch T1Shut down and device under test TdutWhen conducting, the corresponding current path is as shown in fig. 5 c: detection current generation circuit for detecting TdutA probe current is injected.
Inductor L current and device under test TdutThe current waveform is shown in fig. 6. It can be seen that the device under test TdutWhen conducting, TdutThe current and inductor L current rise simultaneously, in effect TdutThe current will be slightly larger because of the presence of the probe current component. When the device under test TdutAt turn-off, TdutThe current drops to 0 and the inductor L current begins to freewheel through the freewheel circuit, at a value that is equal to the value of the device under test TdutThe gap that is turned off decays to the same magnitude before rising.
Alternatively, the main switch T1 may be an IGBT, but is not limited thereto.
Optionally, in any of the embodiments disclosed above, as shown in fig. 7, the dc power supply includes a capacitor CbusThe direct current bus capacitor is used for simulating an actual circuit; capacitor CbusVoltage UbusProvided by a preceding stage circuit.
Alternatively, in any of the embodiments disclosed above, still referring to fig. 7, the free-wheeling circuit includes a diode D and a resistor R connected in series.
Optionally, in any of the embodiments disclosed above, the inductor L simulates an inductive load of an actual circuit, and the diode D makes the device under test contain a diode recovery current component when the device under test is turned on, which is closer to an actual situation that the device under test operates in the converter.
Optionally, in any of the embodiments disclosed above, the detection current generation circuit includes a voltage source, an energy backflow prevention device, and a current limiting device connected in series. Still referring to fig. 7, the voltage source is identified as Us, and the energy back-flow prevention device is, for example, a back-flow prevention diode Ds, and the current limiting device is, for example, a current limiting resistor Rs.
Or, the detection current generation circuit comprises a current source, an energy backflow prevention device and a second switch unit which are connected in series, and the switch time sequence of the second switch unit is complementary with that of the first switch unit. Referring to fig. 8, the current source Is identified, the energy backflow prevention device Is, for example, a backflow prevention diode Ds, and the second switching unit Is, for example, a switching tube Ts. Since the inductor L Is also equivalent to a current source during operation and cannot be connected in series with the current source Is in the detection current generation circuit, Ts and Ds are required to be used to make the inductor L separate from the main loop during operation.
Optionally, in any embodiment disclosed above, the test circuit further includes: the drive circuit of the device to be tested is used for changing the gate resistance value of the device to be tested, so that the on-off process of the device to be tested is adjusted, and the heating efficiency of the device to be tested is changed.
In addition, corresponding to the method embodiment, the embodiment of the invention also discloses a power cycle test method of the power semiconductor device, which is applied to a test circuit; the main loop of the test circuit is connected with a direct current power supply, a first switch unit, an inductive device and a device to be tested in series, and the test circuit also comprises a follow current loop of the inductive device;
the method comprises the following steps: and controlling the first switch unit to be switched on and off in a circulating way, controlling the tested device to be switched on and off in a switching-on period of the first switch unit, and cooling the tested device through a cooling system in a switching-off period of the first switch unit so as to enable junction temperature fluctuation of the tested device to be in accordance with regulations.
Optionally, the test circuit further includes: a probe current generating circuit connected in parallel with the device under test; the detection current generation circuit is used for introducing detection current when the device to be detected is conducted, and meanwhile, an energy backflow prevention device is further arranged on the detection current generation circuit;
the cooling of the device under test by the cooling system during the turn-off period of the first switching unit so as to make the junction temperature fluctuation of the device under test meet the specification, as shown in fig. 9, specifically includes:
step S01: determining a saturation voltage drop temperature coefficient of the tested device under the detection current;
step S02: controlling the tested device to be kept normally on during the turn-off period of the first switching unit, and acquiring a saturation voltage drop value of the tested device under the detection current;
step S03: and calculating junction temperature according to the saturation voltage drop value and the saturation voltage drop temperature coefficient of the tested device under the detection current, and cooling the tested device through a cooling system to enable the junction temperature fluctuation of the tested device to be in accordance with the specification.
Optionally, the test is ended until the device under test fails or a failure determination criterion is reached or the required number of power cycles is completed.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The terms "first," "second," and the like in the description and in the claims, and in the drawings, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the use of the verb "comprise a" to define an element does not exclude the presence of another, identical element in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the embodiments. Thus, the present embodiments are not intended to be limited to the embodiments shown herein but are to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (11)
1. A power cycle test system for a power semiconductor device, comprising: a test circuit and a controller; the main loop of the test circuit is connected with a direct current power supply, a first switch unit, an inductive device and a device to be tested in series, and the test circuit also comprises a follow current loop of the inductive device;
the controller is used for controlling the first switch unit to be switched on and off in a circulating mode, controlling the tested device to be switched on and off in a circulating mode during the on period of the first switch unit, and cooling the tested device through the cooling system during the off period of the first switch unit so that junction temperature fluctuation of the tested device can meet the regulation.
2. The power semiconductor device power cycle test system of claim 1, wherein junction temperature measurements of the device under test are obtained based on the controller and the probe current generation circuit;
the detection current generation circuit is connected in parallel to the device to be detected and is used for introducing detection current when the device to be detected is conducted, and meanwhile, an energy backflow prevention device is further arranged on the detection current generation circuit;
the controller is specifically configured to control the device under test to be kept normally on during the period when the first switching unit is turned off, and calculate the junction temperature according to the saturation voltage drop value and the saturation voltage drop temperature coefficient of the device under test at the detection current.
3. The power semiconductor device power cycle test system of claim 2, wherein the probing current generating circuit comprises a voltage source, an energy backflow prevention device and a current limiting device connected in series.
4. The power semiconductor device power cycle test system of claim 2, wherein the probing current generating circuit comprises a current source, an energy backflow prevention device and a second switching unit connected in series, and the second switching unit is complementary to the first switching unit in switching timing.
5. The power semiconductor device power cycle test system of claim 1, wherein the freewheel loop includes a diode and a resistor connected in series.
6. The power cycle test system of claim 1, wherein the output voltage of the dc power supply is equal to the dc bus voltage to which the device under test is subjected during actual operation.
7. The power cycling test system for power semiconductor devices according to claim 1, wherein the magnitude of the inductive load of the inductive device is equal to the magnitude of the inductive load in the circuit when the device under test is actually operating.
8. The power semiconductor device power cycle test system of claim 1, wherein the test circuit further comprises: the drive circuit of the device to be tested is used for changing the gate resistance value of the device to be tested, so that the on-off process of the device to be tested is adjusted, and the heating efficiency of the device to be tested is changed.
9. A power semiconductor device power cycle test method is characterized in that the method is applied to a test circuit; the main loop of the test circuit is connected with a direct current power supply, a first switch unit, an inductive device and a device to be tested in series, and the test circuit also comprises a follow current loop of the inductive device;
the method comprises the following steps: and controlling the first switch unit to be switched on and off in a circulating way, controlling the tested device to be switched on and off in a switching-on period of the first switch unit, and cooling the tested device through a cooling system in a switching-off period of the first switch unit so as to enable junction temperature fluctuation of the tested device to be in accordance with regulations.
10. The power semiconductor device power cycle test method of claim 9, wherein the test circuit further comprises: a probe current generating circuit connected in parallel with the device under test; the detection current generation circuit is used for introducing detection current when the device to be detected is conducted, and meanwhile, an energy backflow prevention device is further arranged on the detection current generation circuit;
the cooling of the device under test by the cooling system during the turn-off period of the first switching unit so as to make the junction temperature fluctuation of the device under test meet the specification specifically includes:
determining a saturation voltage drop temperature coefficient of the tested device under the detection current;
controlling the tested device to be kept normally on during the turn-off period of the first switching unit, and acquiring a saturation voltage drop value of the tested device under the detection current;
and calculating junction temperature according to the saturation voltage drop value and the saturation voltage drop temperature coefficient of the tested device under the detection current, and cooling the tested device through a cooling system to enable the junction temperature fluctuation of the tested device to be in accordance with the specification.
11. The power semiconductor device power cycle test method of claim 9, wherein the test is terminated until the device under test fails or a failure determination criterion is met or a required number of power cycles is completed.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115656770A (en) * | 2022-10-19 | 2023-01-31 | 杭州国磊半导体设备有限公司 | Method and device for testing power driving chip, computer equipment and storage medium |
| CN116500400A (en) * | 2022-09-08 | 2023-07-28 | 南京信息工程大学 | Online in-situ characterization system and method for failure state of solder layer of silicon carbide power device |
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