CN113243049A

CN113243049A - Display panel and electronic device

Info

Publication number: CN113243049A
Application number: CN201880097601.5A
Authority: CN
Inventors: 黄斌; 金志河
Original assignee: Shenzhen Royole Technologies Co Ltd
Current assignee: Shenzhen Royole Technologies Co Ltd
Priority date: 2018-12-27
Filing date: 2018-12-27
Publication date: 2021-08-10
Also published as: WO2020133086A1

Abstract

The utility model provides a display panel (100), including display screen (10) and a plurality of drive circuit (20), breach (12) have been seted up to one side of display screen (10), display screen (10) include pixel array (18), pixel array (18) are including a plurality of first display region pixel line (182) that are located breach (12) one side and a plurality of second display region pixel line (184) that are located breach (18) other side, first display region pixel line (182) and second display region pixel line (184) that are located same line are connected, every drive circuit (20) are connected and are located first display region pixel line (182) and second display region pixel line (184) of same line.

Description

Display panel and electronic device

Technical Field

The present disclosure relates to display screens, and particularly to a display panel and an electronic device.

Background

In the prior art, a Gate driver on array (GOA) circuit is widely used in displays such as LCD and AMOLED. Which is a critical part of the display panel for supplying scanning signals to the pixel array. When the communication terminal is applied, due to the existence of a front-facing camera, a receiver and the like, a display panel of the existing communication terminal generally adopts a Notch (special-shaped screen) display panel design, the left side and the right side of the Notch display panel are respectively connected with a GOA circuit with the same row number as that of a pixel row of a pixel array, the left GOA circuit and the right GOA circuit of the display panel respectively provide scanning signals for the same pixel row, and due to the fact that the number of the GOA circuits is large, the area of circuit wiring of the display panel is large, and the frame of the display panel is wide, and the requirement of the current narrower frame cannot be met.

Disclosure of Invention

Embodiments of the present application provide a display panel and an electronic device.

The display panel of the embodiment of this application includes display screen and a plurality of drive circuit, a breach has been seted up to a side of display screen, the display screen includes pixel array, pixel array is including being located a plurality of first display area pixel rows of breach one side and being located a plurality of second display area pixel rows of breach opposite side are located same row first display area pixel row with second display area pixel row electricity is connected, every drive circuit connects and is located same row first display area pixel row with second display area pixel row.

In the display panel of the embodiment of the application, the first display area pixel row and the second display area pixel row which are positioned on the same row are electrically connected, and each driving circuit is connected with the first display area pixel row and the second display area pixel row which are positioned on the same row, so that under the condition that the display picture is normally displayed, the number of the driving circuits can be relatively reduced, the circuit wiring area and the frame width of the display panel can be reduced, and the display panel can meet the requirement of a narrower frame.

An electronic device according to an embodiment of the present application includes the display panel described above.

In the electronic device according to the embodiment of the application, the first display area pixel row and the second display area pixel row in the same row are electrically connected, and each driving circuit is connected with the first display area pixel row and the second display area pixel row in the same row, so that the number of the driving circuits can be relatively reduced under the condition of ensuring normal display of a display picture, and therefore the circuit wiring area and the frame width of the display panel can be reduced, and the display panel can meet the requirement of a narrower frame.

Additional aspects and advantages of embodiments of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of embodiments of the present application.

Drawings

The above and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application.

Fig. 2 is a control timing chart of the display panel according to the embodiment of the present application.

Fig. 3 is a schematic structural diagram of a display panel in the prior art.

Fig. 4 is a control timing diagram of a related art display panel.

Fig. 5 is a schematic view of a partial structure of a display panel according to an embodiment of the present application.

Fig. 6 is a schematic configuration diagram of a driving circuit of a display panel according to an embodiment of the present invention.

The main reference numbers:

the display device comprises a display panel 100, a display screen 10, a notch 12, a left side 14, a right side 16, a lower side 17, a pixel array 18, a first display area pixel row 182, a second display area pixel row 184, a third display area pixel row 186, a driving circuit 20, a first driving circuit 22, a second driving circuit 24, a first clock signal line 30, a second clock signal line 40, a scanning signal line 50, a first metal layer 60, an insulating layer 70 and a second metal layer 80.

Detailed Description

Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative and are only for the purpose of explaining the present application and are not to be construed as limiting the present application.

In the description of the present application, it is to be understood that the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.

Referring to fig. 1 and fig. 2, in an embodiment of the present disclosure, a display panel 100 is provided, the display panel 100 includes a display screen 10 and a plurality of driving circuits 20, a notch 12 is formed on one side of the display screen 10, the display screen 10 includes a pixel array 18, the pixel array 18 includes a plurality of first display area pixel rows 182 located on one side of the notch 12 and a plurality of second display area pixel rows 184 located on the other side of the notch 12, the first display area pixel rows 182 and the second display area pixel rows 184 located on the same row are electrically connected, and each driving circuit 20 is connected to the first display area pixel rows 182 and the second display area pixel rows 184 located on the same row.

In the display panel 100 of the above embodiment, the first display area pixel row 182 and the second display area pixel row 184 in the same row are electrically connected, and each driving circuit 20 connects the first display area pixel row 182 and the second display area pixel row 184 in the same row, so that the number of the driving circuits 20 can be relatively reduced under the condition of ensuring normal display of the display screen, and thus the circuit wiring area and the frame width of the display panel 100 can be reduced, so that the display panel 100 can meet the requirement of a narrower frame.

Specifically, the display panel 100 may be a Notch (shaped screen) display panel 100. Wherein, special-shaped screen includes bang screen and V type screen etc..

The Display screen 10 may be an OLED (Organic Light-Emitting Diode), an LCD (Liquid Crystal Display, or Liquid Crystal Display 10), and the type of the Display screen 10 is not limited herein.

The driving circuit 20 may be a Gate driver on array (GOA) circuit. The GOA circuit provides row scanning signals for the pixel rows in the display area.

In some embodiments, the plurality of driving circuits 20 includes a plurality of first driving circuits 22 and a plurality of second driving circuits 24, the plurality of first driving circuits 22 being electrically connected to the odd-numbered rows of the first display region pixel rows 182 and the second display region pixel rows 184, respectively, and the plurality of second driving circuits 24 being electrically connected to the even-numbered rows of the first display region pixel rows 182 and the second display region pixel rows 184, respectively.

In this manner, the plurality of first driving circuits 22 may supply the scan signals to the first display area pixel rows 182 of the odd-numbered rows, respectively, and the plurality of second driving circuits 24 may supply the scan signals to the second display area pixel rows 184 of the even-numbered rows, respectively, thereby enabling the number of driving circuits 20 to be relatively reduced.

In some embodiments, the first display area pixel rows 182 and the second display area pixel rows 184 are located on the left side 14 and the right side 16 of the aperture 12, respectively, the pixel array 18 includes a third display area pixel rows 186 located on the lower side 17 of the aperture 12, the first driving circuits 22 are electrically connected to the odd-numbered third display area pixel rows 186, respectively, and the second driving circuits 24 are electrically connected to the even-numbered third display area pixel rows 186, respectively.

In this way, the number of driving circuits 20 connected to the pixel rows 186 of the third display region can be reduced, and the circuit layout area and the frame width of the display panel 100 can be reduced.

Specifically, in the related art, please refer to fig. 3 and fig. 4, the clock signals output by the clock signal lines (clk busline)130 connected to the driving circuits 120 connected to the pixel rows in the same row of the display area are the same. The pixel rows in the same display area in the left side 114 and the right side 116 of the notch 112 are respectively controlled by the left and right driving circuits 120 connected with the pixel rows in the corresponding display area, but the waveform timing of the row scanning signals transmitted to the pixel rows in the display area by the left and right driving circuits 120 in the same row through the row scanning signal line 150 is consistent. The two driving circuits 120 of the corresponding display area pixel rows are connected to the left and right sides of the same display area pixel row on the lower side 117 of the notch and controlled together, and the waveform timing of the row scanning signals transmitted to the display area pixel rows by the driving circuits 120 of the same row through the row scanning signal lines 150 is consistent. The driving circuit 120 is controlled in a double-fed (double-edge control) manner. As can be seen from fig. 3, in the conventional Notch display panel 100, the number of the driving circuits 120 to be connected to the display panel 100 having n rows of display area pixel rows is 2n, which results in a large area of the circuit wiring of the display panel 100 and a relatively wide frame of the display panel 110, and thus cannot satisfy the current requirement of a narrower frame.

In the present application, referring to fig. 1, the left side 14 of the notch 12 and the right side 16 of the notch 12 are notch GOA regions, and the lower side 18 of the notch 12 is a non-notch GOA region. The same row of display area pixel rows on the left side 14 of the aperture 12 and the right side 16 of the aperture 12 are connected by wires by making holes under the display panel 100 such that the first display area pixel row 182 on the same row is electrically connected to the second display area pixel row 184 and the first display area pixel row 182 and the second display area pixel row 184 on the same row can be supplied with a row scan signal by only one driving circuit 20.

Specifically, the first drive circuit 22 provides a row scan signal to electrically connect the first display region pixel rows 182 and the second display region pixel rows 184 of the odd rows. The second drive circuit 24 provides row scan signals to electrically connect the even numbered rows of the first display region pixel rows 182 and the second display region pixel rows 184. The waveform timing of the line scanning signals transmitted to the same line display area pixel lines on the left side 14 of the notch 12 and the right side 16 of the notch 12 are consistent, and the interlacing control mode is an inter-space (single-side drive) mode. As can be seen from this, in the Notch display panel 100 of the present application, the number of the driving circuits 20 that need to be connected to the display panel 100 having n rows of pixel rows in the display area is also n, so that compared to the Notch display panel 100 of the prior art, the number of the driving circuits 20 is reduced by half under the condition that the clock signal (clk) timing of the left and right sides of the display panel 100 is changed without increasing the number of the clock signal lines (clk busline) of the left and right sides of the display panel 100 and under the condition that the structure of the driving circuits 20 is not changed, and thus the circuit wiring area and the frame width of the display panel 100 can be reduced, so that the display panel 100 can meet the requirement of a narrower frame.

Referring to fig. 1, each of the first driving circuits 22 is connected to the first display area pixel rows 182 and the second display area pixel rows 184 of the same odd-numbered row, and the number of the first driving circuits 22 is the same as the total number of the rows of the display area pixel rows of the odd-numbered row. Each second drive circuit 24 connects a first display area pixel row 182 and a second display area pixel row 184 of the same even row, the number of second drive circuits 24 being the same as the total number of rows of display area pixel rows of even rows.

In this way, since the number of the first driving circuits 22 is the same as the total number of rows of the display area pixel rows of the odd-numbered rows and the number of the second driving circuits 24 is the same as the total number of rows of the display area pixel rows of the even-numbered rows, the number of the driving circuits 20 can be relatively reduced by the single-side driving method, and the circuit wiring area and the frame width of the display panel 100 can be reduced.

Specifically, in one embodiment, all of the first driving circuits 22 are disposed at one side of the display panel 100, and all of the second driving circuits 24 are disposed at the other side of the display panel 100. The first driving circuit 22 and the second driving circuit 24 are symmetrically arranged. Each first drive circuit 22 may provide a row scan signal to the first display area pixel row 182 and the second display area pixel row 184 connecting the same odd row. Each second drive circuit 24 may provide a row scan signal to first display area pixel rows 182 and second display area pixel rows 184 connected to the same even row.

Referring to fig. 1, in some embodiments, the display panel 100 includes a first clock signal line 30 and a second clock signal line 40, the first clock signal line 30 is connected to the first driving circuit 22, the second clock signal line 40 is connected to the second driving circuit 24, and the clock signals provided by the first clock signal line 30 and the second clock signal line 40 are arranged in time sequence.

In this way, the first clock signal line 30 is connected to the first driver circuit 22, and the second clock signal line 40 is connected to the second driver circuit 24, so that the first clock signal line 30 can independently input a clock signal to the first driver circuit 22, and the second clock signal line 40 can independently input a clock signal to the second driver circuit 24.

Specifically, the first clock signal line 30 may transmit a clock signal to the first driver circuit 22, and the second clock signal line 40 may transmit a clock signal to the second driver circuit 24. The clock signal is generated by the chip. The clock signal has two levels, one is low level, the other is high level, and the high and low levels can be set to different voltages according to the requirements of the circuit.

Referring to fig. 1, in some embodiments, the number of the first clock signal lines 30 is N1, the number of the first driving circuits 22 is M1, and the M1 first driving circuits 22 are divided into K1 first driving circuits 22, where M1 is K1N 1, N1 first clock signal lines 30 are connected to each first driving circuit 22 in the K2 first driving circuit 22 group according to a preset timing condition, 1 ≦ K2 ≦ K1, and M1, K1, N1, and K2 are positive integers.

Thus, the first clock signal lines 30 can cyclically provide clock signals to all the first driving circuits 22 according to the predetermined timing conditions, so that the number of the first clock signal lines 30 can be reduced, and the circuit layout area and the frame width of the display panel 100 can be reduced.

The number of the first clock signal lines 30 and the number of the first driving circuits 22 are not limited herein, and may be set according to actual requirements. Preferably, the number of the first clock signal lines 30 is 4.

Referring to fig. 1, in some embodiments, the number of the second clock signal lines 40 is N2, the number of the second driving circuits 24 is M2, and the M2 second driving circuits 24 are divided into K3 second driving circuits 24, where M2 is K3N 2, N2 second clock signal lines 40 are connected to each second driving circuit 24 of the K24 second driving circuits 24 according to a preset timing condition, 1 ≦ K4 ≦ K3, and M2, K3, N2, and K4 are positive integers.

Thus, the second clock signal lines 40 can cyclically provide clock signals to all the second driving circuits 24 according to the predetermined timing conditions, so that the number of the second clock signal lines 40 can be reduced, and the circuit layout area and the frame width of the display panel 100 can be reduced.

The number of the second clock signal lines 40 and the number of the second driving circuits 24 are not limited herein, and may be set according to actual requirements. Preferably, the number of the second clock signal lines 40 is 4.

Referring to fig. 1 and 2, in some embodiments, the clock signals of the first driving circuits 22 corresponding to the display area pixel rows of two adjacent odd-numbered rows have a difference of one period. The clock signals of the second driving circuits 24 corresponding to the pixel rows of the display areas of two adjacent even-numbered rows have a difference of one period.

In this way, the row scanning signals provided by the first driving circuit 22 to the pixel rows of the display area of the adjacent odd-numbered row may differ by one period, and the row scanning signals provided by the second driving circuit 24 to the pixel rows of the display area of the adjacent even-numbered row may also differ by one period.

Referring to fig. 1 and 2, in some embodiments, the clock signals of the driving circuits 20 corresponding to the pixel rows of the display regions in two adjacent rows are different by half a period. Thus, the scanning signals supplied to the pixel rows of the display region of two adjacent rows by the driving circuit 20 are different by a half cycle.

Specifically, as shown in fig. 1, in one embodiment, the first driving circuit 22 is connected to four first clock signal lines 30, which are the first

clock signal lines

1, 2, 3, and 4 respectively according to the predetermined timing condition, wherein the clock signals of two adjacent first clock signal lines 30 are different by one cycle. Every four first driving circuits 22 are grouped, and every four first driving circuits 22 are respectively connected with the first

clock signal lines

1, 2, 3 and 4. The second driving circuit 24 is connected to the four second clock signal lines 40, and respectively serves as the first

clock signal lines

5, 6, 7, and 8 according to a predetermined timing condition, wherein the clock signals of two adjacent second clock signal lines 40 have a difference of one cycle. Every four second driving circuits 24 are grouped, and every four second driving circuits 24 are respectively connected with the second

clock signal lines

5, 6, 7 and 8.

Referring to fig. 1 and 2, the clock signal lines connecting the first driving circuit 22 and the second driving circuit 24 cyclically provide clock signals, for example, the first

clock signal lines

1, 2, 3, 4 are respectively connected to the first driving circuits GOA1, GOA3, GOA5 and GOA7 in sequence. The first

clock signal lines

5, 6, 7, and 8 are connected to the second driving circuits GOA2, GOA4, GOA6, and GOA8, respectively, in this order. The first driver GOA1 outputs a row scanning signal G1, the first driver GOA3 outputs a row scanning signal G3, the first driver GOA5 outputs a row scanning signal G5, the first driver GOA7 outputs a row scanning signal G7, and so on, and the first driver GOA (n-1) signal G (n-1). The second driving circuit GOA2 outputs a row scanning signal G2, the second driving circuit GOA4 outputs a row scanning signal G4, the second driving circuit GOA6 outputs a row scanning signal G6, and so on, and the second driving circuit GOA (n) signal G (n).

Referring to fig. 1 and 2, in some embodiments, the number of the first driving circuits 22 is n/2, the first driving circuit 22 corresponding to the display area pixel row of the k-th row provides an input signal for the first driving circuit 22 corresponding to the display area pixel row of the k +2 row, and the first driving circuit 22 corresponding to the display area pixel row of the k +2 row provides a reset signal for the first driving circuit 22 corresponding to the display area pixel row of the k row.

The number of the second driving circuits 24 is n/2, the second driving circuit 24 corresponding to the display area pixel row of the (k-1) th row provides an input signal for the second driving circuit 24 corresponding to the display area pixel row of the (k + 1) th row, and the second driving circuit 24 corresponding to the display area pixel row of the (k + 1) th row provides a reset signal for the second driving circuit 24 corresponding to the display area pixel row of the (k-1) th row.

In the above embodiment, M1+ M2 is n.

Specifically, referring to fig. 1 and 2, in one embodiment, an input signal stvL is provided to the first driving circuit GOA1, an output signal of the first driving circuit GOA1 is used as an input signal of the first driving circuit GOA3, and the first driving circuit GOA3 provides a reset signal for the first driving circuit GOA 1; the output signal of the first driver GOA3 is used as the input signal of the first driver GOA5, and the first driver GOA5 provides the reset signal for the first driver GOA 3; the output signal of the first driver GOA5 is used as the input signal of the first driver GOA7, the first driver GOA7 provides the reset signal for the first driver GOA5, and so on, the output signal of the first driver GOA (n-3) is used as the input signal of the first driver GOA (n-1), the first driver GOA (n-1) provides the reset signal for the first driver GOA (n-3), and finally, a reset signal resetL is input to the first driver GOA (n-1).

In another embodiment, the second driver GOA2 is provided with an input signal stvR, the output signal of the second driver GOA2 is used as the input signal of the second driver GOA4, and the second driver GOA4 provides the reset signal for the second driver GOA 2; the output signal of the second driver GOA4 is used as the input signal of the second driver GOA6, and the second driver GOA6 provides the reset signal for the second driver GOA 4; the output signal of the second driver GOA6 is used as the input signal of the second driver GOA8, and the second driver GOA8 provides the reset signal for the second driver GOA 6; in analogy, the output signal of the second driving circuit GOA (n-2) is used as the input signal of the second driving circuit GOA (n), the second driving circuit GOA (n) provides the reset signal for the second driving circuit GOA (n-2), and finally, a reset signal resetR is input to the second driving circuit GOA (n).

Referring to fig. 1, in some embodiments, the display panel 100 includes scan signal lines 50, the driving circuit 20 provides row scan signals to the display area pixel rows through the scan signal lines 50, and a line width of the scan signal lines 50 connecting the plurality of first display area pixel rows 182 of the first display area 14 and the plurality of second display area pixel rows 184 of the second display area 16 is smaller than a line width of the scan signal lines 50 connecting the plurality of third display area pixel rows 186 of the third display area 17.

In this way, the resistances of the lines of the first display area 14 and the second display area 16 can be increased, so that the resistances of the lines of the first display area 14 and the second display area 16 can be balanced with the resistance of the lines of the third display area 17, thereby ensuring the quality of the picture of the display screen 10.

Referring to fig. 5, in some embodiments, the pixel rows of the display area include a first metal layer 60, an insulating layer 70, and a second metal layer 80 sequentially stacked from bottom to top, where the first metal layer 60 is used as a scan signal line, and the first metal layer 60, the insulating layer 70, and the second metal layer 80 form a capacitor.

In this way, since the first metal layer 60, the insulating layer 70 and the second metal layer 80 can form a capacitor, the capacitance of the lines on the left side 14 of the notch 12 and the right side 16 of the notch 12 can be increased, so that the capacitance of the lines on the left side 14 of the notch 12 and the left side 16 of the notch 12 can be balanced with the capacitance of the lines on the lower side 17 of the notch 12, thereby ensuring the quality of the picture of the display screen 10.

Specifically, RC loading (resistive and capacitive loading) of the display panel 100 refers to the product of resistance and capacitance generated by circuit elements of the display panel 100 connected by the scanning signal lines 50. The large RC loading of each region on the display panel 100 may cause deterioration of signal transmission quality, the inconsistent RC loading of the scanning signal lines 50 in different rows may cause inconsistency of signal transmission environment, and the load consistency of the scanning signal lines 50 in different rows may easily affect display quality. In the Notch (irregular screen) display panel 100, when one side of the display screen 10 is opened with the Notch 12 and some pixels are missing, the line widths of the row scanning signal lines 50 of the corresponding rows of the left side 14 of the Notch 12 and the right side 16 of the Notch 12 are reduced to increase the resistance R of the lines of the left side 14 of the Notch 12 and the right side 16 of the Notch 12, and the second metal layer 80 is added on the insulating layer 70 to make the first metal layer 60, the insulating layer 70 and the second metal layer 80 form an overlap capacitor, so that the rclading of the row scanning signal lines 50 of the left side 14 of the Notch 12, the right side 16 of the Notch 12 and the lower side 17 of the Notch 12 are consistent.

Referring to fig. 6, in some embodiments, the driving circuit 20 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and a capacitor C1. The gate of the first transistor M1 is connected to one end of the driving circuit 20 receiving the input signal, and the drain of the first transistor M1 is connected to the gate of the first transistor M1. The gate of the second transistor M2 is connected to the positive voltage of the power supply, and the source of the second transistor M2 is connected to the gate of the second transistor M2. The gate of the third transistor M3 is connected to one end of the capacitor C1 and the drain of the first transistor M1, the source of the third transistor M3 is connected to the clock signal terminal, and the drain of the third transistor M3 is connected to the scan signal line 50. The drain of the fourth transistor M4 is connected to the drain of the first transistor M1, and the source of the fourth transistor M4 is connected to the negative voltage of the power supply. The source of the fifth transistor M5 is connected to the drain of the third transistor M3 and one end of the capacitor C1, and the drain of the fifth transistor M5 is connected to the negative voltage of the power supply. The drain of the sixth transistor M6 is connected to the scan signal line 50, the gate of the sixth transistor M6 is connected to one end of the reset signal supplied from the driving circuit 20, and the source of the sixth transistor M6 is connected to the negative voltage of the power supply. The gate of the seventh transistor M7 is connected to the drain of the first transistor M1 and the gate of the third transistor M3, the source of the seventh transistor M7 is connected to the gate of the fourth transistor M4 and the gate of the fifth transistor M5, and the drain of the seventh transistor M7 is connected to the negative voltage of the power supply.

It should be noted that, the display panel 100 firstly provides an stvL input level to the driver circuit GOA1, the third transistor M3 is turned on, the clock signal line clk1 starts to input a clock signal, the signal terminal of the driver circuit outputs the row scan signal G1, and the clock signal line clk3 starts to input a clock signal, that is, the sixth transistor of the driver circuit is turned on, so that the signal terminal of the driver circuit is grounded, the row scan signal is reset to a low level, and so on, the signal terminal G (n) of the nth driver circuit is connected to the signal input terminal of the (n + 2) th driver circuit and the reset signal terminal of the (n-2) th driver circuit.

The embodiment of the present application further provides an electronic device (not shown). The electronic device includes the display panel 100 of any of the above embodiments.

In the electronic device according to the embodiment of the present invention, the first display area pixel row 182 and the second display area pixel row 184 in the same row are electrically connected, and each driving circuit 20 is connected to the first display area pixel row 182 and the second display area pixel row 184 in the same row, so that the number of the driving circuits 20 can be relatively reduced under the condition of ensuring the normal display of the display screen, and thus the circuit wiring area and the frame width of the display panel 100 can be reduced, so that the display panel 100 can meet the requirement of a narrower frame.

Specifically, the electronic device includes, but is not limited to, a mobile phone, a tablet computer, a notebook computer, an electronic book, a wearable electronic device, and the like.

In the description herein, references to the description of the terms "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, various steps or methods may be performed by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for performing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.

It will be understood by those skilled in the art that all or part of the steps carried out in the above method may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and the program, when executed, includes one or a combination of the steps of the method embodiments.

In addition, functional units in the embodiments of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be executed in the form of hardware or in the form of a software functional module. The integrated module, if executed in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.

The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc. Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.

Claims

The display panel is characterized by comprising a display screen and a plurality of driving circuits, wherein a notch is formed in one side edge of the display screen, the display screen comprises a pixel array, the pixel array comprises a plurality of first display area pixel rows located on one side of the notch and a plurality of second display area pixel rows located on the other side of the notch, the first display area pixel rows and the second display area pixel rows located on the same row are electrically connected, and each driving circuit is connected with the first display area pixel rows and the second display area pixel rows located on the same row.
The display panel according to claim 1, wherein the plurality of driving circuits include a plurality of first driving circuits electrically connected to the first display region pixel rows of odd-numbered rows and the second display region pixel rows, respectively, and a plurality of second driving circuits electrically connected to the first display region pixel rows of even-numbered rows and the second display region pixel rows, respectively.
The display panel according to claim 2, wherein a plurality of the first display region pixel rows and a plurality of the second display region pixel rows are respectively located on left and right sides of the notch, the pixel array includes a plurality of third display region pixel rows located on a lower side of the notch, a plurality of the first driving circuits are respectively electrically connected to the third display region pixel rows of odd rows, and a plurality of the second driving circuits are respectively electrically connected to the third display region pixel rows of even rows.
The display panel according to claim 2, wherein each of the first driving circuits is connected to the first display area pixel rows and the second display area pixel rows of the same odd-numbered row, and the number of the first driving circuits is the same as the total number of rows of the display area pixel rows of the odd-numbered rows;

each second driving circuit is connected with the first display area pixel rows and the second display area pixel rows of the same even-numbered row, and the number of the second driving circuits is the same as the row total number of the display area pixel rows of the even-numbered rows.
The display panel according to claim 2, wherein the display panel includes a first clock signal line and a second clock signal line, the first clock signal line is connected to the first driver circuit, the second clock signal line is connected to the second driver circuit, and a clock signal supplied from the first clock signal line and a clock signal supplied from the second clock signal line are arranged in time series.
The display panel according to claim 5, wherein the number of the first clock signal lines is N1, the number of the first driving circuits is M1, the M1 first driving circuits are divided into K1 first driving circuit groups, wherein M1 ═ K1 ═ N1, the N1 first clock signal lines are connected to each of the K2 first driving circuit groups under a preset timing condition, 1 ≦ K2 ≦ K1, and M1, K1, N1, and K2 are positive integers.
The display panel according to claim 5, wherein the number of the second clock signal lines is N2, the number of the second driving circuits is M2, the M2 second driving circuits are divided into K3 second driving circuit groups, wherein M2 is K3N 2, the N2 second clock signal lines are connected to each second driving circuit of the K4 second driving circuit groups under a preset timing condition, 1 ≦ K4 ≦ K3, and M2, K3, N2, and K4 are positive integers.
The display panel according to claim 5, wherein the clock signals of the first driving circuits corresponding to the display area pixel rows of two adjacent odd rows differ by one period;

the clock signals of the second driving circuits corresponding to the pixel rows of the display areas of two adjacent even-numbered rows have a difference of one period.
The display panel according to claim 5, wherein the clock signals of the driving circuits corresponding to the pixel rows of the display area of two adjacent rows are different by a half period.
The display panel according to claim 2, wherein the number of the first driving circuits is n/2, the first driving circuit corresponding to the display area pixel row of the kth row supplies the input signal to the first driving circuit corresponding to the display area pixel row of the kth +2 row, and the first driving circuit corresponding to the display area pixel row of the kth +2 row supplies the reset signal to the first driving circuit corresponding to the display area pixel row of the kth row;

the number of the second driving circuits is n/2, the second driving circuit corresponding to the display area pixel row of the (k-1) th row provides an input signal for the second driving circuit corresponding to the display area pixel row of the (k + 1) th row, the second driving circuit corresponding to the display area pixel row of the (k + 1) th row provides a reset signal for the second driving circuit corresponding to the display area pixel row of the (k-1) th row, k is an odd number, k and n are positive integers, n is the total number of the driving circuits, n is more than or equal to 2, and k is less than or equal to n.
The display panel according to claim 3, wherein the display panel includes scanning signal lines, the driving circuit is configured to supply a row scanning signal to the display region pixel rows through the scanning signal lines, and a line width of the scanning signal lines connecting the plurality of first display region pixel rows and the scanning signal lines connecting the plurality of second display region pixel rows is smaller than a line width of the scanning signal lines connecting the plurality of third display region pixel rows.
The display panel according to claim 11, wherein the display area pixel row includes a first metal layer, an insulating layer, and a second metal layer stacked in this order from bottom to top, the first metal layer serves as the scanning signal line, and the first metal layer, the insulating layer, and the second metal layer form a capacitor.
An electronic device characterized by comprising the display panel according to any one of claims 1 to 12.