CN107966864B - Liquid crystal display device - Google Patents
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- CN107966864B CN107966864B CN201711352517.7A CN201711352517A CN107966864B CN 107966864 B CN107966864 B CN 107966864B CN 201711352517 A CN201711352517 A CN 201711352517A CN 107966864 B CN107966864 B CN 107966864B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
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Abstract
The invention provides a liquid crystal display device, comprising: a first substrate and a second substrate opposite to each other; a liquid crystal layer between the first substrate and the second substrate; a plurality of thin film transistors and pixel electrodes connected thereto on the first substrate; a plurality of color filters on the second substrate; and a plurality of gate lines connected to the plurality of thin film transistors, each gate a corresponding row of the plurality of thin film transistors to apply a gray scale voltage, wherein the first substrate includes a plurality of sides, and at least one of the plurality of sides includes a gap, a first metal layer and a second metal layer are included near the gap, and the second metal layer and the gate lines on the first metal layer are at least partially overlapped to form a capacitor. In the liquid crystal display device provided by the invention, the load difference of the gate lines of the special-shaped screen is adjusted, and the layout space is saved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a special-shaped screen liquid crystal display device.
Background
A liquid Crystal Display (L acquired Crystal Display, L CD) is a mainstream Display technology in the market, and the L CD has a structure that liquid Crystal molecules are placed between a first glass substrate and a second glass substrate which are parallel to each other, a Thin Film Transistor (TFT) is arranged on the second glass substrate, a color filter is arranged on the first glass substrate, and different voltage signals are provided for the TFT to control the rotation direction of the liquid Crystal molecules, so that the deflection of light corresponding to each pixel point is controlled, and the Display purpose is finally achieved.
In recent years, with the rapid development of information electronic technology, wireless communication technology and media technology, people increasingly depend on electronic products, the demand is higher and higher, better visual experience is continuously pursued, and it is expected that an operable Area (AA) of a display screen can be maximized in a state that the size of the display screen is fixed, so that a display effect of narrow frame or even no frame of the display screen is realized. The concept of a full screen is created under the pursuit of the screen proportion, so that the display device becomes more attractive and fashionable in visual effect, and meanwhile, when a user appreciates a picture presented by the display technology, the user can obtain a wider visual field and the viewing experience is better. However, for some mobile devices, the front surface of the panel of the mobile device needs to be provided with devices such as a camera, a speaker, a distance sensor, etc., and the display device needs to avoid the position where the devices are arranged, so that an irregular shaped screen display device is generated, and the display effect of the irregular shaped screen display device, especially how to ensure the display effect of the irregular area of the irregular shaped screen display device, becomes a technical key point to be solved.
According to the existing technical scheme, the routing is arranged around the avoidance area, but the avoidance area is different from the loads of other parts and can generate difference with the display effect of other areas, so that the overall display effect is influenced, and the routing space of the avoidance position is limited.
In order to eliminate the influence of the gate driving parameters on the display effect, the gate driving parameters are generally modified or a virtual thin film transistor is added at present, but the method of modifying the gate driving parameters causes complex layout, so that the product is easy to be unstable due to changes of temperature, manufacturing process and the like; the gate line width is increased by adding the dummy tft compensation capacitor, which results in space waste.
Disclosure of Invention
In view of this, embodiments of the present invention provide a liquid crystal display device to solve the problem that the load of an irregular area in a special-shaped screen is different from that of other normal display areas, thereby affecting the display effect, and further saving space.
The present invention provides a liquid crystal display device, comprising:
a first substrate and a second substrate opposite to each other;
a liquid crystal layer between the first substrate and the second substrate;
a plurality of thin film transistors and pixel electrodes connected thereto on the first substrate;
a plurality of color filters on the second substrate; and
a plurality of gate lines connected to the plurality of thin film transistors for respectively gating a corresponding row of the plurality of thin film transistors to apply gray scale voltages,
wherein the first substrate comprises a plurality of side edges, and at least one side edge of the plurality of side edges comprises a notch,
the vicinity of the gap comprises a first metal layer and a second metal layer, and the second metal layer and the gate line on the first metal layer are at least partially overlapped to form a capacitor.
Preferably, the second metal layer near the gap includes a common electrode, and the plurality of gate lines and the common electrode at least partially overlap in the vicinity of the gap to form a capacitor.
Preferably, the plurality of gate lines include a first gate line and a second gate line for connecting the thin film transistors of the adjacent rows, and the first gate line and the second gate line are located on different metal layers and at least partially overlap in the vicinity of the gap to form a capacitor.
Preferably, the shapes of the first substrate and the second substrate are respectively one selected from the following shapes: rectangular, circular, oval, curved.
Preferably, the switch of the notch is one selected from the following shapes: rectangular, circular, oval, curved.
Preferably, the notch is shaped as an open rectangle including first to third sides.
Preferably, a portion of the first gate line near at least one of the first to third sides overlaps a corresponding portion of the second gate line.
Preferably, the first metal layer overlaps the second metal layer only in a lateral portion.
Preferably, an overlapping distance of the first metal layer and the second metal layer in a length direction and an overlapping distance in a width direction are according to a distribution of the gate line capacitance.
Preferably, the line width of the gate line on the first metal layer is the same as the line width on the second metal layer.
The invention has the beneficial effects that:
in the liquid crystal display device provided by the invention, the load difference of the gate lines of the special-shaped screen is adjusted, so that the load of the special-shaped area can be effectively compensated, the load of the gate lines of the irregular display area is close to that of the gate lines of the normal display area, the gate driving parameters are consistent, the display uniformity is improved, and the layout space is further saved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 is a top view of a tft structure.
FIG. 2 is a schematic top view of a layout according to an embodiment of the present technology.
FIG. 3 is a schematic top view of a layout of another embodiment of the present technology.
Fig. 4 is a schematic diagram illustrating a capacitor formed by stacking different metal layers in the concave-shaped gap region.
Fig. 5 is a diagram illustrating simulation results of a gate driving circuit in a normal display area at various temperatures and capacitances formed by stacking two adjacent gate lines of a concave area.
FIG. 6 is a partial schematic view of one embodiment of the present technology in an implementation.
FIG. 7 is a partial schematic view of another embodiment of the present technology in accordance with an implementation of the present technology.
Detailed Description
The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
FIG. 1 is a top view of a thin film transistor structure comprising: a gate line S11, a gate electrode S12, a source line S21, a source electrode S22, a drain electrode S23, and a pixel electrode S30. The gate line S11 is arranged laterally and forms a gate electrode S12 at an intersection with the source line S21, the source line S21 is arranged longitudinally and forms a source electrode S22 at a gate electrode S12 at an intersection with the gate line S11, and a drain electrode S23, the drain electrode S23 being connected to the pixel electrode S30. The gate driver provides a gate signal to the gate line S11, a gray scale signal is connected to the source line S21, when the voltage on the gate S12 reaches a threshold, the source S22 and the drain S23 are turned on, the pixel electrode S30 obtains the gray scale voltage provided by the source line S21, an electric field is formed between the pixel electrode S30 and the common electrode, and the liquid crystal molecules are influenced by the electric field and rotate due to dielectric anisotropy. The rotation angle of the liquid crystal molecules may change the transmittance of light transmitted through the pixel region. This allows for a brightness gradation, while the dummy thin film transistor (dummy TFT) is similar in structure and size to the same, with a single gate line S11 having a width of about 24 um.
FIG. 2 is a layout top view of one embodiment of the present technology. The irregular notch part is provided with a first metal layer M1 and a second metal layer M2, a gate wire of the irregular display area is positioned on the first metal layer M1 in a surrounding mode, the second metal layer M2 is stacked above the first metal layer M1 and forms a capacitance structure with the gate wire on the first metal layer M1, so that a part of a gate line S11 on the M1 in the figure is shielded and invisible by the second metal layer M2, the second metal layer M2 is electrically connected with a common electrode at the edge of the display area, the load increased by the capacitance structure of the capacitance structure is close to the load of a pixel unit missing from the notch, the deviation of the load of the notch part and the gate line S11 of the normal display area is compensated, and the gate driving parameters are consistent. The gate lines in the figures are for illustration only and are intended to fall within the scope of the present invention regardless of the number of gate lines.
Fig. 3 is a schematic top view of another embodiment of the present invention, wherein the shaped recess portion has a first gate line S1 and a second gate line S2, the gate lines of the shaped display area are respectively disposed on the first metal layer and the second metal layer around the recess, the second gate line S2 is stacked above the first gate line S1, the two traces are at least partially overlapped to form a capacitor structure, the load added by the capacitor structure is close to the load of the pixel unit missing at the recess to compensate the deviation between the load of the recess portion and the normal display area, so as to make the gate driving parameters consistent, and the layout space on the plane is saved because the first gate line S1 and the second gate line S2 are stacked on the first metal layer and the second metal layer. The gate lines in the figures are for illustration only and are intended to fall within the scope of the present invention regardless of the number of gate lines.
Fig. 4 is a partial schematic view showing a capacitor formed by stacking different metal layers in the concave-shaped gap region. Different metal layer wires are overlapped to form a capacitor, and the deviation between the notch part and the load of the normal display area is compensated, so that the load of the notch area is close to the load of the normal display area.
When the gate traces are distributed on different metal layers, in the figure, G1, G2, G3 and G4 are all gate traces, G1 and G3 are first gate lines, G2 and G4 are second gate lines, G1 and G3 are located on the first metal layer, and G2 and G4 are located on the second metal layer, wherein a is the width of a part which is transversely stacked to form a capacitor, b is the width of a part which is longitudinally stacked to form a capacitor, s is the longitudinal distance between a part which is stacked by G1 and G2 to form a capacitor and a part which is stacked by G3 and G4 to form a capacitor, p is the distance which is more from the part which is stacked by G3 and G4 to form a capacitor than from the transverse side of the part which is stacked by G1 and G2 to form a capacitor, and b is the overlapping width of the longitudinal part which is stacked by G1 and G2 to form a. Taking the size X3X of the unit pixel unit as an example, the capacitance of the grid wiring of the unit pixel is Cg_pThe values of a and b can be calculated as follows:
formula (3) can be obtained according to capacitance calculation formulas (1) and (2), wherein C is the capacitance,ris dielectric constant, S is the area of two electrode plates facing each other, k is the constant of electrostatic force, d is the distance between the two electrode plates,0is the dielectric constant in vacuum. Referring to fig. 4, d is the thickness of the insulating layer between two metal layers, which can be derived as follows:
a＝Cg_pd/X0 r…(4)
because G3, G4 are located at the outer circles of G1, G2 tracks, the length of one side of the horizontal part of the stack of G3, G4 is more than that of the horizontal part of the stack of G1, G2 by p, so that G1, G2 need to stack the longitudinal part for compensation, G1, G2 are two adjacent gate tracks, so the size of the related longitudinal pixel unit is 2 × 3 × 6 × and thus it can be derived:
through the above calculation formula and some specific parameters, the values of the line widths a and b of the stacked part can be calculated, taking a pixel unit of 4.5 inches as an example, by using the scheme, the load of the notch area and the normal area can be the same by calculating the horizontal overlapped line width to be 10 um; if the method of adding the virtual thin film transistor is used, the line width of the grid routing is 24 um; assuming that there are 100 rows of pixel cells missing from the notch area, the present invention can save 100 x (24-10) um to 1.4mm of vertical space. The gate lines in the figures are for illustration only and are intended to fall within the scope of the present invention regardless of the number of gate lines.
When the gate traces are distributed on the same metal layer, in the figure, G1 and G3 are gate lines located on the first metal layer, G2 and G4 are second metal layer traces, wherein G2 and G4 are electrically connected to the common electrode at the edge of the display area, G2 and G1 are stacked, G4 and G3 are stacked to form a capacitor structure, where a is the width of the portion where the capacitor is formed by transverse stacking, b is the width of the portion where the capacitor is formed by longitudinal stacking, s is the longitudinal spacing of the portion where the capacitor is formed by G1 and G2 stacking and the portion where the capacitor is formed by G3 and G4 stacking, p is the distance that the portion where the capacitor is formed by G3 and G4 stacking is more than the distance that the portion where the capacitor is formed by G1 and G2 stacking, and b is the overlapping width of the longitudinal portion where the capacitor is formed by G1 and G2 stacking. Taking the size X3X of the unit pixel unit as an example, the capacitance of the grid wiring of the unit pixel is Cg_pThe values of a and b can be calculated, and the calculation process is similar to that when the gate trace is distributed on different metal layers, which is not repeated herein.
Fig. 5 shows simulation results of gate driving circuits in the normal display region at various temperatures by stacking capacitances formed between two adjacent gate lines of the concave region, where S01, S02, S03, and S04 are gate signals of four levels adjacent to the normal portion, and S11, S12, S13, and S14 are gate signals of four levels adjacent to the notch portion.
Fig. 6 is a schematic diagram showing that two adjacent rows of gate traces are overlapped with each other only in the middle transverse direction to form a capacitor, the first gate line G1 is located on the first metal layer, the second gate line G2 is located on the second metal layer, G1 and G2 are adjacent gate traces, P10 is a corresponding pixel portion, and G1 and G2 are overlapped with each other only in the middle transverse direction to form a capacitor structure, which has the following advantages in practical implementation: the size calculation is more convenient. The gate lines in the figures are for illustration only and are intended to fall within the scope of the present invention regardless of the number of gate lines.
Fig. 7 is a schematic diagram showing two adjacent rows of gate traces overlapping in the transverse direction and the longitudinal direction to form a capacitor, the first gate line G1 is located on the first metal layer, the second gate line G2 is located on the second metal layer, and G1 and G2 are adjacent gate traces overlapping in the transverse direction and the longitudinal direction to form a capacitor structure. The gate lines in the figures are for illustration only and are intended to fall within the scope of the present invention regardless of the number of gate lines.
In fig. 6 and 7, the gate lines are both distributed on different metal layers, and when the gate lines are distributed on the same metal layer, in fig. 6 and 7, G1 is a gate line located on the first metal layer, G2 is a second metal layer line, and G2 is electrically connected to the common electrode at the edge of the display area, which can also compensate the load of the irregular area, so that the gate line of the irregular display area is close to the load of the gate line of the normal display area. The selection of the overlapping portions and the corresponding advantages of the different selections are also applicable to the solutions shown in fig. 6 and 7 and will not be described herein again.
In the liquid crystal display device provided by the invention, the load difference of the gate lines of the special-shaped screen is adjusted, so that the load of the special-shaped area can be effectively compensated, the load of the gate lines of the irregular display area is close to that of the gate lines of the normal display area, the gate driving parameters are consistent, the stability is ensured, the display uniformity is improved, and the planar layout space is saved.
Furthermore, it will be appreciated by those of ordinary skill in the art that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale, and that some details (e.g., number of gate lines in the example) are given to provide a thorough understanding of the present disclosure and should not be construed as limiting the scope of the present disclosure.
Also, it should be understood that the example embodiments are provided so that this disclosure will be thorough and will fully convey the scope to those skilled in the art. Numerous specific details are set forth such as examples of specific components, devices, and methods to provide a thorough understanding of the present disclosure. Those skilled in the art will understand that specific details need not be employed, that example embodiments may be embodied in many different forms and that example embodiments should not be construed as limiting the scope of the disclosure. In some example embodiments, well-known device structures and well-known technologies are not described in detail.
When an element or layer is referred to as being "on," "engaged to," "connected to" or "coupled to" another element or layer, it may be directly on, engaged, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly engaged to," "directly connected to" or "directly coupled to" another element or layer, there may be no intervening elements or layers present. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" and "directly between," "adjacent" and "directly adjacent," etc.). As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another element, region, layer or section. Terms such as "first," "second," and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A liquid crystal display device comprising:
a first substrate and a second substrate opposite to each other;
a liquid crystal layer between the first substrate and the second substrate;
a plurality of thin film transistors and pixel electrodes connected thereto on the first substrate;
a plurality of color filters on the second substrate; and
a plurality of gate lines connected to the plurality of thin film transistors, respectively for gating a corresponding row of the plurality of thin film transistors to apply a gray scale voltage;
wherein the first substrate comprises a plurality of sides and at least one of the sides comprises a notch,
the first metal layer and the second metal layer are arranged near the gap, the plurality of gate lines comprise a first gate line and a second gate line, the first gate line and the second gate line are used for connecting the thin film transistors in adjacent rows, and the first gate line and the second gate line are located on different metal layers and at least partially overlapped near the gap to form a capacitor.
2. The liquid crystal display device according to claim 1, wherein the first substrate and the second substrate each have a shape selected from one of the following shapes: rectangular, circular, oval, curved.
3. The liquid crystal display device according to claim 1, wherein the shape of the notch is one selected from the following shapes: rectangular, circular, oval, curved.
4. The liquid crystal display device according to claim 3, wherein the notch has a shape of an open rectangle including the first to third sides.
5. The liquid crystal display device according to claim 4, wherein a portion of the first metal layer in the vicinity of at least one of the first to third sides overlaps with a corresponding portion of the second metal layer.
6. The liquid crystal display device according to claim 5, wherein the first metal layer and the second metal layer partially overlap only in a lateral direction.
7. The liquid crystal display device according to claim 5, wherein an overlapping distance in a length direction and an overlapping distance in a width direction of the first metal layer and the second metal layer are determined according to a distribution of gate line capacitance.
8. The liquid crystal display device according to claim 5, wherein a line width of the gate line on the first metal layer is the same as a line width on the second metal layer.
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| KR102276995B1 (en) * | 2015-02-12 | 2021-07-21 | 삼성디스플레이 주식회사 | Nonsquare display |
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| US10354578B2 (en) * | 2016-04-15 | 2019-07-16 | Samsung Display Co., Ltd. | Display device |
| CN107424551B (en) * | 2017-05-25 | 2021-01-29 | 上海天马微电子有限公司 | Array substrate, special-shaped display and display device |
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