CN110568679B - Display panel - Google Patents

Abstract

The invention discloses a display panel, which is provided with an active area and a peripheral area, wherein the shape of the active area is special-shaped. The display panel includes a substrate, a plurality of pixel units, a plurality of gate lines, and at least one redundant thin film transistor. The pixel units are arranged on the substrate and positioned in the active area. The gate lines are disposed on the substrate, each gate line is coupled to one or more of the pixel units, and the number of the pixel units coupled to a first gate line of the gate lines is smaller than the number of the pixel units coupled to a second gate line of the gate lines. The redundant thin film transistor is positioned in the peripheral area and is coupled to the first gate line. The display panel provided by the invention has the special-shaped active area and comprises a resistance or capacitance compensation function of the grid line, so that the problems of incorrect gray scale of a display picture and the like can be avoided.

Description

Display panel

Technical Field

The present invention relates to a display panel, and more particularly, to a display panel having an irregular active region.

Background

With the development of display panel manufacturing technology, nowadays, high-resolution display panels are already applied to wearable and handheld electronic products, such as smart watches, health bracelets, etc. On the other hand, the aesthetic requirements of consumers for electronic products are increasing, and display panels with special exterior designs are applied to electronic products. The display panel on these electronic products usually has a non-rectangular shape, such as a circle or other irregular shapes.

For example, fig. 1 is a schematic diagram of a conventional rectangular display panel, and fig. 2A and 2B respectively illustrate different aspects of a conventional irregular display panel. The display panels 100, 200A, 200B of fig. 1, 2A, and 2B include pixel rows (row) R (1) -R (n) respectively coupled to corresponding gate lines (not shown), wherein each pixel row R (1) -R (n) includes a plurality of pixels, and each pixel includes a tft and a pixel electrode. Because a gate line has a resistance and there is a parasitic capacitance (e.g., gate/source capacitance (Cgs) and gate/drain capacitance (Cgd) due to the thin film transistors TFT) between the gate line and the thin film transistors in the corresponding pixel row to which it is coupled, each gate line has its corresponding resistance-capacitance loading (RC loading). Since the active area 110 of the display panel 100 in fig. 1 is rectangular, each pixel row R (1) -R (n) includes the same number of pixels, so that the impedance-capacitance load of each gate line in the display panel 100 in fig. 1 is the same. Referring to fig. 2A and 2B, as shown in fig. 2A and 2B, the top portions of the display panels 200A and 200B of fig. 2A and 2B have a recess, and the top portions of the active regions 210A and 210B also have a shape corresponding to the recess. In addition, the difference between fig. 2A and fig. 2B is that the shape of the lower left and right corners of the active region 210A in fig. 2A is rectangular, and the shape of the lower left and right corners of the active region 210B in fig. 2B is arc. Therefore, in the display panel 200A of fig. 2A, the upper half of the active region 210A has the irregular regions 210A _ U, and in the display panel 200B of fig. 2B, the upper half and the lower half of the active region 210B have the irregular regions 210B _ U, 210B _ L, respectively. As shown in fig. 2A and 2B, the number of pixels in the pixel rows (e.g., the pixel row r (j)) in the irregular regions 210A _ U and 210B _ U is less than the number of pixels in the pixel rows (e.g., the pixel row r (i)) in the regular region (the region of the active region 210A other than the irregular region 210A _ U and the rectangular region of the active region 210B other than the irregular regions 210B _ U and 210B _ L), i.e., the pixel row r (j) includes a smaller number of tfts than the pixel row r (i), so that the parasitic capacitance on the gate line coupled to the pixel row r (j) is less than the parasitic capacitance on the gate line coupled to the pixel row r (i), and the impedance-capacitance load of the gate line coupled to the pixel rows (e.g., the pixel row r (j)) in the irregular regions 210A _ U and 210B _ U is different from the impedance-capacitance load of the gate line coupled to the pixel rows (e.g., the pixel rows r (j)) in the regular region The resistance-capacitance loading of the gate lines of the pixel rows R (i) may cause problems such as incorrect gray levels of the displayed image in some specific areas. Particularly, the irregular regions 210A _ U and 210B _ U include recesses, and the difference between the number of pixels in each pixel row of the irregular regions 210A _ U and 210B _ U and the number of pixels in each pixel row of the regular region is too large, so that the difference between the brightness of the display image in the active region at the two sides of the recesses and the brightness of the display image in the active region of the regular region is too large, resulting in poor gray scale display of the image. Therefore, how to make the impedance-capacitance load of the gate line in the irregular area including the recess equal to or similar to the impedance-capacitance load of the gate line in the regular area is a problem to be solved.

Disclosure of Invention

The present invention is directed to a display panel having a special-shaped active region and including a resistance or capacitance compensation function of a gate line, so as to avoid the generation of problems such as incorrect gray scale of a display screen.

In accordance with the above objectives, the present invention provides a display panel having an active area and a peripheral area, wherein the active area is shaped as an odd-shaped (odd-shaped). The display panel includes a substrate, a plurality of pixel units, a plurality of gate lines, and at least one redundant thin film transistor. The pixel units are arranged on the substrate and positioned in the active area. The gate lines are disposed on the substrate, each of the gate lines is coupled to one or more of the pixel units, and the number of the pixel units coupled to a first gate line of the gate lines is smaller than the number of the pixel units coupled to a second gate line of the gate lines. The redundant thin film transistor is positioned in the peripheral area and is coupled to the first gate line.

According to an embodiment of the present invention, the active region includes a first sub-region and a second sub-region, the first sub-region and the second sub-region are opposite to each other with a gap therebetween, and the redundant thin film transistor is disposed in the gap.

According to another embodiment of the present invention, the active region further includes a rectangular region, the first sub-region and the second sub-region are connected to a side of the rectangular region, and the second gate line is located in the rectangular region.

According to another embodiment of the present invention, the first gate line includes a first portion, a second portion and a third portion respectively located in the first sub-region, the gap and the second sub-region, wherein two ends of the second portion are respectively coupled to the first portion and the third portion, and the redundant tft is coupled to the second portion.

According to another embodiment of the present invention, the second portion of the first gate line includes a dual-layer trace structure.

According to another embodiment of the present invention, the dual-layer trace structure includes an upper layer trace and a lower layer trace, the upper layer trace is disposed above the lower layer trace, and the upper layer trace overlaps the lower layer trace in a vertical projection direction, wherein the vertical projection direction is perpendicular to the substrate.

According to another embodiment of the present invention, a third gate line of the gate lines includes a first portion, a second portion and a third portion, the first portion, the second portion and the third portion of the third gate line are respectively located in the first sub-area, the gap and the second sub-area, the second portion of the third gate line includes another double-layer routing structure, the another double-layer routing structure includes another upper-layer routing and another lower-layer routing, the another upper-layer routing is disposed above the another lower-layer routing, the another upper-layer routing overlaps the another lower-layer routing in a vertical projection direction, and a width of the upper-layer routing is different from a width of the another upper-layer routing.

According to another embodiment of the present invention, the display panel further includes a conductive layer disposed on the dual-layer trace structure and overlapping and insulated from the dual-layer trace structure in a vertical projection direction, wherein the vertical projection direction is perpendicular to the substrate.

According to another embodiment of the present invention, the conductive layer is a common electrode.

According to another embodiment of the present invention, the display panel further includes a common electrode signal trace disposed between an edge of the active region and an edge of the display panel, and the redundant thin film transistor is disposed between the edge of the active region and the common electrode signal trace.

The invention has the advantages that the problems of incorrect gray scale of a display picture and the like can be avoided by carrying out resistance or capacitance compensation on the gate line of the display panel with the special-shaped active area.

Drawings

For a more complete understanding of the embodiments and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIGS. 1, 2A and 2B are schematic views of a conventional display panel having a profiled active region;

FIG. 3 is a schematic diagram of a display panel with a specially shaped active region according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of the gate driving circuit of FIG. 3;

FIG. 5 is a partially enlarged schematic view of the display panel of FIG. 3;

FIGS. 6A-6D respectively illustrate pixel cell arrangements and device configurations in different regions of the active region of FIG. 3;

FIGS. 7A-7C respectively illustrate pixel cell arrangements and device configurations in different regions of the active region of FIG. 3;

FIGS. 8A to 8E are schematic layout diagrams of stages of fabricating TFTs and redundant TFTs according to an embodiment of the present invention;

fig. 9A is a layout diagram of a dual-layer routing structure according to an embodiment of the invention;

FIG. 9B is a cross-sectional view of the partial layout of FIG. 9A taken along line V-V;

fig. 10 is a schematic partial layout view of a plurality of traces and auxiliary traces in a peripheral region between the irregular region and the recessed region of fig. 3;

FIG. 11 is a cross-sectional view of the partial layout of FIG. 10 taken along line A-A;

FIG. 12 illustrates pixel cell arrangements and element configurations of the display device of FIG. 3 in a local portion of a sub-region of an active area;

FIG. 13 is a cross-sectional view of the partial structure of FIG. 12 taken along line B-B; and

FIG. 14 is a schematic diagram of a display device according to some embodiments of the invention.

Detailed Description

Embodiments of the invention are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The embodiments discussed and disclosed are merely illustrative and are not intended to limit the scope of the invention.

It will be understood that, although the terms "first," "second," "third," …, etc. may be used herein to describe various elements, components, regions and/or sections, these elements, components, regions and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region and/or section from another element, component, region and/or section.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the claims. The singular forms "a", "an" and "the" may be used to refer to a plurality of forms unless otherwise limited. Furthermore, the spatially relative terms are used to describe various orientations of the elements in use or operation and are not intended to be limited to the orientations shown in the figures. Elements may also be oriented in other ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted in a similar manner.

Reference numerals and/or letters may be repeated among the various embodiments for simplicity and clarity of illustration, but are not intended to indicate a resulting relationship between the various embodiments and/or configurations discussed.

As used herein, the term "coupled" may mean that two or more elements are in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, and "coupled" may mean that two or more elements operate or act in conjunction with each other.

Referring to fig. 3, fig. 3 is a schematic view of a display panel 300 according to some embodiments of the invention. The display panel 300 may be a liquid crystal display panel such as a Twisted Nematic (TN) type, an in-plane switching (IPS) type, an FFS (fringe-field switching) type, a VA (vertical alignment) type, a reflective (reflective) type, or a transflective (transflective) type, or an Organic Light Emitting Diode (OLED) type display panel, but is not limited thereto. The display panel 300 includes a substrate 302 having an active area 310 and a peripheral area 320, a plurality of pixel units (not shown) disposed on the substrate 302 and in the active area 310, and a gate driving circuit 330 disposed on the substrate 302 and in the peripheral area 320 for generating a scan signal and transmitting the scan signal to the gate lines, such that the pixel units in the active area 310 are driven by the scan signal to display an image at a specific time.

In some embodiments, the display panel 300 is a System On Glass (SOG) panel. That is, the gate driving circuit 330 is formed on the substrate 302 of the display panel 300. Thus, the same process can be used to fabricate the electronic devices in the gate driving circuit 330 and the electronic devices (such as but not limited to the thin film transistors) in the active region 310. In other embodiments, the gate driving circuit 330 may be located in a chip, and the chip may be bonded to the pads disposed on the substrate 302 by Chip On Glass (COG), Tape Automated Bonding (TAB), Chip On Film (COF), or the like, so as to provide the scan signals to the gate lines.

In addition, the display panel 300 is an odd-shaped (odd-shaped) display panel. As shown in fig. 3, an edge 300E of the display panel 300 is irregular and has a recess (notch)300N on a top side of the display panel 300. The active region 310 is a profiled active region, and the top side of the active region 310 also has a recess 310N, which is disposed corresponding to the first recess 300N. Herein, the recess 310N of the active region 310 and the recess 300N of the display panel 300 may also be referred to as a first recess and a second recess, respectively. In addition, the shapes of the upper left end and the upper right end of the display panel 300 and the active region 310 are arc shapes instead of right angles, but not limited thereto. As shown in fig. 3, the active region 310 includes a regular region (e.g., a rectangular region) 310L and an irregular region 310U. If the size of each pixel unit in the active region 310 is the same, the number of pixel units in each pixel row in the regular region 310L of the active region 310 is the same, and the irregular region 310U of the active region 310 includes the sub-regions 310U1 and 310U 2. The sub-regions 310U1, 310U2 are opposite to each other with a gap 310S therebetween, and the sub-regions 310U1, 310U2 are respectively disposed at upper left and upper right of the rectangular region 310L and connect upper side edges of the rectangular region 310L. Thus, the combination of the sub-regions 310U1, 310U2 and the rectangular region 310L can form the active region 310 with the recess 310N, and the right side of the sub-region 310U1, the left side of the sub-region 310U2 and a portion of the upper side of the rectangular region 310L form the edge of the recess 310N. As shown in fig. 3, the pixel units are not disposed in the gaps 310S between the sub-regions 310U1 and 310U2, and therefore, in the irregular region 310U, each pixel row includes a plurality of pixel units located in the sub-regions 310U1 and 310U2, that is, a part of the pixel units in each pixel row are located in the sub-region 310U1, the rest of the pixel units are located in the sub-region 310U2, and the pixel units are not disposed in the gaps 310S (or the recesses 310N). The number of pixel units in each pixel row located in the irregular area 310U is smaller than the number of pixel units in each pixel row located in the regular area 310L. Herein, the sub-regions 310U1, 310U2 may also be referred to as a first sub-region and a second sub-region, respectively. In addition, the number of pixel units in different pixel rows in the irregular area 310U is not exactly the same, but is not limited thereto. In the irregular area 310U, since the arrangement space of the topmost pixel row is smaller than that of the bottommost pixel row, the number of pixel units in the topmost pixel row is smaller than that in the bottommost pixel row. In a variant embodiment, the number of pixel cells in different pixel rows in the irregular area 310U may be identical. In summary, the display panel 300 includes pixel rows R (1) -R (N), wherein the pixel rows R (1) -R (N ') are disposed in the regular region 310L of the active region 310, and the number of pixel units in each of the pixel rows R (1) -R (N ') is M, and the pixel rows R (N ' +1) -R (N) are disposed in the irregular region 310U of the active region 310, and the number of pixel units in each of the pixel rows R (N ' +1) -R (N) is less than M, wherein N ' is a positive integer less than N. In addition, in some embodiments, the pixel units in at least some of the pixel rows R (N' +1) -R (N) are different. In the following description, the maximum number of pixel units of a pixel row is M, and the maximum number of pixel units of a pixel column (column) is N.

Referring to fig. 3 and fig. 4, fig. 4 is a schematic diagram of the gate driving circuit 330 of fig. 3. As shown in fig. 4, the gate driving circuit 330 is disposed in the peripheral region 320. The gate driving circuit 330 includes N shift registers 332(1) -332(N) for respectively and sequentially outputting the scan signals OUT (1) -OUT (N) to the gate lines SL (1) -SL (N). For example, in the same frame period (frame period), the 1 st stage shift register 332(1) outputs the 1 st stage scan signal OUT (1) to the gate line SL (1), then the 2 nd stage shift register 332(2) outputs the 2 nd stage scan signal OUT (2) to the gate line SL (2) after a time t, then the 3 rd stage shift register 332(3) outputs the 3 rd stage scan signal OUT (3) to the gate line SL (3) after a time t, and so on until the nth stage shift register 332(N) outputs the nth stage scan signal OUT (N) to the gate line SL (N). In another embodiment, the gate driving circuit 330 can sequentially output the scan signals OUT (1) -OUT (n) to the gate lines SL (1) -SL (n) in the active region 310 in opposite directions. For example, during the same frame period, the nth stage shift register 332(N) outputs the nth stage scan signal OUT (N) to the gate line SL (N), after a time t, the (N-1) th stage shift register 332(N-1) outputs the (N-1) th stage scan signal OUT (N-1) to the gate line SL (N-1), after a time t, the (N-2) th stage shift register 332(N-2) outputs the (N-2) th stage scan signal OUT (N-2) to the gate line SL (N-2), and so on until the 1 st stage shift register 332(1) outputs the 1 st stage scan signal OUT (1) to the gate line SL (1).

In fig. 3, the gate driving circuit 330 includes a first gate driving circuit 330A and a second gate driving circuit 330B respectively disposed at two opposite sides of the active region 310. Therefore, one of the first gate driving circuit 330A and the second gate driving circuit 330B may include odd-numbered shift registers 332(1), 332(3), …, and 332(N-1) for respectively and sequentially outputting odd-numbered scan signals OUT (1), OUT (3), …, and OUT (N-1) to odd-numbered gate lines SL (1), SL (3), …, and SL (N-1), and the other of the first gate driving circuit 330A and the second gate driving circuit 330B includes even-numbered shift registers 332(2), (332) (4), (…), and 332(N) for respectively and sequentially outputting even-numbered scan signals OUT (2), OUT (4), …, and OUT (N) to even-numbered gate lines SL (2), SL (4), …, and SL (N), but the invention is not limited thereto. In another embodiment, both ends of each of the gate lines SL (1) -SL (N) are coupled to the first gate driving circuit 330A and the second gate driving circuit 330B, and each of the first gate driving circuit 330A and the second gate driving circuit 330B includes N shift registers 332(1) -332(N) for respectively outputting the scan signals OUT (1) -OUT (N) to the gate lines SL (1) -SL (N). In other words, two ends of each gate line SL (1) -SL (n) receive the corresponding scan signals output by the first gate driving circuit 330A and the second gate driving circuit 330B simultaneously, so as to improve the driving capability.

In the embodiment of fig. 3, the gate driving circuit 330 includes a first gate driving circuit 330A and a second gate driving circuit 330B, which are respectively disposed on two opposite sides of the active region 310, but not limited thereto. In an alternative embodiment, the gate driving circuit 330 may be disposed on only one side of the active region 310 and includes N shift registers 332(1) -332(N) for outputting the scan signals OUT (1) -OUT (N) to the gate lines SL (1) -SL (N).

Referring to fig. 5 and 6A, fig. 5 is a partially enlarged schematic view of the display panel of fig. 3, and the gate driving circuit 330 is omitted, and fig. 6A shows a partial pixel unit arrangement and an element configuration in a regular region 310L of the active region 310, where the position of the partial pixel unit arrangement and the element configuration corresponds to the region a in fig. 5. As shown in fig. 5, the recess 300N of the display panel 300 includes first to third side edges 300N _ S1, 300N _ S2 and 300N _ S3, the recess 310N of the active region 310 includes first to third side edges 310N _ S1, 310N _ S2 and 310N _ S3, wherein the first side edge 300N _ S1 and the third side edge 300N _ S3 are respectively connected to two opposite ends of the second side edge 300N _ S2, the first side edge 310N _ S1 and the third side edge 310N _ S3 are respectively connected to two opposite ends of the second side edge 310N _ S2, and the second side edges 300N _ S2 and 310N _ S2 are bottom edges of the recesses 300N and 310N. As described above, the right side of the sub-region 310U1, the left side of the sub-region 310U2, and a portion of the upper side of the rectangular region 310L form the edge of the recess 310N, so the first to third sides 310N _ S1, 310N _ S2, and 310N _ S3 of the recess 310N of the active region 310 can also be the right side of the sub-region 310U1, a portion of the upper side of the rectangular region 310L, and the left side of the sub-region 310U2, respectively. As shown in FIG. 6A, in the regular region 310L of the active area 310, each pixel column C (1) -C (M) and each pixel row (e.g., pixel row R (i)₁)、R(i₁+1)) of the sameThere are a thin film transistor TFT and a pixel electrode PX. With pixel column C (1) and pixel row R (i)₁) For example, the TFT is coupled to the data line DL (1) and the gate line SL (i)₁) According to the gate line SL (i)₁) The supplied scan signal (i.e., the scan signal OUT (i))₁) Controls whether or not the data signal supplied from the data line DL (1) is input to the pixel electrode PX. The thin film transistor TFT may be an amorphous silicon (amorphous silicon) thin film transistor, a Low Temperature Polysilicon (LTPS) thin film transistor, an Indium Gallium Zinc Oxide (IGZO) thin film transistor, or other suitable thin film transistors. In the regular region 310L of the active region 310, each pixel row has the same number of pixel units (in other words, the same number of thin film transistors and the same number of pixel electrodes). In addition, in the peripheral region 320 (i.e., between the edge 310E of the active region 310 and the edge 300E of the display panel 300), a Common Electrode signal trace VL for providing a Common voltage signal to a Common Electrode (Common Electrode) (not shown in fig. 6A) of each pixel unit may be provided, so that the liquid crystal molecules in the pixel units are twisted by the electric field generated between the corresponding pixel Electrode PX and the Common Electrode. For example, the common electrode signal trace VL can be a closed loop trace (also called a common voltage loop (Vcom Ring)), which surrounds the active region 310, but not limited thereto. In an alternative embodiment, the common electrode signal trace VL may be a non-closed trace.

Fig. 6B shows the pixel unit arrangement and the element configuration in the area B corresponding to fig. 5. As shown in fig. 6B, in the area B corresponding to fig. 5, the topmost pixel row in the regular area 310L of the active area 310 is the pixel row R (N '), and the peripheral area 320 between the sub-areas 310U1 and 310U2 has the gate lines SL (N ' +1) -SL (N) and the common electrode signal trace VL, each gate line SL (N ' +1) -SL (N) extends into the sub-areas 310U1 and 310U2 on the left and right sides of the gap 310S (or the recess 310N) to couple to the pixel rows R (N ' +1) -R (N) (not shown), respectively, wherein a part of the pixel cells in each pixel row R (N ' +1) -R (N) is located in the sub-area 310U1, and the rest of the pixel cells are located in the sub-area 310U 2.

As shown in FIG. 6B, each pixel column C (j)₁)-C(j₁+7) and the pixel row R (N') are arranged with the pixel cell (including the thin film transistor TFT and the pixel electrode PX) at the intersection, but each pixel column C (j)₁)-C(j₁And no pixel unit is correspondingly arranged at the intersection of the +7) and the pixel rows R (N' +1) -R (N). Therefore, in order to compensate for the phenomenon that the rc loading on each gate line SL (N '+ 1) -SL (N) is not consistent with the rc loading on the gate lines SL (1) -SL (N'), redundant Thin Film transistors (Dummy Thin Film transistors) may be disposed in the peripheral region 320 and coupled to one or more gate lines SL (N '+ 1) -SL (N) to add additional parasitic capacitance on the gate lines SL (N' +1) -SL (N). For example, in some embodiments, as shown in fig. 5 and 6B, redundant TFTs are disposed in the gaps 310S (or recesses 310N) between the sub-regions 310U1 and 310U2 of the active region 310, which are coupled to the gate line SL (N '+ 1) and the data line DL (j' +1), respectively₁)-DL(j₁+7). The structure of the redundant thin film transistor TFT 'may be the same as that of the thin film transistor TFT', and each redundant thin film transistor TFT 'also has parasitic capacitances such as a gate/source capacitance and a gate/drain capacitance for compensating the parasitic capacitance on the gate line SL (N' + 1). Similarly, the redundant thin film transistor TFT' may be an amorphous silicon thin film transistor, a low temperature polysilicon thin film transistor, an indium gallium zinc oxide thin film transistor, or other suitable thin film transistors.

As shown in fig. 6B, the common electrode signal trace VL is disposed between the gate lines SL (N '+ 1) and SL (N' +2), and the redundant thin film transistor TFT 'is coupled to the gate line SL (N' + 1). In other words, the redundant TFT' of fig. 6B is disposed between the second side 310N _ S2 of the recess 310N of the active region 310 and the common electrode signal trace VL, but not limited thereto. In an alternative embodiment, the redundant thin film transistor TFT' may be disposed between the common electrode signal trace VL and the second side 300N _ S2 of the recess 300N of the display panel 300. It should be noted that the arrangement of the redundant thin film transistor TFT' and the common electrode signal trace VL shown in fig. 6B are only examples, and are not intended to limit the scope of the present invention. For example, in other embodiments, the position of the common electrode signal trace VL can be adjusted (e.g., disposed between the gate lines SL (N ' +2) and SL (N ' +3), but not limited thereto), and/or at least two of the gate lines SL (N ' +1) -SL (N) are coupled to the redundant TFT ' in the gap 310S (or the recess 310N) between the sub-regions 310U1 and 310U2, so as to compensate for the parasitic capacitance on at least two of the gate lines SL (N ' +1) -SL (N). In addition, in other embodiments, the common electrode signal trace VL may not be disposed in the peripheral region 320 between the second side 300N _ S2 of the recess 300N of the display panel 300 and the second side 310N _ S2 of the recess 310N of the active region 310, and at least one of the gate lines SL (N '+ 1) -SL (N) is coupled to the redundant TFT' in the gap 310S (or the recess 310N) between the sub-regions 310U1 and 310U2 for compensating the parasitic capacitance on at least one of the gate lines SL (N '+ 1) -SL (N'). It should be noted that, in some embodiments, the gate lines SL (N ' +1) -SL (N) are not coupled to the redundant TFT ' in the peripheral region 320 (e.g., the region B in fig. 5) between the second side 300N _ S2 of the recess 300N of the display panel 300 and the second side 310N _ S2 of the recess 310N of the active region 310, but coupled to the redundant TFT ' (e.g., the embodiment shown in fig. 6C described later) near the first side 310N _ S1 of the recess 310N near the active region 310, and coupled to the redundant TFT ' (e.g., the embodiment shown in fig. 6D described later) near the third side 310N _ S3 of the recess 310N near the active region 310, so as to compensate for parasitic capacitances on the gate lines SL (N ' +1) -SL (N).

Fig. 6C shows the pixel cell arrangement and the element configuration in a local portion of the sub-region 310U1 of the active region 310, the position of which corresponds to the region C in fig. 5. As shown in fig. 6C, in the sub-region 310U1 of the active region 310, the number of pixel units in the upper pixel row is smaller than or equal to the number of pixel units in the lower pixel row. For example, as shown in FIG. 6C, pixel column R (i)₂The number of pixel units in +1) is less than that of the pixel row R (i)₂) The number of pixel units in (1). However, the invention is not limited thereto. In an alternative embodiment, the number of pixel units in the pixel rows from bottom to top in the sub-region 310U1 can be sequentially decreased and increasedIncreasing, equal to each other, or varying irregularly.

As shown in fig. 5 and fig. 6C, redundant TFTs are disposed in the peripheral region 320 of the first side 310N _ S1 of the recess 310N near the active region 310, and are coupled to at least some of the gate lines SL (N '+ 1) -SL (N) to compensate for parasitic capacitance on at least some of the gate lines SL (N' +1) -SL (N). For example, the gate line SL (i) in FIG. 6C₂+1) and data line DL (j)₂+4)-DL(j₂+7) and gate line SL (i)₂+2) and data line DL (j)₂)-DL(j₂+3) are coupled to redundant TFT' at the intersection to compensate the gate line SL (i)₂+1)、SL(i₂+2) on the substrate. In addition, in the embodiment of fig. 6C, the common electrode signal trace VL is disposed between the first side 300N _ S1 of the recess 300N of the display panel 300 and the first side 310N _ S1 of the active region 310, and the redundant thin film transistor TFT' is disposed between the first side 310N _ S1 of the recess 310N of the active region 310 and the common electrode signal trace VL, but not limited thereto. In a variant embodiment, the gate line SL (i)₂+1)、SL(i₂+2) may be coupled to the redundant thin film transistor TFT' after traversing the common electrode signal trace VL to the right. In addition, in other embodiments, the common electrode signal trace VL may not be disposed in the peripheral region 320 between the first side 300N _ S1 of the recess 300N of the display panel 300 and the first side 310N _ S1 of the recess 310N of the active region 310.

Fig. 6D shows the pixel cell arrangement and the element configuration in a local portion of the sub-region 310U2 of the active region 310, the position of which corresponds to the region D in fig. 5. As shown in fig. 6D, in the sub-region 310U2 of the active region 310, the number of pixel units in the upper pixel row is less than or equal to the number of pixel units in the lower pixel row. For example, as shown in FIG. 6D, pixel column R (i)₃The number of pixel units in +1) is less than that of the pixel row R (i)₃) The number of pixel units in (1). However, the invention is not limited thereto. In various embodiments, the number of pixel units in the pixel rows from bottom to top in the sub-region 310U2 may decrease, increase, be equal to each other, or vary irregularly.

Similar to the arrangement of the redundant thin film transistors shown in fig. 6C, the redundant thin film transistors TFT ' are disposed in the peripheral region 320 of the third side 310N _ S3 of the recess 310N near the active region 310, and are coupled to at least some of the gate lines SL (N ' +1) -SL (N) to compensate for the parasitic capacitance on at least some of the gate lines SL (N ' +1) -SL (N). For example, the gate line SL (i)₃+1) and data line DL (j)₃)-DL(j₃+3) and gate line SL (i)₃+2) and data line DL (j)₃+4)-DL(j₃+7) are coupled to redundant TFT' at the intersection to compensate the gate line SL (i)₃+1)、SL(i₃+2) on the substrate. In addition, in the embodiment of fig. 6D, the common electrode signal trace VL is disposed between the third side 300N _ S3 of the recess 300N of the display panel 300 and the third side 310N _ S3 of the recess 310N of the active region 310, and the redundant thin film transistor TFT' of fig. 6D is disposed between the third side 310N _ S3 of the recess 310N of the active region 310 and the common electrode signal trace VL, but not limited thereto. In an alternative embodiment, the gate line L (i)₃+1)、SL(i₃+2) may be coupled to the redundant thin film transistor TFT' after traversing the common electrode signal trace VL to the left. In addition, in other embodiments, the common electrode signal trace VL may not be disposed in the peripheral region 320 between the third side 300N _ S3 of the recess 300N of the display panel 300 and the third side 310N _ S3 of the recess 310N of the active region 310.

The combination of fig. 6B-6D combines a pixel cell arrangement in each part of the irregular region 310U of the active region 310 and a gate line arrangement in each part of the gap 310S between the sub-regions 310U1 and 310U 2. In addition, each gate line SL (N ' +1) -SL (N) includes a first portion, a second portion and a third portion respectively located in the sub-region 310U1, the gap 310S and the sub-region 310U2, wherein the first portion and the third portion are respectively located in the sub-regions 310U1 and 310U2, the second portion is located in the gap 310S (or the recess 310N) between the sub-regions 310U1 and 310U2, and both ends of the second portion of each gate line SL (N ' +1) -SL (N) are respectively coupled to the first portion and the third portion of the corresponding gate line SL (N ' +1) -SL (N) respectively located in the sub-regions 310U1 and 310U 2. Herein, each gridThe second portion of the gate line SL (N '+ 1) -SL (N) may also be referred to as the trace WR (N' +1) -WR (N), and thus the gate line SL (N '+ 1) -SL (N) in fig. 6B may also be referred to as WR (N' +1) -WR (N). A second portion of at least one of the gate lines SL (N '+ 1) -SL (N) is coupled to the redundant TFT' disposed in the gap 310S (or the recess 310N) between the sub-regions 310U1 and 310U 2. The redundant TFT' is preferably located in at least one of a region near the left side (i.e., near the right side of the sub-region 310U 1) in the gap 310S (or the recess 310N) (as in the embodiment of fig. 6C), a region near the right side (i.e., near the left side of the sub-region 310U 2) (as in the embodiment of fig. 6D), and a region near the lower side (i.e., near a portion of the upper side of the rectangular region 310L) (as in the embodiment of fig. 6B), but is not limited thereto. For example, the redundant TFTs TFT' may be located in two regions of the gap 310S (or the recess 310N) between the sub-regions 310U1 and 310U2 near the left side and the right side, respectively, or located in three regions of the gap 310S (or the recess 310N) between the sub-regions 310U1 and 310U2 near the left side, the right side, and the lower side, respectively. As shown in fig. 6B to 6D, the common electrode signal trace VL is disposed between the edge 300E of the display panel 300 and the edge 310E of the active region 310. In other words, the common electrode signal trace VL is disposed in the peripheral region 320 between the side of the recess 300N of the display panel 300 (including the first to third side edges 300N _ S1, 300N _ S2, 300N _ S3) and the side of the recess 310N of the active region 310 (including the first to third side edges 310N _ S1, 310N _ S2, 310N _ S3), so that the redundant thin film transistor TFT' can be further disposed between the edge 310E of the active region 310 and the common electrode signal trace VL. In other words, the redundant thin film transistors TFT' may be further disposed in the peripheral region 320 between the side edges (including the first to third side edges 310N _ S1, 310N _ S2, 310N _ S3) of the recess 310N of the active region 310 and the common electrode signal trace VL, but not limited thereto. In addition, the number of the redundant thin film transistors TFT 'coupled to different gate lines of the gate lines SL (N' +1) to SL (N) may not be completely the same, but is not limited thereto. In an alternative embodiment, the number of the redundant thin film transistors TFT 'coupled to each of the gate lines SL (N' +1) to SL (N) may be the same. As shown in fig. 6C, the display panel 300 is viewed from the left half sideGate line SL (j)₂+1)、SL(j₂+2) the first portion in the sub-region 310U1 extends into the gap 310S (or the recess 310N) and is coupled to the trace WR (i) respectively₂+1)、WR(i₂+2) (trace WR (i)₂+1)、WR(i₂+2) may also be regarded as gate lines SL (j) respectively₂+1)、SL(j₂+2) of the sub-regions 310U2 on the right side of the display panel 300 and respectively coupled to the gate lines SL (j) located in the sub-regions 310U2₂+1)、SL(j₂+2) of the third portion (not shown). And, as shown in fig. 6D, the gate lines SL (j) are viewed from the right side of the display panel 300₃+1)、SL(j₃+2) the third portion in the sub-region 310U2 extends into the gap 310S (or the recess 310N) and is coupled to the trace WR (i) respectively₃+1)、WR(i₃+2) (trace WR (i)₃+1)、WR(i₃+2) can be regarded as gate lines SL (j) respectively₃+1)、SL(j₃+2) of the sub-regions 310U1 and which are respectively coupled to the gate lines SL (j) in the sub-regions 310U1 at the left half side of the display panel 300₃+1)、SL(j₃+2)) of the first portion (not shown). Although not shown in fig. 6C and 6D, it can be directly understood from the contents of fig. 6B to 6D that the first portion and the third portion of the other gate lines in the gate lines SL (N '+ 1) -SL (N) in the sub-regions 310U1 and 310U2 are also correspondingly coupled to the other traces in the trace WR (N' +1) -WR (N) in the gap 310S (or the recess 310N). In addition, in some embodiments, the widths of WR (N '+ 1) -WR (N) may be respectively the same as the widths of the corresponding gate lines in the active region 310 (i.e., the widths of the gate lines SL (N' +1) -SL (N) in the first and third portions of the sub-regions 310U1 and 310U 2), but not limited thereto. In other embodiments, the width of at least a portion WR (N ' +1) -WR (N) may be different from the width of the corresponding gate line in the active region 310 (i.e., the widths of the first portion and the third portion of the gate lines SL (N ' +1) -SL (N) in the sub-regions 310U1 and 310U 2), so as to adjust the resistance of at least a portion of the gate lines SL (N ' +1) -SL (N), but not limited thereto. For example, trace WR (i)₂+1)、WR(i₂+2) may have widths greater than gate lines SL (j), respectively₂+1)、SL(j₂+2) width in the active area 310 to lower the gate line SL (j)₂+1)、SL(j₂+2) resistance value. Since the top sides of the display panel 300 and the active region 310 have the recesses 300N and 310N, respectively, after the first portion of the gate line SL (N ' +1) -SL (N) extends from the sub-region 310U1 to the gap 310S (or the recess 310N) to couple the corresponding trace WR (N ' +1) -WR (N), the trace WR (N ' +1) -WR (N) needs to pass through the gap 310S (or the recess 310N) between the sub-regions 310U1 and 310U2 to extend to the third portion of the sub-region 310U2 to couple the corresponding gate line SL (N ' +1) -SL (N), so that at least some of the trace WR (N ' +1) -WR (N) have different lengths. In particular, in some embodiments, at least some of the traces WR (N ' +1) -WR (N) have different widths to adjust the resistance of the gate lines SL (N ' +1) -SL (N), so that the impedance-capacitance loads of the gate lines SL (N ' +1) -SL (N) can be similar or the same.

Referring to fig. 7A, 7B and 7C, another embodiment of pixel cell arrangement and device configuration in a local portion of the peripheral region 320 between the sub-regions 310U1, 310U2 and 310U1, 310U2 of the active region 310 is shown, respectively. Fig. 7A, 7B, and 7C are similar to fig. 6C, 6D, and 6B, respectively, except that the second portion of the gate line in fig. 6A to 6C is a single-layer routing structure, and the second portion of the gate line in fig. 7A to 7C includes a double-layer routing structure to reduce the resistance of the gate line. For example, as viewed from an area near the sub-area 310U1 in the left half of the display panel 300, as shown in fig. 7A, the gate line SL (i)₂The second part of +1) comprises a trace WR (i)₂+1) and AW (i)₂+1), gate line SL (i)₂The second part of +2) comprises a trace WR (i)₂+2) and AW (i)₂+2). In this context, trace WR (i)₂+1)、WR(i₂+2) may also be referred to as the first trace, trace AW (i)₂+1)、AW(i₂+2) may also be referred to as a second trace. Second trace AW (i)₂+1)、AW(i₂+2) are connected to the first trace WR (i) respectively₂+1)、WR(i₂+2) at least partially overlapping to form a dual layer routing structure AW (i)₂+1)/WR(i₂+1) and AW (i)₂+2)/WR(i₂+2). In FIG. 7A, trace WR (i)₂+1)、WR(i₂+2) the respective travel paths are extended a distance after the gap 310S (or the recess 310N)Line AW (i)₂+1)、AW(i₂+2) overlap to form a double-layer wiring structure, i.e., gate line SL (i)₂A part of the second portion of +1) and the gate line SL (i)₂+2) is a double-layer routing structure, but not limited thereto. In a variant embodiment, the trace WR (i)₂+1)、WR(i₂+2) can be connected to the trace AW (i) at the side of the gap 310S (or the recess 310N), respectively₂+1)、AW(i₂+2) overlap to form a double-layer wiring structure, i.e. gate line SL (i)₂The second part of +1) and the gate line SL (i)₂The second portions of +2) may be both double-layer routing structures. In summary, at least a portion of the second portion of the gate line is a dual-layer trace structure. The double-layer wiring structure comprises an upper layer wiring and a lower layer wiring which are respectively formed by different conductor layers. For example, the dual layer trace structure AW (i)₂+1)/WR(i₂+1) the lower layer trace and the upper layer trace can be the trace WR (i)₂+1) and trace AW (i)₂+1) and may be formed from different conductor layers (e.g., metal layers), respectively. Routing AW (i)₂+1)、AW(i₂+2) pass through the respective contacts PL (i)₂+1)、PL(i₂+2) is coupled to the trace WR (i)₂+1)、WR(i₂+2), and these traces AW (i)₂+1)、AW(i₂+2) are also respectively coupled to the traces WR (i) on the right side of the display panel 300 through the contacts₂+1)、WR(i₂+2) (not shown). Thus, the dual-layer trace structure AW (i)₂+1)/WR(i₂+1) and AW (i)₂+2)/WR(i₂+2) the upper trace and the lower trace are configured in parallel, and the gate line SL (I)₂+1)、SL(i₂+2) resistance value is thus reduced. And as viewed from an area near the sub-area 310U2 in the right half of the display panel 300, as shown in fig. 7B, the gate line SL (i)₃+1) comprises trace WR (i)₃+1) and AW (i)₃+1), gate line SL (i)₃+2) includes the trace WR (i)₃+2) and AW (i)₃+2) in which AW (i) is routed₃+1)、AW(i₃+2) are respectively connected with the trace WR (i)₃+1)、WR(i₃+2) at least partially overlapping to form a dual layer routing structure AW (i)₃+1)/WR(i₃+1) and AW (i)₃+2)/WR(i₃+2). Routing AW (i)₃+1)、AW(i₃+2) pass through the contacts PR (i) respectively₃+1)、PR(i₃+2) is coupled to the trace WR (i)₃+1)、WR(i₃+2), and these traces AW (i)₃+1)、AW(i₃+2) are also respectively coupled to the traces WR (i) on the left half side of the display panel 300 by the contacts₃+1)、WR(i₃+2). Thus, the dual-layer trace structure AW (i)₃+1)/WR(i₃+1) and AW (i)₃+2)/WR(i₃+2) the upper trace and the lower trace are disposed in parallel, and the gate line SL (i)₃+1)、SL(i₃+2) resistance value is thus reduced. As seen from the bottom of the recess 310N near the active region 310, as shown in fig. 7C, the traces AW (N '+ 2) -AW (N' +5) at least partially overlap with the traces WR (N '+ 2) -WR (N' +5), respectively, to form a dual-layer trace structure AW (N '+ 2)/WR (N' +2) -AW (N '+ 5)/WR (N' +5), and the regions of the traces AW (N '+ 2) -AW (N' +5) near the sub-region 310U1 in the left half of the display panel 300 and the regions of the right half of the display panel 300 near the sub-region 310U2 are respectively coupled to the traces WR (N '+ 2) + (N' +5) by contacts. In this way, the upper layer trace and the lower layer trace in the dual-layer trace structure AW (N '+ 2)/WR (N' +2) -AW (N '+ 5)/WR (N' +5) are arranged in parallel, and the resistance of the gate line SL (N '+ 2) -SL (N' +5) is reduced. It should be noted that in the embodiment of fig. 7C, the second portion of the gate line SL (N' +1) includes a single-layer routing structure, but not limited thereto. In an alternative embodiment, the second portion of the gate line SL (N' +1) may include a dual-layer routing structure. In the above embodiment, the upper layer trace and the lower layer trace in the dual layer trace structure at least partially overlap in the vertical projection direction of the substrate 302 (i.e. the direction perpendicular to the substrate 302), that is, the dual layer trace structure includes the stacked upper layer trace and the stacked lower layer trace, so as to reduce the area occupied by the dual layer trace structure, but not limited thereto. In an alternative embodiment, the upper layer trace and the lower layer trace in the dual-layer trace structure may not overlap with each other (e.g., are parallel to each other), and two opposite ends of the upper layer trace are coupled to the corresponding lower layer trace through the contact, so as to form a parallel configuration.

Fig. 8A to 8E are schematic layout views of stages of manufacturing a pixel unit according to an embodiment of the invention, wherein fig. 8A to 8E include schematic layout views of a thin film transistor TFT and a redundant thin film transistor TFT'. First, as shown in fig. 8A, a metal layer M1 including gate electrodes and scan lines of the TFTs and the redundant TFTs TFT' is formed by depositing a metal on a substrate (not shown in fig. 8A) and performing photolithography and etching processes on the deposited metal. The material used to form the metal layer M1 may include, but is not limited to, chromium, tungsten, tantalum, titanium, molybdenum, aluminum, copper, and the like, or other similar elements, or alloys or compounds formed by any combination of the above metal elements.

Next, as shown in fig. 8B, a gate insulating layer (also referred to as a first insulating layer) (not shown in fig. 8B) is formed on the substrate (not shown in fig. 8B) and the metal layer M1, and then a semiconductor layer SE is formed on the gate insulating layer and on the gates of the thin film transistor TFT and the redundant thin film transistor TFT', respectively. The gate insulating layer extends from the active region 310 to the peripheral region 320, and covers the metal layer M1. The material forming the gate insulating layer may be silicon nitride or the like, and the material forming the semiconductor layer SE may be amorphous silicon, single crystal silicon, polycrystalline silicon, or the like.

After that, as shown in fig. 8C, the pixel electrode PX is formed in the pixel unit including the thin film transistor TFT. The material forming the pixel electrode PX may be, for example, Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), indium oxide (indium oxide), tin oxide (tin oxide), or other suitable transparent conductive material. Note that, since the redundant thin film transistor TFT ' is used only for compensating the resistance capacitance of the gate line and not for displaying an image, that is, the redundant thin film transistor TFT ' does not belong to any one pixel unit, a pixel electrode corresponding to the redundant thin film transistor TFT ' is not formed.

Next, as shown in fig. 8D, metal is deposited on the gate insulating layer, the metal layer M1, the semiconductor layer SE, and the pixel electrode PX, and the deposited metal is etched to form a metal layer M2 including source and drain electrodes and data lines of the thin film transistor TFT and the redundant thin film transistor TFT'. The material used to form the metal layer M2 may include, but is not limited to, chromium, tungsten, tantalum, titanium, molybdenum, aluminum, copper, and the like, or other similar elements, or alloys or compounds formed by any combination of the above metal elements.

Next, as shown in fig. 8E, a protective layer (also referred to as a second insulating layer) (not shown in fig. 8E) is formed on the metal layer M2, the semiconductor layer SE, and the pixel electrode PX, and a common electrode COM is formed on the protective layer. The passivation layer extends from the active region 310 to the peripheral region 320, and covers the thin film transistor TFT, the redundant thin film transistor TFT ', the data line, and the gate line, so as to provide protection and insulation effects for the thin film transistor TFT, the redundant thin film transistor TFT', the data line, and the gate line. The material used to form the protective layer may be silicon nitride, silicon oxynitride, or other similar materials. The common electrode COM and the pixel electrode PX form an internal electric field for controlling the rotation of the liquid crystal molecules. Similarly, the material forming the common electrode COM may be, for example, indium tin oxide, indium zinc oxide, indium oxide, tin oxide, or other suitable transparent conductive material.

It should be noted that the pixel units in fig. 8A to 8E are the pixel units of the fringe field switching display panel, and the pixel electrodes are below the common electrode, but the invention is not limited thereto. The embodiments of the present invention can also be applied to other types of display panels. For example, the display panel may be a liquid crystal display panel such as a twisted nematic (tn), a horizontal switching (horizontally switching), a fringe field switching (fringe field switching), a vertical alignment, a reflective display, or a transflective display, or an organic light emitting diode (oled) type display panel, but is not limited thereto.

In some embodiments, the upper layer trace and the lower layer trace in the dual-layer trace structure may at least partially overlap in a vertical projection direction of the substrate 302, so as to reduce an area occupied by the dual-layer trace structure. For example, trace WR (i) shown in FIG. 7A₂+1) and trace AW (i)₂+1) may overlap in the vertical projection direction of the substrate 302. Fig. 9A is a layout diagram of a dual-layer trace structure according to an embodiment of the invention, and fig. 9B is a partial layout of fig. 9A cut along V-VCross-sectional view of a wire. It should be noted that fig. 9A is the dual-layer trace structure AW (i) in fig. 7A₂+1)/WR(i₂+1) is an example, but not limited thereto. The layout of fig. 9A can be applied to the dual-layer routing structure of other gate lines in the gap 310S (or the recess 310N) between the sub-regions 310U1 and 310U2 as the cross-sectional structure of fig. 9B. In FIGS. 9A and 9B, trace WR (i)₂+1)、AW(i₂+1) belong to the metal layers M1 and M2, respectively, the gate insulating layer GI extends from the active region 310 to the peripheral region 320 and covers the metal layer M1, and the through hole TH1 passes through the gate insulating layer GI, so the metal layer M2 can be filled in the through hole TH1 to contact the metal layer M1, so that the metal layers M1 and M2 are electrically connected to each other, i.e., the trace WR (i)₂+1) and AW (i)₂+1), and the protection layer PV extends from the active region 310 to the peripheral region 320 and covers the metal layer M2. Referring to FIG. 7A, the gate line SL (i) is used₂+1) as an example, trace WR (i)₂+1) and trace AW (i)₂+1) belong to metal layers M1 and M2, respectively, and contact PL (i)₂+1) corresponds to through holes TH 1. In summary, the dual-layer trace structure of the gate line includes an upper trace and a lower trace, an insulating layer (e.g., a gate insulating layer GI) is disposed between the upper trace and the lower trace, a plurality of through holes (e.g., through holes TH1) are disposed in the insulating layer, each through hole exposes a portion of the lower trace, a portion of the through holes and another portion of the through holes overlap with two opposite ends of the upper trace in a vertical projection direction of the substrate 302, and the upper trace is electrically connected to the lower trace through a portion of the through holes and another portion of the through holes. It should be noted that the layout diagrams and the cross-sectional views of the dual-layer trace structure shown in fig. 9A and 9B are only examples, and are not intended to limit the scope of the invention. For example, in other embodiments, one end of the upper trace can be electrically connected to the lower trace through the bridge electrode, and the other end of the upper trace can be electrically connected to the lower trace through another bridge electrode to form a dual-layer trace structure, wherein the bridge electrode is electrically connected to one end of the upper trace and the lower trace through two vias respectively formed in at least one insulating layer covering the upper trace and at least one insulating layer covering the lower traceIn the insulating layer, one end of the upper layer trace and one part of the lower layer trace are respectively exposed, and the other bridging electrode is electrically connected to the other end of the upper layer trace and the lower layer trace through another two through holes, which are respectively formed in at least one insulating layer covering the upper layer trace and at least one insulating layer covering the lower layer trace, and respectively expose the other end of the upper layer trace and the other part of the lower layer trace, but not limited thereto.

In the embodiments of fig. 8A to 9B, the thin film transistor TFT and the redundant thin film transistor TFT' are bottom-gate (bottom-gate) structures; the wirings WR (N '+ 2) -WR (N) belong to the metal layer M1 together with the gate electrode of each of the thin film transistors TFT and the redundant thin film transistors TFT' in the display panel 300, and the wirings AW (N '+ 2) -AW (N) belong to the metal layer M2 together with the source electrode and the drain electrode of each of the thin film transistors TFT and the redundant thin film transistors TFT' in the display panel 300. That is, the routing lines WR (N '+ 2) -WR (N) may be simultaneously formed with the gate electrodes of each thin film transistor TFT and the redundant thin film transistor TFT' through the same process, and the routing lines AW (N '+ 2) -AW (N) may also be simultaneously formed with the source and drain electrodes of each thin film transistor TFT and the redundant thin film transistor TFT' in the display panel 300 through the same process. In other embodiments, the thin film transistor TFT and the redundant thin film transistor TFT' are in a top-gate (top-gate) structure; the trace AW (N '+ 2) -AW (N) is the same metal layer M1 as the source and drain electrodes of each TFT and TFT' in the display panel 300, and the trace WR (N '+ 2) -WR (N) is the same metal layer M2 as the gate electrode of each TFT and TFT' in the display panel 300.

In addition, the traces WR (N '+ 2) -WR (N) and AW (N' +2) -AW (N) can be fabricated simultaneously with the electronic components in the gate driving circuit 330. For example, the trace WR (N '+ 2) -WR (N) may be fabricated simultaneously with the gate of the transistor in the shift register 332(1) -332(N), and the auxiliary trace AW (N' +2) -AW (N) may be fabricated simultaneously with the source and drain of the transistor in the shift register 332(1) -332 (N).

FIG. 10 shows traces WR (N '+ 2) -WR (N' +5) and AW (N '+ 2) -AW (N' +5) in sub-area 3The positions of the partial layout in the gap 310S (or the recess 310N) between the 10U1 and the 310U2 may correspond to the positions of the gate lines SL (N '+ 2) -SL (N' +5) in fig. 6B. In other words, fig. 10 can be seen as replacing at least a part of the second portion of the gate line SL (N '+ 2) -SL (N' +5) (i.e., the trace WR (N '+ 2) -WR (N' +5)) of fig. 6B with the dual-layer trace structure AW (N '+ 2)/WR (N' +2) -AW (N '+ 5)/WR (N' + 5). In detail, the dual-layer routing structures AW (N '+ 2)/WR (N' +2) -AW (N '+ 5)/WR (N' +5) are part of the gate lines SL (N '+ 2) -SL (N' +5), respectively. In fig. 10, since the traces AW (N '+ 2) -AW (N' +5) respectively cover the traces WR (N '+ 2) -WR (N' +5) in the vertical projection direction of the substrate 302, the traces WR (N '+ 2) -WR (N' +5) are all represented by dotted lines, wherein the traces WR (N '+ 2) -WR (N' +5) respectively have a width W₁-W₄And traces AW (N '+ 2) -AW (N' +5) have widths W₁’-W₄’。

Fig. 11 is a cross-sectional view of the partial layout of fig. 10 taken along line a-a. As shown in fig. 11, the gate insulating layer GI covers the traces WR (N '+ 2) -WR (N' +5), and the traces AW (N '+ 2) -AW (N' +5) are located on the gate insulating layer GI and covered by the protective layer PV, and respectively overlap with the traces WR (N '+ 2) -WR (N' +5) in the vertical projection direction of the substrate 302. Any two adjacent tracks in the tracks WR (N '+ 2) -WR (N' +5) have a distance G between them₁₂、G₂₃Or G₃₄And a distance G is formed between any two adjacent tracks in the tracks AW (N '+ 2) -AW (N' +5)_12’、G_23’Or G_34’. Since the top sides of the display panel 300 and the active region 310 have the recesses 300N and 310N, respectively, and the first portion of the gate line SL (N ' +1) -SL (N) extends from the sub-region 310U1 to the gap 310S (or the recess 310N) between the sub-regions 310U1 and 310U2 for coupling with the corresponding trace WR (N ' +1) -WR (N), the trace WR (N ' +1) -WR (N) needs to pass through the gap 310S (or the recess 310N) between the sub-regions 310U1 and 310U2 to extend to the third portion of the sub-region 310U2 for coupling with the corresponding gate line SL (N ' +1) -SL (N), the lengths of at least some of the traces WR (N ' +1) -WR (N) are different. In the invention, because the upper layer wire and the lower layer wire in the double-layer conductive structure are connected in parallel, the width of at least one of the upper layer wire and the lower layer wire can be adjusted to change the corresponding gridThe resistance value of the pole line. For example, the second portion of at least some of the gate lines in the irregular area 310U includes a dual-layer trace structure, and the resistance of the gate lines SL (N' +1) -SL (N) can be adjusted by adjusting the width of at least one of the upper trace and the lower trace in the dual-layer conductive structure, so that the impedance-capacitance loads of the gate lines SL (1) -SL (N) can be similar or identical. For example, in the embodiments of fig. 10 and 11, the widths of the traces AW (N '+ 2) -AW (N' +5) are all different to adjust the resistance of the gate lines SL (N '+ 2) -SL (N' + 5). In this embodiment, the width W of the trace WR (N '+ 2) -WR (N' +5)₁-W₄Equal, and the width of trace AW (N '+ 2) -AW (N' +5) has a relation of W₁’>W₂’>W₃’>W₄', but not limited thereto. In a variation, the width W of trace WR (N '+ 2) -WR (N' +5)₁-W₄May not be identical, the widths of the traces AW (N '+ 2) -AW (N' +5) may decrease sequentially or vary irregularly. In addition, each two adjacent tracks in the tracks AW (N '+ 2) -AW (N' +5) have the same distance therebetween, i.e. G₁₂’＝G₂₃’＝G₃₄'. For example, the widths of the traces WR (N '+ 2) -WR (N' +5) can be 5 μm, and the widths W of the traces AW (N '+ 2) -AW (N' +5)₁’-W₄' may be 10 microns, 9 microns, 8 microns, and 7 microns, respectively, and each two adjacent traces in traces AW (N ' +2) -AW (N ' +5) have a pitch of 5 microns therebetween, but not limited thereto.

In summary, fig. 7A to 7C, 10 and 11 combine to form a pixel cell arrangement in each part of the irregular region 310U of the active region 310 and a gate line arrangement in each part of the gap 310S (or the recess 310N) between the sub-regions 310U1 and 310U 2. As shown in fig. 7A to 7C, fig. 10 and fig. 11, the second portion of at least some gate lines in the gap 310S (or the recess 310N) between the sub-regions 310U1 and 310U2 may include a dual-layer trace structure to reduce the resistance of the gate lines, and preferably, the widths of the upper layer traces and/or the widths of the lower layer traces in the dual-layer trace structure are different to adjust the resistance of the gate lines correspondingly. In addition, the upper layer trace and the lower layer trace in the dual layer trace preferably at least partially overlap in the vertical projection direction of the substrate 302, and opposite ends of the upper layer trace are respectively coupled to the corresponding lower layer trace through a contact (e.g., a via hole), so as to reduce the area occupied by the dual layer trace in the peripheral region 320.

Fig. 12 shows the pixel cell arrangement and the element configuration in the local part of the sub-region 310U2 of the active region 310, the position of which corresponds to the region E in fig. 5. As shown in FIG. 12, pixel row R (i)₄)-R(i₄+6) is gradually reduced. Further, a gate line SL (i)₄)-SL(i₄+7) extends from the sub-region 310U2 of the active region 310 to the peripheral region 320 and passes through the common electrode signal trace VL due to the gate line SL (i)₄)-SL(i₄+7) belongs to the metal layer M1, and the common electrode signal trace VL belongs to the metal layer M2, so that the gate line SL (i)₄)-SL(i₄+7) are insulated from each other by the common electrode signal trace VL. At the gate line SL (i)₄)-SL(i₄+7) after passing through the common electrode signal trace VL, trace AW (i)₄)-AW(i₄+7) and trace WR (i)₄)-WR(i₄+7) overlap and trace AW (i)₄)-AW(i₄+7) are respectively coupled to the trace WR (i) through the through holes TH1₄)-WR(i₄+7) to form a double layer trace AW (i)₄)/WR(i₄)-AW(i₄+7)/WR(i₄+7) and bent downward near the edge 300E of the display panel 300. It should be noted that fig. 12 is a partial view of the right half of the display panel 300, and the portion not shown in fig. 12 is the bent dual-layer trace AW (i)₄)/WR(i₄)-AW(i₄+7)/WR(i₄+7) extends to the left half side of the display panel 300 through the peripheral region 320 between the side of the recess 300N of the display panel 300 and the side of the recess 310N of the active region 310, and the trace AW (i) is routed₄)-AW(i₄+7) are respectively coupled to the trace WR (i) through the vias TH1₄)-WR(i₄+7), trace AW (i)₄)-AW(i₄+7) are respectively connected with the trace WR (i)₄)-WR(i₄+7) forms a parallel structure to lower the gate line SL (i)₄)-SL(i₄+7) resistance value. Then, routing WR (i)₄)-WR(i₄+7) to the leftExtend to couple gate lines SL (i) in sub-regions 310U1 of the active region 310₄)-SL(i₄+7) of the first portion. Fig. 12 is a partial view of the right half of the display panel 300, and a partial view of the left half of the display panel 300 can be obtained by turning 180 degrees the fig. 12 with the second direction D2 as an axis, but the invention is not limited thereto.

In some embodiments, a conductive layer may be disposed in the peripheral region 320 of the display panel 300, and at least a portion of the conductive layer overlaps the dual-layer routing structure in the vertical projection direction of the substrate 302. The conducting layer covers the upper layer of wiring in the double-layer wiring structure, at least one insulating layer is arranged between the conducting layer and the upper layer of wiring, so that the conducting layer and the upper layer of wiring are insulated from each other, and the conducting layer, the at least one insulating layer and the upper layer of wiring form a capacitor to increase the parasitic capacitance on the gate line. An example of disposing a conductive layer in the peripheral region 320 of the display panel 300 is shown in fig. 13, which is a cross-sectional view of the partial structure of fig. 12 along a line B-B. In FIG. 13, trace WR (i)₄+5)-WR(i₄+8) is covered by the gate insulating layer GI, trace AW (i)₄+5)-AW(i₄+8) is located on the gate insulating layer GI and covered by the protection layer PV, and is respectively connected to the traces WR (i) in the vertical projection direction of the substrate 302₄+5)-WR(i₄+8) overlap. In addition, the conductive layer CE is located on the protection layer PV and connected to the trace WR (i)₄+5)-WR(i₄+8), and is electrically connected to the Common Electrode signal trace VL through the through hole TH2, so that the Common Electrode signal trace VL provides a Common voltage to the conductive layer CE through the through hole TH2, in other words, the conductive layer CE may be a Common Electrode (Common Electrode), but not limited thereto. Conductive layer CE and trace AW (i)₄+5)-AW(i₄+8) respectively generate parasitic capacitances PC (i)₄+5)-PC(i₄+8) to compensate the gate line SL (i)₄+5)-SL(i₄+8) parasitic capacitance of the coupling.

In some embodiments, the conductive layer CE may extend from the active area 310 to the peripheral area 320, and the common electrode COM in each pixel unit may belong to the conductive layer CE. In this way, each common electrode COM in the active area 310 and the conductive layer CE in the peripheral area 320 can be formed through the same process.

In addition, the parasitic capacitance generated by the conductive layer CE and the traces AW (N '+ 2) -AW (N), respectively, may be related to the width of the traces AW (N' +2) -AW (N). For example, fig. 14 is a cross-sectional view of the partial layout of fig. 10 with the conductive layer CE added along the line a-a. As shown in fig. 14, the conductive layer CE and the trace AW (N '+ 2) -AW (N' +5) generate parasitic capacitances PC (N '+ 2) -PC (N' +5), respectively. Because the width of the trace AW (N '+ 2) -AW (N' +5) has a relation of W₁’>W₂’>W₃’>W₄', the relationship of the capacitance of the parasitic capacitance PC (N' +2) -PC (N '+ 5) is also PC (N' +2)>PC(N’+3)>PC(N’+4)>PC (N' + 5). In summary, the second portion of at least some gate lines in the gap 310S (or the recess 310N) between the sub-regions 310U1 and 310U2 may include a dual-layer trace structure, the conductive layer covers the upper trace of the dual-layer trace, and at least one insulating layer is disposed between the conductive layer and the upper trace to increase the parasitic capacitance on the gate lines, and preferably, the width of the upper trace of at least some dual-layer trace structures is different to adjust the parasitic capacitance on the gate lines in the irregular region 310U, so that the impedance-capacitance load of each gate line is equal or similar.

In summary, the display panel of the present invention has the special-shaped active region and includes the resistance and capacitance compensation function of the gate lines, so that the impedance-capacitance load of each gate line is equal or similar, thereby avoiding the generation of the problems of incorrect gray scale of the display image.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (8)

1. A display panel is characterized in that the display panel is provided with an active area and a peripheral area, the active area is shaped like a special shape, and the display panel comprises:

a substrate;

a plurality of pixel units disposed on the substrate and in the active region;

a plurality of gate lines disposed on the substrate, each gate line being coupled to one or more of the pixel units, a number of pixel units coupled to a first gate line of the gate lines being less than a number of pixel units coupled to a second gate line of the gate lines, wherein a portion of the first gate line includes a dual-layer routing structure, the dual-layer routing structure includes an upper layer routing and a lower layer routing, and the upper layer routing and the lower layer routing are configured in parallel, wherein the upper layer routing is formed by a first conductor layer, the lower layer routing is formed by a second conductor layer, the upper layer routing is disposed above the lower layer routing, and the upper layer routing overlaps the lower layer routing in a vertical projection direction, wherein the vertical projection direction is perpendicular to the substrate;

the insulating layer is positioned between the upper layer wire and the lower layer wire;

a plurality of first through holes in the insulating layer, wherein one and another of the plurality of first through holes are respectively overlapped with two opposite ends of the upper layer trace in the vertical projection direction, and the two opposite ends of the upper layer trace are respectively electrically connected with the lower layer trace through the one and another of the plurality of first through holes; and

at least one redundant thin film transistor disposed on the substrate and coupled to the first gate line.

2. The display panel of claim 1, wherein the active region comprises a first sub-region and a second sub-region, the first sub-region and the second sub-region are opposite to each other with a gap therebetween, and the at least one redundant thin film transistor is disposed in the gap.

3. The display panel of claim 2, wherein the active region further comprises a rectangular region, the first sub-region and the second sub-region are connected to one side of the rectangular region, and the second gate line is located in the rectangular region.

4. The display panel of claim 2, wherein the first gate line comprises a first portion, a second portion and a third portion, the first portion, the second portion and the third portion are respectively located in the first sub-region, the gap and the second sub-region, two ends of the second portion are respectively coupled to the first portion and the third portion, the second portion of the first gate line comprises the dual-layer routing structure, and the at least one redundant thin film transistor is coupled to the second portion.

5. The display panel according to claim 4, wherein a third gate line of the plurality of gate lines includes a first portion, a second portion and a third portion, the first portion, the second portion and the third portion of the third gate line are respectively located in the first sub-area, the gap and the second sub-area, and the second portion of the third gate line includes another dual-layer routing structure, the another dual-layer routing structure includes another upper-layer routing and another lower-layer routing, the another upper-layer routing is disposed above the another lower-layer routing, and the another upper-layer routing overlaps the another lower-layer routing in the vertical projection direction;

wherein the width of the upper layer trace is different from the width of the other upper layer trace.

6. The display panel of claim 4, wherein the display panel further comprises:

and the conductive layers are arranged on the double-layer wiring structures, are overlapped with the double-layer wiring structures in the vertical projection direction and are insulated from each other, wherein the vertical projection direction is vertical to the substrate.

7. The display panel according to claim 6, wherein the conductive layer is a common electrode.

8. The display panel of claim 2, wherein the display panel further comprises:

and the common electrode signal routing line is arranged between the edge of the active area and the edge of the display panel, and the at least one redundant thin film transistor is arranged between the edge of the active area and the common electrode signal routing line.

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