CN113238138A - Fault detection method for pcie exchange chip - Google Patents
Fault detection method for pcie exchange chip Download PDFInfo
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- CN113238138A CN113238138A CN202110348970.0A CN202110348970A CN113238138A CN 113238138 A CN113238138 A CN 113238138A CN 202110348970 A CN202110348970 A CN 202110348970A CN 113238138 A CN113238138 A CN 113238138A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N29/00—Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object
- G01N29/04—Analysing solids
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N29/00—Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic waves; Visualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object
- G01N29/22—Details, e.g. general constructional or apparatus details
- G01N29/30—Arrangements for calibrating or comparing, e.g. with standard objects
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
- G01R31/2874—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
- G01R31/2875—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature related to heating
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
- G06F30/23—Design optimisation, verification or simulation using finite element methods [FEM] or finite difference methods [FDM]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/08—Thermal analysis or thermal optimisation
Abstract
The invention relates to the technical field of chips and discloses a fault detection method for a pcie exchange chip, which comprises the following steps: arranging a to-be-detected pcie exchange chip on a fault detection tool, and heating a welding pin on the pcie exchange chip for 2-3 minutes at the heating temperature of 35-40 ℃; and calculating the size parameter of the initial welding leg based on a plastic deformation volume invariant theory according to the shape of the pcie exchange chip, and processing the target initial welding leg according to the size parameter. This a fault detection method for pcie exchange chip can treat that the pcie exchange chip that detects carries out fault detection, can connect stability, the pcie exchange chip current conduction quality and utilize the reference block of standard degree of depth simulation crackle to the leg of pcie exchange chip simultaneously, detects the pcie exchange chip crackle, realizes that the integral type detects, improves detection efficiency, reduces the defective index.
Description
Technical Field
The invention relates to the technical field of chips, in particular to a fault detection method for a pcie exchange chip.
Background
The classification method of integrated circuits is many, and can be classified into the following according to circuit analog or digital: analog integrated circuits, digital integrated circuits, and mixed signal integrated circuits (analog and digital on a single chip).
Digital integrated circuits may contain anything from thousands to millions of logic gates, flip-flops, multiplexers, and other circuits on a few square millimeters. The small size of these circuits allows for higher speed, lower power consumption (see low power design) and reduced manufacturing costs compared to board level integration. These digital ICs, represented by microprocessors, digital signal processors, and microcontrollers, operate using binary systems to process 1 and 0 signals.
The analog integrated circuit has, for example, a sensor, a power control circuit, and an operational amplifier, and processes analog signals. And the functions of amplification, filtering, demodulation, frequency mixing and the like are completed. The analog integrated circuit which is designed by experts and has good characteristics is used, so that the burden of a circuit designer is relieved, and the circuit designer does not need to design the analog integrated circuit from basic transistors.
Integrated circuits analog and digital circuits may be integrated on a single chip to make devices such as analog-to-digital converters and digital-to-analog converters. Such circuits provide smaller size and lower cost, but care must be taken with respect to signal collisions.
At present, the pcie exchange chip to be detected can not be utilized to carry out fault detection, and meanwhile, the welding leg connection stability of the pcie exchange chip, the current conduction quality of the pcie exchange chip and a reference block for simulating cracks by utilizing standard depth can not be realized, so that the cracks of the pcie exchange chip are detected, and integrated detection is realized, therefore, the improvement on the integrated detection is needed.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides the fault detection method for the pcie exchange chip, which has the advantages of a wire arrangement function and a temperature simulation test function, and solves the problems that the fault detection cannot be carried out on the pcie exchange chip to be detected, the welding leg connection stability of the pcie exchange chip, the current conduction quality of the pcie exchange chip and the detection on the cracks of the pcie exchange chip cannot be realized by using a standard depth simulation crack comparison test block, and the integrated detection cannot be realized in the prior art.
The fault detection method for the pcie exchange chip comprises the following steps:
step one, arranging a to-be-detected pcie exchange chip on a fault detection tool, and heating a welding leg on the pcie exchange chip for 2-3 minutes at the heating temperature of 35-40 ℃;
step two, calculating the size parameter of the initial welding leg based on the plastic deformation volume invariant theory according to the shape of the pcie exchange chip, and processing the target initial welding leg according to the size parameter;
comparing the shape of the processed initial welding leg with the shape of a target pcie exchange chip, analyzing the flow conditions of different positions of the initial pcie exchange chip in the forging process, partitioning the initial welding leg according to the deformation degree and the deformation difficulty of different parts of the initial welding leg, and determining the deformation temperature of each region by combining the thermal deformation behavior of the material;
preliminarily designing matched parameters of the gradient induction heating coil according to the zoning condition, the shape and the size of the welding leg, adopting gradual design in the transition part of the gradient induction heating coil, establishing a finite element model according to the shape and the size of the initial welding leg, the zoning and the temperature distribution of the welding leg and the parameters of the gradient induction heating coil, and simulating;
step five, detecting whether the pcie exchange chip works normally, if the pcie exchange chip can work normally, determining the plastic packaging problem of the heating chip, heating a welding pin of the chip, and simultaneously detecting whether the pcie exchange chip works normally, and if the pcie exchange chip can work normally, determining the welding problem of the heating chip;
designing and processing a reference block containing a standard depth simulation crack according to a detected pcie exchange chip, customizing a single crystal probe according to the depth of a detected area of the pcie exchange chip, and connecting ultrasonic equipment with the single crystal probe;
and seventhly, performing ultrasonic sensitivity adjustment on the reference block by using the standard depth simulation crack, taking the ultrasonic wave height of 40-65% as a detection reference wave height as a criterion for judging damage, and performing in-situ ultrasonic detection on the detected piece by using the ultrasonic sensitivity.
Preferably, the size of a welding foot of the pcie exchange chip is 8-10 mm.
Preferably, the gradient induction heating coil utilizes an insulated wire coil wound on the outer side of the pcie exchange chip, and generates electromagnetic induction heating in the pcie exchange chip after alternating current is supplied, so as to heat the pcie exchange chip.
Preferably, the induction heating furnace rectifies the three-phase power frequency alternating current into direct current, converts the direct current into adjustable intermediate frequency current, supplies the adjustable intermediate frequency alternating current to the capacitor and the induction coil, generates high-density magnetic lines in the induction coil, cuts the metal material contained in the induction coil, and generates eddy current in the metal material.
Preferably, in the fourth step, if the simulation result meets the design requirement of the target workpiece, the currently designed parameters are considered to be reasonable, otherwise, the second step and the third step are returned, adjustment is performed on the basis of the existing parameters, parameter design and simulation judgment are performed again, the coil is processed according to the determined gradient induction heating coil parameters and is placed in a complete set of induction heating furnace, the initial welding leg is placed in the induction heating furnace for heating, and the radiation thermometer is used for measuring the temperature of each part of the welding leg in real time until the temperature of each part reaches the target temperature.
Preferably, in the seventh step, if no waveform signal exceeding the height of the reference wave appears between the initial wave and the bottom wave, it is determined that the pcie exchange chip has no crack, and the detection is completed; and if a waveform signal exceeding the height of the reference wave appears between the initial wave and the bottom wave, recording the position information of the appearance of the waveform, and judging that the crack of the pcie exchange chip exceeds the standard.
Preferably, the power frequency 50HZ alternating current of the induction heating furnace is converted into 300HZ-1000 HZ.
Preferably, the single crystal probe has a frequency of 2.5MHz and a wavelength of 1.3 mm.
Compared with the prior art, the invention has the following beneficial effects: this a fault detection method for pcie exchange chip can treat that the pcie exchange chip that detects carries out fault detection, can connect stability, the pcie exchange chip current conduction quality and utilize the reference block of standard degree of depth simulation crackle to the leg of pcie exchange chip simultaneously, detects the pcie exchange chip crackle, realizes that the integral type detects, improves detection efficiency, reduces the defective index.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The fault detection method for the pcie exchange chip comprises the following steps:
step one, arranging a to-be-detected pcie exchange chip on a fault detection tool, and heating a welding leg on the pcie exchange chip for 2-3 minutes at the heating temperature of 35-40 ℃;
step two, calculating the size parameter of the initial welding leg based on the plastic deformation volume invariant theory according to the shape of the pcie exchange chip, and processing the target initial welding leg according to the size parameter;
comparing the shape of the processed initial welding leg with the shape of a target pcie exchange chip, analyzing the flow conditions of different positions of the initial pcie exchange chip in the forging process, partitioning the initial welding leg according to the deformation degree and the deformation difficulty of different parts of the initial welding leg, and determining the deformation temperature of each region by combining the thermal deformation behavior of the material;
preliminarily designing matched parameters of the gradient induction heating coil according to the zoning condition, the shape and the size of the welding leg, adopting gradual design in the transition part of the gradient induction heating coil, establishing a finite element model according to the shape and the size of the initial welding leg, the zoning and the temperature distribution of the welding leg and the parameters of the gradient induction heating coil, and simulating;
step five, detecting whether the pcie exchange chip works normally, if the pcie exchange chip can work normally, determining the plastic packaging problem of the heating chip, heating a welding pin of the chip, and simultaneously detecting whether the pcie exchange chip works normally, and if the pcie exchange chip can work normally, determining the welding problem of the heating chip;
designing and processing a reference block containing a standard depth simulation crack according to a detected pcie exchange chip, customizing a single crystal probe according to the depth of a detected area of the pcie exchange chip, and connecting ultrasonic equipment with the single crystal probe;
and seventhly, performing ultrasonic sensitivity adjustment on the reference block by using the standard depth simulation crack, taking the ultrasonic wave height of 40-65% as a detection reference wave height as a criterion for judging damage, and performing in-situ ultrasonic detection on the detected piece by using the ultrasonic sensitivity.
The size of the welding foot of the pcie exchange chip is 8-10 mm.
The gradient induction heating coil utilizes the insulated wire coil of winding in the pcie exchange chip outside, produces electromagnetic induction after leading to the alternating current and generates heat in the pcie exchange chip, heats the pcie exchange chip.
The induction heating furnace rectifies the three-phase power frequency alternating current into direct current, converts the direct current into adjustable intermediate frequency current, supplies the intermediate frequency alternating current flowing through a capacitor and an induction coil, generates high-density magnetic lines in the induction coil, cuts metal materials contained in the induction coil, and generates eddy currents in the metal materials.
And step four, if the simulation result meets the design requirement of the target workpiece, considering that all the parameters of the current design are reasonable, otherwise, returning to the step two and the step three, adjusting on the basis of all the existing parameters, redesigning the parameters and carrying out simulation judgment, processing the coil according to the determined gradient induction heating coil parameters, placing the coil into a complete set of induction heating furnace, placing the initial welding leg into the induction heating furnace for heating, and measuring the temperature of all the parts of the welding leg in real time by using a radiation thermometer until the temperature of all the parts reaches the target temperature.
If no waveform signal exceeding the reference wave height appears between the initial wave and the bottom wave, judging that the pcie exchange chip has no crack, and finishing the detection; and if a waveform signal exceeding the height of the reference wave appears between the initial wave and the bottom wave, recording the position information of the appearance of the waveform, and judging that the crack of the pcie exchange chip exceeds the standard.
The power frequency 50HZ alternating current of the induction heating furnace is converted into 300HZ-1000 HZ.
The frequency of the single crystal probe was 2.5MHz and its wavelength was 1.3 mm.
It should be noted that the fault detection method includes the following steps: arranging a to-be-detected pcie exchange chip on a fault detection tool, and heating a welding pin on the pcie exchange chip for 2-3 minutes at the heating temperature of 35-40 ℃; calculating the size parameter of the initial welding leg based on a plastic deformation volume invariant theory according to the shape of the pcie exchange chip, and processing the target initial welding leg according to the size parameter; comparing the shape of the processed initial welding leg with the shape of a target pcie exchange chip, analyzing the flow conditions of different positions of the initial pcie exchange chip in the forging process, partitioning the initial welding leg according to the deformation degree and the deformation difficulty of different parts of the initial welding leg, and determining the deformation temperature of each region by combining the thermal deformation behavior of the material; preliminarily designing matched parameters of the gradient induction heating coil according to the zoning condition, the shape and the size of the welding leg, adopting gradual design at the transition part of the gradient induction heating coil, establishing a finite element model according to the shape and the size of the initial welding leg, the zoning and the temperature distribution of the welding leg and the parameters of the gradient induction heating coil, and simulating; detecting whether the pcie exchange chip works normally, if so, heating a welding pin of the chip, and detecting whether the pcie exchange chip works normally, and if so, detecting the problem of plastic package of the heating chip; designing and processing a reference block containing a standard depth simulation crack according to a detected pcie exchange chip, customizing a single crystal probe according to the depth of a detected region of the pcie exchange chip, and connecting ultrasonic equipment with the single crystal probe; and (3) performing ultrasonic sensitivity adjustment on the reference block by using the standard depth simulation crack, taking the ultrasonic wave height of 40-65% as a detection reference wave height as a criterion for judging damage, and performing in-situ ultrasonic detection on the detected piece by using the ultrasonic sensitivity.
This a fault detection method for pcie exchange chip can treat that the pcie exchange chip that detects carries out fault detection, can connect stability, the pcie exchange chip current conduction quality and utilize the reference block of standard degree of depth simulation crackle to the leg of pcie exchange chip simultaneously, detects the pcie exchange chip crackle, realizes that the integral type detects, improves detection efficiency, reduces the defective index.
It should be noted that when the pcie exchange chip is detected, the suspected chip can firstly check whether the input end and the output end have signals (wave patterns) according to the instruction of the manual, if so, then check whether the control signals (clocks) of the IC are present or not, if so, the possibility of the IC being damaged is very high, and if not, the control signals are not present, and the previous pole of the IC is tracked until the damaged IC is found;
the same model can be selected when the user does not take off the electrode temporarily. Or the IC with the same program content is backed on the upper surface, and whether the program is improved or not is observed when the IC is started so as to confirm whether the IC is damaged or not.
Finding a short circuit line by a tangent and line-jumping method: if some signal line and ground line, +5V or other multiple ICs should not be connected to the pin short circuit, can cut off the line and remeasure, judge whether it is IC problem or plate routing problem, or from other ICs to weld to the phenomenon picture that looks good on the IC that the wave pattern is not right on by signal, judge whether the IC is good or bad.
Comparison method: a good circuit board with the same content is found to compare and measure the pin patterns and the number of the corresponding ICs to determine whether the ICs are damaged.
The IC was tested using ICTEST software in a microcomputer universal programmer (ALL-03/07) (EXPRO-80/100, etc.).
It should be noted that, because of the damage caused by the bad quality of the chip and other devices, during the fault detection, the dust is prevented, and the dust on the chip can be lightly brushed away by a brush, and in addition, some plug-in cards and chips on the chip adopt the pin form, and the contact is bad because of the oxidation of the pin. The surface oxide layer can be erased by using an eraser and the detection device is required to be closed immediately after the power is cut off suddenly, so that the chip and the power supply are prevented from being burnt down by a sudden incoming call.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (8)
1. The fault detection method for the pcie exchange chip is characterized by comprising the following steps of: the fault detection method comprises the following steps:
step one, arranging a to-be-detected pcie exchange chip on a fault detection tool, and heating a welding leg on the pcie exchange chip for 2-3 minutes at the heating temperature of 35-40 ℃;
step two, calculating the size parameter of the initial welding leg based on the plastic deformation volume invariant theory according to the shape of the pcie exchange chip, and processing the target initial welding leg according to the size parameter;
comparing the shape of the processed initial welding leg with the shape of a target pcie exchange chip, analyzing the flow conditions of different positions of the initial pcie exchange chip in the forging process, partitioning the initial welding leg according to the deformation degree and the deformation difficulty of different parts of the initial welding leg, and determining the deformation temperature of each region by combining the thermal deformation behavior of the material;
preliminarily designing matched parameters of the gradient induction heating coil according to the zoning condition, the shape and the size of the welding leg, adopting gradual design in the transition part of the gradient induction heating coil, establishing a finite element model according to the shape and the size of the initial welding leg, the zoning and the temperature distribution of the welding leg and the parameters of the gradient induction heating coil, and simulating;
step five, detecting whether the pcie exchange chip works normally, if the pcie exchange chip can work normally, determining the plastic packaging problem of the heating chip, heating a welding pin of the chip, and simultaneously detecting whether the pcie exchange chip works normally, and if the pcie exchange chip can work normally, determining the welding problem of the heating chip;
designing and processing a reference block containing a standard depth simulation crack according to a detected pcie exchange chip, customizing a single crystal probe according to the depth of a detected area of the pcie exchange chip, and connecting ultrasonic equipment with the single crystal probe;
and seventhly, performing ultrasonic sensitivity adjustment on the reference block by using the standard depth simulation crack, taking the ultrasonic wave height of 40-65% as a detection reference wave height as a criterion for judging damage, and performing in-situ ultrasonic detection on the detected piece by using the ultrasonic sensitivity.
2. The fault detection method for a pcie switch chip of claim 1, wherein: the size of a welding foot of the pcie exchange chip is 8-10 mm.
3. The fault detection method for a pcie switch chip of claim 1, wherein: the gradient induction heating coil utilizes an insulated wire coil wound on the outer side of the pcie exchange chip to generate electromagnetic induction heating in the pcie exchange chip after alternating current is conducted, and the pcie exchange chip is heated.
4. The fault detection method for a pcie switch chip of claim 1, wherein: the induction heating furnace rectifies three-phase power frequency alternating current into direct current, converts the direct current into adjustable intermediate frequency current, supplies the adjustable intermediate frequency alternating current to the capacitor and the induction coil, generates high-density magnetic lines in the induction coil, cuts metal materials contained in the induction coil, and generates eddy current in the metal materials.
5. The fault detection method for a pcie switch chip of claim 1, wherein: and step four, if the simulation result meets the design requirement of the target workpiece, considering that all the parameters of the current design are reasonable, otherwise, returning to the step two and the step three, adjusting on the basis of all the existing parameters, redesigning the parameters and carrying out simulation judgment, processing the coil according to the determined gradient induction heating coil parameters, placing the coil into a complete set of induction heating furnace, placing the initial welding leg into the induction heating furnace for heating, and measuring the temperature of all the parts of the welding leg in real time by using a radiation thermometer until the temperature of all the parts reaches the target temperature.
6. The fault detection method for a pcie switch chip of claim 1, wherein: if no waveform signal exceeding the reference wave height appears between the initial wave and the bottom wave, judging that the pcie exchange chip has no crack, and finishing the detection; and if a waveform signal exceeding the height of the reference wave appears between the initial wave and the bottom wave, recording the position information of the appearance of the waveform, and judging that the crack of the pcie exchange chip exceeds the standard.
7. The fault detection method for a pcie switch chip of claim 1, wherein: and converting the power frequency 50HZ alternating current of the induction heating furnace into 300HZ-1000 HZ.
8. The fault detection method for a pcie switch chip of claim 1, wherein: the frequency of the single crystal probe was 2.5MHz and the wavelength was 1.3 mm.
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