CN113224236B - Transparent double-layer-structure memristor and preparation method thereof - Google Patents
Transparent double-layer-structure memristor and preparation method thereof Download PDFInfo
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- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
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- H—ELECTRICITY
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- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
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Abstract
The invention belongs to the technical field of conductor device micro-nano processing, and particularly relates to a transparent memristor with a double-layer structure and a preparation method thereof. The memristor with the double-layer structure is composed of a substrate, a bottom electrode and a top electrode which are sequentially arranged from bottom to top, wherein the top electrode and the bottom electrode are used for being connected with a positive voltage and a negative voltage respectively, so that the volatility and the self-current limiting performance of the memristor are realized.
Description
Technical Field
The invention belongs to the technical field of conductor device micro-nano processing, and particularly relates to a transparent memristor with a double-layer structure and a preparation method thereof.
Background
The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.
With the rapid increase of the data amount required to be processed in the information era, the traditional semiconductor storage and operation device faces the physical bottleneck, and a novel operation mode and device represented by memory operation and brain-like nerve morphology operation have great potential. The memristor is a fourth basic electronic component, except for a resistor, an inductor and a capacitor, which is obtained by China scientist professor Chuan begonia from the perspective of circuit completeness. The device shows the relationship between the electric charge and the magnetic flux, can change the resistance of the device along with the change of the external voltage, has the characteristics of simple structure, easy integration, high reading and writing speed, low power consumption and the like, and can be used for future large-scale novel storage devices; and synapse plasticity can be simulated and applied to novel brain-like operations, so that an artificial neural network is realized on a hardware level.
A volatile memristor, also called a threshold-type memristor, is a special memristor. When a voltage applied across the volatile memristor exceeds its threshold voltage, its resistance changes to a low resistance state. When the voltage is removed, the resistance of the volatile memristor restores to a high resistance state. Volatile memristors can be used as selectors for memory circuits, as well as in simulations of neurons.
The inventor finds that the traditional volatile memristor mostly adopts nonferrous metals such as silver or copper and the like as electrode materials, and is not beneficial to future transparent electronic application. In addition, the traditional memristor has a three-layer structure of a top electrode, a dielectric layer and a bottom electrode, achieves the purpose of volatility by means of externally added small limiting current when in use, and is complex in preparation and integration.
Disclosure of Invention
In order to solve the technical problems in the background art, the invention provides a transparent memristor with a double-layer structure and a preparation method thereof, wherein the transparent memristor has good light transmittance in a visible light region, shows the phenomena of volatility and self current limiting, and is simpler in preparation and integration processes. Wherein the visible light region refers to an electromagnetic wave region having a wavelength of 400 to 780 nm.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention provides a transparent memristor with a double-layer structure, which is composed of a substrate, a bottom electrode and a top electrode which are sequentially arranged from bottom to top, wherein the top electrode and the bottom electrode are used for being connected with positive voltage and negative voltage respectively, so that the volatility and the self-current limiting performance of the memristor are realized.
Further, the substrate and the bottom electrode are transparent indium tin oxide glass or indium tin oxide PET (polyethylene terephthalate).
Further, the bottom electrode is formed by etching an indium tin oxide glass or PET substrate.
Further, the top electrode is an indium tin oxide layer.
Further, the top electrode is formed on the bottom electrode by sputtering and depositing an indium tin oxide layer by a magnetron sputtering method.
The second aspect of the invention provides a preparation method of a transparent memristor with a double-layer structure, which comprises the following steps:
using transparent indium tin oxide glass or indium tin oxide PET as a substrate;
cleaning a substrate, and preparing a mask layer with a bottom electrode pattern on the substrate;
etching a rectangular structure array on the substrate and using the rectangular structure array as a bottom electrode layer;
removing the mask layer with the bottom electrode pattern, and preparing a top electrode pattern mask layer vertical to the bottom electrode pattern on the substrate with the rectangular structure array;
depositing an indium tin oxide layer by magnetron sputtering, wherein the indium tin oxide layer is used as a top electrode layer;
and removing the mask layer with the top electrode pattern.
Further, the process of cleaning the substrate is as follows:
cleaning the substrate by using a cleaning solution;
cleaning the substrate by using ultrasonic cleaning equipment with different liquids;
and taking out the cleaned substrate and drying the substrate by blowing.
Further, the process of cleaning the substrate by using the ultrasonic cleaning equipment with different liquids is as follows:
cleaning the substrate again by pure water ultrasound;
cleaning the substrate again by using acetone ultrasound;
and cleaning the substrate again by using ethanol ultrasound.
Further, the process of preparing the mask layer having the bottom electrode pattern on the substrate is:
heating the substrate at a set temperature;
spin coating a photoresist on a heated substrate;
heating the substrate coated with the photoresist for a set time;
placing a substrate in an ultraviolet photoetching machine, photoetching by utilizing a photoetching mask plate with an electrode pattern, and then placing the substrate in a developing solution;
and placing the substrate in a concentrated hydrochloric acid solution for etching to prepare the substrate with a rectangular structure array, thereby obtaining the mask layer with the bottom electrode pattern.
Furthermore, a target gun filled with indium tin oxide material is selected as a sputtering source, the power of a magnetron sputtering instrument and the vacuum degree during sputtering are set, and sputtering is carried out at room temperature.
The invention has the beneficial effects that:
the memristor only comprises the substrate, the bottom electrode and the top electrode, and an additional resistance change dielectric layer is not needed, so that the transparent double-layer memristor is simpler in structure, the preparation process of the memristor is greatly simplified, and the whole device has higher transparency and can be used as a novel transparent device. The device has good volatility characteristic, does not need additional electricity formation and current limiting operation, and can be used as a memory circuit selector or used for simulating the function of an artificial neuron in brain-like operation.
Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings, which form a part hereof, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, an illustrative embodiment 1 of the invention and the description thereof for the purpose of explanation and not limitation of the invention.
Fig. 1 is a flowchart of a method for manufacturing a transparent memristor with a double-layer structure according to embodiment 1 of the present disclosure;
FIG. 2 is a schematic view of the structure of a transparent substrate according to embodiment 1 of the present invention;
FIG. 3 is a schematic structural diagram of forming a bottom electrode in example 1 of the present invention;
FIG. 4 is a schematic structural diagram of forming a top electrode in example 1 of the present invention;
FIG. 5 is a cross-sectional view of a transparent two-layer memristor of embodiment 1 of the present invention;
FIG. 6 is a diagram of the memristor optical transmittance of the transparent double-layer structure of embodiment 1 of the present invention;
fig. 7 is a current-voltage characteristic diagram of a transparent double-layer memristor according to embodiment 1 of the present invention.
Fig. 8(a) is a graph of the artificial pain receptor current response at different input voltage durations according to example 2 of the present invention;
fig. 8(b) is a graph showing the artificial pain receptor current response at different input voltage amplitudes according to example 2 of the present invention.
Detailed Description
The invention is further described with reference to the following figures and examples.
It is to be understood that the following detailed description is exemplary and is intended to provide further explanation of the invention as claimed. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
In the present invention, terms such as "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "side", "bottom", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only terms of relationships determined for convenience of describing structural relationships of the parts or elements of the present invention, and are not intended to refer to any parts or elements of the present invention, and are not to be construed as limiting the present invention.
In the present invention, terms such as "fixedly connected", "connected", and the like should be understood broadly, and mean that they may be fixedly connected, or may be integrally connected or detachably connected; may be directly connected or indirectly connected through an intermediate. The specific meanings of the above terms in the present invention can be determined according to specific situations by persons skilled in the relevant scientific or technical field, and are not to be construed as limiting the present invention.
Example 1
As shown in fig. 5, the transparent memristor with a double-layer structure in the present embodiment is composed of a substrate, a bottom electrode, and a top electrode, which are sequentially arranged from bottom to top, and the top electrode and the bottom electrode are used for connecting a positive voltage and a negative voltage, respectively, so as to implement the volatility and the self-current limiting performance of the memristor.
In the present embodiment, the substrate and the bottom electrode are transparent indium tin oxide glass or indium tin oxide PET (polyethylene terephthalate). In other embodiments, a commercially available substrate such as polyethylene naphthalate (PEN) or Polyimide (PI) may be used as the substrate.
In other embodiments, the bottom electrode is formed by etching an indium tin oxide glass or PET substrate.
In some embodiments, the top electrode is a layer of indium tin oxide.
Specifically, the top electrode is formed on the bottom electrode by sputtering and depositing an indium tin oxide layer by a magnetron sputtering method.
Referring to fig. 1, a preparation method of the transparent double-layer memristor of the present embodiment includes:
step 1: transparent indium tin oxide glass or indium tin oxide PET was used as the substrate.
Step 2: and cleaning the substrate, and preparing a mask layer with a bottom electrode pattern on the substrate.
In this embodiment, the process of cleaning the substrate is as follows:
cleaning the substrate by using a cleaning solution; for example: taking transparent indium tin oxide glass or indium tin oxide PET as a substrate, putting the substrate into a beaker, adding diluted dikang cleaning solution into the beaker, wherein the preparation ratio of the dikang cleaning solution is dikang stock solution: pure water 1: and 20, putting the mixture into an ultrasonic cleaning machine for cleaning, and taking out the mixture after 5 min.
Cleaning the substrate by using ultrasonic cleaning equipment with different liquids;
and taking out the cleaned substrate and drying the substrate by blowing.
The process of cleaning the substrate by using the ultrasonic cleaning equipment with different liquids comprises the following steps:
cleaning the substrate again by pure water ultrasound;
cleaning the substrate again by using acetone ultrasound;
and cleaning the substrate again by using ethanol ultrasound.
In specific implementation, liquid in a beaker after the dikang cleaning liquid is subjected to ultrasonic treatment is poured into a waste liquid barrel, pure water is added into the beaker, the beaker is placed into an ultrasonic cleaning machine for primary pure water cleaning, and the beaker is taken out after 5 min; then pouring the liquid in the beaker subjected to the ultrasonic treatment of the first pure water into a waste liquid barrel, adding the pure water into the beaker again, putting the beaker into an ultrasonic cleaning machine for cleaning the beaker with the pure water for the second time, and taking out the beaker after 5 min; then pouring the liquid in the beaker after pure water is subjected to ultrasonic treatment into a waste liquid barrel, adding an acetone solution, putting into an ultrasonic cleaning machine for cleaning, and taking out after 5 min; then pouring the liquid in the acetone-treated beaker into a waste liquid barrel, adding an ethanol solution, putting into an ultrasonic cleaning machine for cleaning, and taking out after 5 min; the cleaned substrate was then removed and purged with a nitrogen gun to yield a cleaned indium tin oxide glass or PET substrate, as shown in fig. 2.
And step 3: and etching the rectangular structure array on the substrate and using the rectangular structure array as a bottom electrode layer.
Placing indium tin oxide glass or PET substrate on a heating table, and heating at 110 ℃ for more than 3 min; then spin-coating AR-P5350 photoresist on an indium tin oxide glass or PET substrate at the spin-coating rate of 500r/min for 5s at first and 1500r/min for 90s at later; then placing the indium tin oxide glass or PET substrate on a heating table, and heating for 3min at 110 ℃; then placing the indium tin oxide glass or the PET substrate in an ultraviolet photoetching machine, photoetching by utilizing a photoetching mask plate with electrode patterns, and then placing the indium tin oxide glass or the PET substrate in a developing solution; then, the indium tin oxide glass or PET substrate is placed in a concentrated hydrochloric acid solution for etching, and indium tin oxide with a rectangular structure array is prepared to be used as a bottom electrode, as shown in fig. 3.
And 4, step 4: removing the mask layer with the bottom electrode pattern, and preparing a top electrode pattern mask layer vertical to the bottom electrode pattern on the substrate with the rectangular structure array;
in this embodiment, the process of preparing a mask layer having a bottom electrode pattern on a substrate is as follows:
heating the substrate at a set temperature;
spin coating a photoresist on a heated substrate;
heating the substrate coated with the photoresist for a set time;
placing a substrate in an ultraviolet photoetching machine, photoetching by utilizing a photoetching mask plate with an electrode pattern, and then placing the substrate in a developing solution;
and placing the substrate in a concentrated hydrochloric acid solution for etching to prepare the substrate with a rectangular structure array, thereby obtaining the mask layer with the bottom electrode pattern.
For example: removing the mask layer, placing indium tin oxide glass or PET substrate on a heating table, and heating at 110 deg.C for more than 3 min; then spin-coating AR-P5350 photoresist on an indium tin oxide glass or PET substrate at the spin-coating rate of 500r/min for 5s at first and 1500r/min for 90s at later; the indium tin oxide glass or PET substrate was then placed on a heating stage and heated at 110 ℃ for 3 min.
And 5: an indium tin oxide layer was deposited by magnetron sputtering, the indium tin oxide layer acting as the top electrode layer.
Placing indium tin oxide glass or a PET substrate in an ultraviolet photoetching machine, photoetching by utilizing a photoetching mask plate with electrode patterns, and then placing the indium tin oxide glass or the PET substrate in a developing solution to prepare a top electrode pattern mask layer vertical to a bottom electrode layer pattern; depositing an indium tin oxide layer on the photoetched indium tin oxide glass or PET substrate by magnetron sputtering, selecting a target gun filled with an indium tin oxide material as a sputtering source, setting the power of a magnetron sputtering instrument to be 60W, and setting the vacuum degree to be lower than 1 x 10 during sputtering - 6 Torr, sputtering at room temperature, and preparing a top electrode. The mask layer with the top electrode pattern is then removed.
As shown in fig. 4.
The electrical characteristics of the transparent double-layer memristor are explained in detail with reference to fig. 7:
when the memristor is subjected to an electrical characteristic test under a direct-current scanning voltage, a positive voltage is applied to the top electrode, the voltage is swept from 0V to a set positive voltage value and then swept back to 0V from the set voltage value, and no additional limiting current is required to be arranged in the whole process. The device is in a high-resistance state initially, the current is slowly increased along with the increase of the voltage, and after the threshold voltage is reached, the current is rapidly increased, so that the device is converted into a low-resistance state. And during the subsequent second scanning and the third scanning, the device shows a high-resistance state at the beginning, which shows that the device restores from the low-resistance state to the high-resistance state after the voltage is removed, and has volatile characteristics. Wherein, the voltage change of the second scanning and the third scanning is the same as the voltage change of the first scanning, namely, a positive voltage is applied on the top electrode, and the voltage is swept from 0V to a set positive voltage value and then swept back to 0V from the set voltage value. The threshold voltage value of the device which generates resistance conversion in three times of scanning is close. As shown in fig. 7, the current suddenly changes at 4V in the first scan, and the device switches from the high resistance state to the low resistance state. And the voltage values of the current jumps at the subsequent second and third scans approach, indicating that the device does not require an additional initial electroforming process.
The transparent double-layer structure memristor is simpler in structure, and the preparation flow of the memristor is greatly simplified. The device has high transparency and can be used as a novel transparent device. The device has good volatility characteristic, does not need additional electricity formation and current limiting operation, and can be used as a memory circuit selector or used for simulating the function of an artificial neuron in brain-like operation.
Example 2
The embodiment shows an application scenario of a memristor with a double-layer structure, and specifically, the memristor is used as an artificial pain receptor to simulate an organism pain perception function, which is described in detail with reference to fig. 8(a) and 8 (b):
as shown in fig. 8(a), when a pulse signal having a voltage amplitude of 6V and a duration of increasing from 40 μ s, 100 μ s, 200 μ s, 1ms, 2ms was applied across the artificial nociceptor, the response current generated by the artificial nociceptor was low at voltage durations of 40 μ s, 100 μ s, and 200 μ s, each being about 0.05mA, indicating that the artificial nociceptor was not activated; whereas the response current increased to around 0.15mA at voltage durations of 1ms and 2ms, indicating that the artificial pain receptors were activated, producing a large response. This behavior can be used to simulate the response of the biological pain receptors to the duration of the pain stimulus, i.e., to be insensitive to external stimuli of relatively low duration, and when the duration of the external stimulus increases, the biological pain receptors produce pain and transmit an activation signal to the central nerve.
As shown in fig. 8(b), when a pulse signal having a voltage of 1ms duration and an increasing magnitude from 1V, 2V, 3V, 4V, 5V, 6V is applied across the artificial nociceptor, the response current generated by the artificial nociceptor is low at voltage magnitudes of 1V, 2V, 3V, 4V, and 5V, and is lower than 0.05mA, indicating that the artificial nociceptor is not activated; and the response current increases to about 0.15mA at a voltage amplitude of 6V, which indicates that the artificial pain receptor is activated and generates a large response. This behavior can be used to simulate the response of a pain receptor of a living organism to the intensity of a pain stimulus, i.e., to an external stimulus of lower intensity, which when increased above a pain threshold, causes the pain receptor of the living organism to produce a pain sensation that transmits an activation signal to the central nerve.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (5)
1. A transparent memristor with a double-layer structure is characterized by being composed of a substrate, a bottom electrode and a top electrode which are sequentially arranged from bottom to top, wherein the top electrode and the bottom electrode are used for being respectively connected with a positive voltage and a negative voltage so as to achieve the volatility and the self-current limiting performance of the memristor;
the substrate and the bottom electrode are made of transparent indium tin oxide glass or indium tin oxide PET;
the top electrode is an indium tin oxide layer;
the preparation method of the transparent double-layer structure memristor comprises the following steps:
using transparent indium tin oxide glass or indium tin oxide PET as a substrate;
cleaning a substrate, and preparing a mask layer with a bottom electrode pattern on the substrate;
etching a rectangular structure array on the substrate and using the rectangular structure array as a bottom electrode layer;
removing the mask layer with the bottom electrode pattern, and preparing a top electrode pattern mask layer vertical to the bottom electrode pattern on the substrate with the rectangular structure array;
depositing an indium tin oxide layer by magnetron sputtering, wherein the indium tin oxide layer is used as a top electrode layer;
and removing the mask layer with the top electrode pattern.
2. The transparent bilayer architecture memristor of claim 1, wherein the cleaning of the substrate is by:
cleaning the substrate by using a cleaning solution;
cleaning the substrate by using ultrasonic cleaning equipment with different liquids;
and taking out the cleaned substrate and drying the substrate by blowing.
3. The transparent double-layer memristor according to claim 1, wherein the substrate is cleaned by an ultrasonic cleaning device using different liquids in the following steps:
cleaning the substrate again by pure water ultrasound;
cleaning the substrate again by using acetone ultrasound;
and cleaning the substrate again by using ethanol ultrasound.
4. The transparent double-layer memristor according to claim 1, wherein the process of preparing the mask layer with the bottom electrode pattern on the substrate is as follows:
heating the substrate at a set temperature;
spin coating a photoresist on a heated substrate;
heating the substrate coated with the photoresist for a set time;
placing a substrate in an ultraviolet photoetching machine, photoetching by utilizing a photoetching mask plate with an electrode pattern, and then placing the substrate in a developing solution;
and placing the substrate in a concentrated hydrochloric acid solution for etching to prepare the substrate with a rectangular structure array, thereby obtaining the mask layer with the bottom electrode pattern.
5. The transparent memristor with a double-layer structure as in claim 1, wherein a target gun filled with indium tin oxide material is used as a sputtering source, the power of a magnetron sputtering instrument and the vacuum degree during sputtering are set, and sputtering is carried out at room temperature.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101740718B (en) * | 2009-12-17 | 2012-08-01 | 复旦大学 | Multi-resistance state resistor random-access memory unit and preparation method thereof |
| CN104752608A (en) * | 2013-12-26 | 2015-07-01 | 北京有色金属研究总院 | Memristor and manufacturing method thereof |
| US10008264B2 (en) * | 2014-10-23 | 2018-06-26 | Hewlett Packard Enterprise Development Lp | Memristive cross-bar array for determining a dot product |
| CN105304813A (en) * | 2015-09-23 | 2016-02-03 | 复旦大学 | Neural synapse simulation device and preparation method thereof |
| US10062843B2 (en) * | 2015-12-11 | 2018-08-28 | Samsung Electronics Co., Ltd. | Variable resistive memory device and method of manufacturing the same |
| CN105932035A (en) * | 2016-04-28 | 2016-09-07 | 杭州电子科技大学 | Gating device for resistive random access memory crossbar array and preparation method thereof |
| CN106449123B (en) * | 2016-12-14 | 2018-03-09 | 郑州华晶金刚石股份有限公司 | For DSSC to electrode and its preparation and application |
| CN110137350A (en) * | 2019-04-28 | 2019-08-16 | 南京邮电大学 | A kind of array memristor for realizing resistance state consecutive variations |
| CN110137352A (en) * | 2019-05-28 | 2019-08-16 | 湖北大学 | One kind being based on Ti3C2The gating device and preparation method thereof of-MXene film functional layer |
| CN111900249B (en) * | 2020-07-15 | 2022-10-14 | 南京邮电大学 | Memristor and preparation method thereof |
| CN111900250A (en) * | 2020-07-24 | 2020-11-06 | 南京邮电大学 | Memristor based on two-dimensional transition metal material and preparation method thereof |
| CN111969108A (en) * | 2020-08-27 | 2020-11-20 | 电子科技大学 | Flexible substrate-based copper metaaluminate memristor and preparation method |
| CN112271253A (en) * | 2020-10-19 | 2021-01-26 | 南京邮电大学 | Based on two dimension V2Memristor made of C material and preparation method thereof |
| CN112331773B (en) * | 2020-10-26 | 2023-02-07 | 复旦大学 | Fully-transparent waterproof flexible organic memristor and preparation method thereof |
| CN112289930B (en) * | 2020-10-29 | 2022-08-05 | 华中科技大学 | CuxO memristor with volatility and non-volatility and regulation and control method thereof |
| CN112467031A (en) * | 2020-11-26 | 2021-03-09 | 南京邮电大学 | Low-power-consumption memristor based on Ag-In-Zn-S quantum dots and preparation method thereof |
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