CN113224167B - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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CN113224167B
CN113224167B CN202110461719.5A CN202110461719A CN113224167B CN 113224167 B CN113224167 B CN 113224167B CN 202110461719 A CN202110461719 A CN 202110461719A CN 113224167 B CN113224167 B CN 113224167B
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layer
charge
semiconductor
buried oxide
charge trapping
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CN113224167A (en
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陆芃
任洪宇
李博
刘凡宇
李多力
卜建辉
刘海南
赵发展
韩郑生
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

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Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, relates to the technical field of semiconductor devices, and aims to solve the problem that performance of a front-end MOSFET (metal-oxide-semiconductor field effect transistor) is affected due to the fact that a large amount of radiation-induced trap trapped charges are easily generated in a buried oxide layer of an MOSFET (metal-oxide-semiconductor field effect transistor) device based on an SOI (silicon on insulator) platform. The semiconductor device includes: an SOI substrate; a charge trapping structure and a first semiconductor layer which are formed on the SOI substrate in a stacking manner from bottom to top, wherein the charge trapping structure is a dielectric layer stacking structure; and a body contact electrode formed on the second semiconductor layer of the SOI substrate, the charge trapping structure for trapping charges of the first semiconductor layer to form a first electric field for neutralizing a second electric field generated by the charge trapping structure due to a radiation effect when a voltage is applied to the body contact electrode. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device comprising the technical scheme.

Description

Semiconductor device and manufacturing method thereof
Technical Field
The present invention relates to the field of semiconductor devices, and more particularly, to a semiconductor device and a method for manufacturing the same.
Background
A Silicon-On-Insulator (SOI) platform is one of the commonly used Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) platforms. Compared with a traditional Bulk Silicon (Bulk Silicon) platform, the SOI platform is additionally provided with a buried oxide layer (BOX) between a front-end device and a substrate, so that all-dielectric isolation between the front-end device and the substrate is realized, and stronger single-event latch-up (SEL) resistance and instantaneous dose rate resistance can be provided for the MOSFET. Experiments show that the SOI platform can improve the neutron single event effect resistance of the MOSFET by more than one order of magnitude. Therefore, SOI reinforcement technology has become one of the important technologies in the space and military field to improve radiation resistance, life span and reliability of aerospace and strategic weapons systems.
In SOI platforms, the buried oxide layer is typically thick and its radiation sensitive volume is large. When irradiated, a great deal of radiation-induced trapped charge accumulation is easily generated in the buried oxide layer, thereby affecting the performance of the front-end MOSFET.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method thereof, which are used for solving the problem that the performance of a front-end MOSFET is influenced because a large amount of charges are easily accumulated in a buried oxide layer of the MOSFET device based on an SOI platform in a radiation environment.
In a first aspect, the present invention provides a semiconductor device comprising:
an SOI substrate;
a charge-trapping structure and a first semiconductor layer formed on the SOI substrate by stacking from bottom to top, the charge-trapping structure being a stacked structure formed of a plurality of dielectric layers;
and a body contact electrode formed on the second semiconductor layer of the SOI substrate, the charge trapping structure for trapping charges in the first semiconductor layer when a voltage is applied to the body contact electrode to form a first electric field for neutralizing a second electric field generated by the charge trapping structure due to a radiation effect.
With the above technical solution, when a voltage is applied to the body contact electrode, the charge trapping structure traps charges in the first semiconductor layer, and the charges in the charge trapping structure form a first electric field for neutralizing a second electric field generated by the charge trapping structure due to a radiation effect. The first electric field can inhibit device leakage and threshold voltage drift caused by radiation charge, and radiation resistance of the system is enhanced. The charge trapping structure can complete the radiation-resistant reinforcement of the device within a period of time through single charge trapping without continuously applying voltage on the body contact electrode, so that the power consumption generated for responding to the radiation reinforcement can be reduced, and the radiation-resistant power consumption is reduced. Meanwhile, the amount of electric charge injected into the charge trapping structure is irrelevant to the amount of electric charge generated by the total dose effect, so that the self-adaptive control of the first electric field on the second electric field is realized.
In a second aspect, the present invention also provides a method for manufacturing a semiconductor device, comprising the steps of:
providing an SOI substrate;
forming a charge trapping structure and a first semiconductor layer on the SOI substrate in a stacking manner from bottom to top, wherein the charge trapping structure is a stacked structure formed by a plurality of dielectric layers;
a body contact electrode is formed on the second semiconductor layer of the SOI substrate, and when a voltage is applied to the body contact electrode, the charge-trapping structure is configured to trap charges in the first semiconductor layer to form a first electric field that cancels a second electric field generated by the charge-trapping structure due to a radiation effect.
With the above technical solution, the beneficial effects of the semiconductor device manufacturing method provided by the second aspect are the same as those of the semiconductor device described in the first aspect, and are not described herein again.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
fig. 2 to fig. 6e are schematic process diagrams of a semiconductor manufacturing method according to an embodiment of the invention.
Reference numerals are as follows:
1-a first buried oxide layer, 2-a second semiconductor layer, 3-a first insulating layer, 4-a substrate layer, 5-a charge trapping layer, 6-a second buried oxide layer, 7-a first semiconductor layer, 8-a gate oxide layer, 9-a polysilicon gate, 10-a sidewall, 11-a source/drain doped region, 12-a first doped region, 13-a first dielectric layer, 14-a first contact hole, 15-a metal silicide layer, 16-an electrode, 100-an SOI substrate, 200-a charge trapping structure, 300-a body contact electrode.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through the use of two elements or the interaction of two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Example one
While the SOI platform improves neutron particle effect (SEE) resistance of the system, it is relatively weak against the total dose effect (TID). In SOI platforms, the BOX is typically thick and its radiation sensitive volume is large. When exposed to radiation, the BOX is susceptible to significant radiation charge accumulation, which affects the performance of the front-end MOSFET. The radiation forms oxide trap charges in the oxide and interface trap charges at the interface of the oxide layer and the semiconductor material. The built-in electric field generated by trap trapped charges induced by radiation in the buried oxide layer can cause the accumulation of electrons at the back channel, so that the back interface of the N-type MOSFET is inverted, and the leakage current is increased. Meanwhile, trapped charges and interface states in the buried oxide layer will also cause drift of the front gate threshold voltage through a coupling effect, resulting in a circuit or system failure. Therefore, the service life of the SOI system in the deep space and other strong radiation environments is shortened, and the application of the SOI platform is limited. In addition, the thicker buried oxide layer also brings more serious floating body effect to the SOI MOSFET. Because the body region of the device is suspended, the potential of the body region changes with different working conditions of the device, and the parasitic npn triode introduced into the drain region, the body region and the source region can be in a conducting state, so that the device fails.
In view of the limited radiation resistance of the MOS device on the existing SOI platform, and particularly the difficulty in meeting the requirements of the application in the aspect of ultra-low power consumption circuits, as shown in fig. 1, an embodiment of the present invention provides a semiconductor device, including:
an SOI substrate 100;
a charge-trapping structure 200 and a first semiconductor layer 7 formed on the SOI substrate 100 by stacking from the bottom up, the charge-trapping structure 200 being a stacked structure formed of a plurality of dielectric layers;
and a body contact electrode 300 formed on the second semiconductor layer 2 of the SOI substrate 100, the charge trapping structure 200 serving to trap charges in the first semiconductor layer 7 when a voltage is applied to the body contact electrode 300 to form a first electric field for neutralizing a second electric field generated by the charge trapping structure 200 due to a radiation effect.
Wherein the charge trapping structure 200 includes a first buried oxide layer 1, a charge trapping layer 5, and a second buried oxide layer 6, which are laminated from bottom to top on the SOI substrate 100, the charge trapping layer 5 serving to trap electrons in the first semiconductor layer 7 when a positive voltage is applied to the body contact electrode 300. The second electric field is a built-in electric field generated by the radiation-induced trapped charges in the buried oxide layer as described above.
In practical applications, the charge trapping structure 200 is used to trap electrons of the first semiconductor layer 7 when a positive voltage is applied to the body contact electrode 300. Specifically, when a positive voltage is applied to the body contact electrode 300, electrons in the first semiconductor layer 7 enter the charge trapping structure 200 through the second buried oxide layer 6 in a thermal excitation or quantum tunneling manner and are trapped by the charge traps, so that charge storage and trapping are realized, and a first electric field is formed and used for neutralizing a second electric field generated by a radiation effect. The second semiconductor layer 2 can complete the radiation hardening of the device within a period of time only by configuring and applying a positive voltage once, and the voltage does not need to be continuously applied to the body contact electrode 300, so that the power consumption generated for the radiation hardening can be reduced, and the radiation hardening power consumption can be reduced.
When a negative voltage is applied to the body contact electrode 300, the charge trapping structure 200 releases the electrons trapped by itself. Specifically, when a negative voltage is applied to the body contact electrode 300, electrons stored in the charge storage structure are discharged, and this process is called an erase operation. The charges generated in the substrate, i.e., the charge trapping structure 200, by the total dose of radiation may be removed by a wipe-out operation. And the threshold voltage of the MOSFET device in the first semiconductor layer 7 is remodulated by reapplying the negative voltage. The process is independent of TID electric charge quantity, so that the self-adaptive control is realized.
In practical applications, the charge trapping layer 5 may be a silicon nitride layer or a silicon oxynitride layer. The silicon nitride and the silicon oxynitride have deep energy level defects, so that charges can be stored in discrete defect states, leakage is not easy to occur, the reliability is good, a tunneling electric field is enhanced, and the configuration speed is increased. The above-described charge trapping layer 5 traps electrons in the first semiconductor layer 7, and it can also be understood that when a positive electrode is applied to the body contact electrode 300, electrons in the first semiconductor layer 7 are injected into the charge trapping layer 5.
For another example, the first buried oxide layer 1 is one of a silicon dioxide material layer, an aluminum oxide material layer, and a hafnium oxide material layer; and/or the second buried oxide layer 6 is one of a silicon dioxide material layer, an aluminum oxide material layer and a hafnium oxide material layer. High dielectric constant dielectric materials (i.e., high k dielectric materials) such as silicon dioxide, hafnium oxide, and aluminum oxide. The high dielectric constant dielectric material can increase the barrier height of the first buried oxide layer 1, can inhibit electrons from being injected from the second semiconductor layer 2 or from a channel in the erasing process, improves the erasing efficiency and inhibits the erasing saturation.
In another example of application, the thickness of the second buried oxide layer 6 is smaller than the thickness of the first buried oxide layer 1, and is also smaller than the thickness of the charge trapping layer 5. The second buried oxide layer 6 is thinner than the charge trapping layer 5 and the first buried oxide layer 1 to isolate the charge trapping layer 5 from the first semiconductor layer 7 while ensuring that electrons in the channel of the first semiconductor layer 7 can tunnel to the charge trapping layer 5.
With the above-described technical solution, when a voltage is applied to the body contact electrode 300, the charge-trapping structure 200 traps charges of the first semiconductor layer 7, and the charges in the charge-trapping structure 200 form a first electric field for neutralizing a second electric field generated by the charge-trapping structure 200 due to the radiation effect. The first electric field can inhibit device leakage and threshold voltage drift caused by the second electric field generated by radiation charges, and the radiation resistance of the whole semiconductor device is enhanced. The charge trapping structure 200 can complete the radiation hardening of the device within a period of time by injecting charges once without continuously applying a voltage to the body contact electrode 300, and can reduce the power consumption generated for the radiation hardening, thereby achieving the purpose of reducing the radiation hardening power consumption and meeting the application requirements in the aspect of ultra-low power consumption circuits. The process of remodulating the threshold voltage of the MOSFET device in the first semiconductor layer 7 is independent of the TID charge amount, thereby achieving adaptive control.
In summary, the semiconductor device provided by the embodiment of the invention has the characteristics of low power consumption, self-adaptive radiation resistance. The technical scheme provided by the embodiment of the invention can realize self-adaption and non-volatile regulation and control of the threshold voltage of the MOSFET based on the SOI platform so as to inhibit device leakage and threshold voltage drift caused by radiation charge and enhance the radiation resistance of the system.
Example two
The embodiment of the invention provides a semiconductor device manufacturing method, which is used for manufacturing the semiconductor device provided by the embodiment of the invention and comprises the following steps:
as shown in fig. 1 and 2, an SOI substrate 100 is provided; the SOI substrate 100 includes a substrate layer 4, a first insulating layer 3, and a second semiconductor layer 2. Wherein the substrate layer 4 is a silicon substrate, the conductivity type of which is not limited, and the second semiconductor layer 2 can be a silicon layer, and the conductive structure is formed by implanting dopant. The first insulating layer 3 is located between the substrate layer 4 and the second semiconductor layer 2, and may be made of silicon dioxide material. The second semiconductor layer 2 is used to configure a voltage such that charges of the first semiconductor layer 7 can be injected into the charge trapping structure 200, and thus, the second semiconductor layer 2 can also be defined as a configuration layer. The first semiconductor layer 7 and the second semiconductor layer 2 may be made of a single crystal silicon material.
As shown in fig. 1 and fig. 3a to 3c, a charge trapping structure 200 is formed by stacking from bottom to top on an SOI substrate 100.
Wherein the charge trapping structure 200 is a dielectric layer stack and is located below the first semiconductor layer 7, the charge trapping structure 200 may generate charge accumulation due to radiation effects. Since the generation of charge is related to the total thickness of the charge trapping structure 200 below the first semiconductor layer 7, the total thickness of the charge trapping structure 200 should be as small as possible.
Accordingly, the formation of the charge trapping structure 200 stacked from bottom to top on the SOI substrate 100 includes the steps of:
as shown in fig. 3a, a first buried oxide layer 1 is formed on an SOI substrate 100, and a high-dielectric-constant dielectric material (i.e., a high-k dielectric material) such as silicon dioxide, hafnium oxide, or aluminum oxide may be used for the first buried oxide layer 1. The high dielectric constant dielectric material can increase the barrier height of the first buried oxide layer 1, can inhibit electrons from being injected from the second semiconductor layer 2 or from a channel in the erasing process, improves the erasing efficiency and inhibits the erasing saturation.
As shown in fig. 3b, the first buried oxide layer 1 is thinned. The thinning of the first buried oxide layer 1 is specifically for improving the control capability of the second semiconductor layer 2 on the charge trapping structure 200, and improving the efficiency of storing and removing electrons or holes. The method for thinning the first buried oxide layer 1 can adopt chemical mechanical polishing or reactive ion etching. The thickness of the first buried oxide layer 1 is finally made smaller than the thickness of the charge trapping layer 5.
As shown in fig. 3c, the first buried oxide layer 1 is thinned, and then surface pre-cleaning is performed to form a charge trapping layer 5 on the first buried oxide layer 1 and a second buried oxide layer 6 on the charge trapping layer 5.
Wherein the thickness of the charge trapping layer 5 is close to that of the first buried oxide layer 1. The charge trapping layer 5 can be made of silicon nitride or silicon oxynitride, the silicon nitride and the silicon oxynitride have deep energy level defects, charges can be stored in discrete defect states, leakage is not prone to occurring, reliability is good, meanwhile, a tunneling electric field is enhanced, and configuration speed is increased. The charge-trapping layer 5 described above may be formed on the first buried oxide layer 1 by, for example, chemical vapor deposition.
Wherein the second buried oxide layer 6 is formed on the charge trapping layer 5 by deposition, and the second buried oxide layer 6 is thinner than the charge trapping layer 5 and the first buried oxide layer 1, so as to isolate the charge trapping layer 5 from the first semiconductor layer 7, and ensure that electrons in the channel of the first semiconductor layer 7 can tunnel into the charge trapping layer 5. The material of the second buried oxide layer 6 can be the same as that of the first buried oxide layer 1.
As shown in FIG. 4, a first semiconductor layer 7 is formed on the charge trapping structure 200. The first semiconductor layer 7 is used to form the relevant functional electrode of the front-end MOSFET and can therefore be defined as a functional layer.
The first semiconductor layer 7 may be prepared on the second buried oxide layer 6 by a Smart-cut technique, specifically, ions are implanted into a semiconductor material such as a single crystal silicon surface to form a bubble layer, the semiconductor material remains on the upper surface of the bubble layer, and the implanted ions may be hydrogen ions or helium ions. And then bonding the upper surface of the bubble layer with the second buried oxide layer 6, intelligently peeling the bonding piece along the bubble layer, annealing and chemically and mechanically polishing, and finally forming a first semiconductor layer 7 on the second buried oxide layer 6.
It should be understood that the specific method for forming the first semiconductor layer 7 on the second buried oxide layer 6 is not limited, and other forming methods are within the scope of the embodiments of the present invention.
As shown in fig. 5a to 5d, forming MOS devices, including but not limited to forming gates and source/drains, on the first semiconductor layer 7 includes the following steps:
as shown in fig. 5a, a gate oxide layer 8 is formed on the first semiconductor layer 7, wherein the gate oxide layer 8 may be prepared by a rapid thermal oxidation method, or by other possible methods such as chemical vapor deposition.
As shown in fig. 5b, a polysilicon gate 9 is deposited on the gate oxide layer 8, and the gate oxide layer 8 and the polysilicon gate 9 are patterned to obtain a gate.
As shown in fig. 5c, spacers 10 are formed outside the gate.
A spacer material layer covering the first semiconductor layer 7 is formed, and patterning, such as dry etching, is performed to obtain the spacer 10. The material of the sidewall 10 may be one of silicon nitride, silicon oxynitride (SiON), silicon oxycarbide (SiCON), and silicon oxyboride (SiBON).
As shown in fig. 5d, doping is performed on both sides of the gate to form doped regions corresponding to the source/drain. Wherein, a dopant may be implanted into the first semiconductor layer 7 at two sides of the gate by ion implantation to form source/drain doped regions 11 corresponding to the source/drain.
In an application example, two pairs of MOS devices connected in series are formed on the first semiconductor layer 7, that is, as shown in fig. 1 and fig. 5d, two gates and three source/drains are formed on the first semiconductor layer. It should be understood that the type, size and series-parallel structure of the NP type MOS device fabricated in the first semiconductor layer 7 are not limited, and other MOS devices are all within the protection scope of the embodiment of the present invention.
As shown in fig. 6a to 6e, the formation of the body contact electrode 300 on the second semiconductor layer 2 of the SOI substrate 100 includes the steps of:
as shown in FIG. 6a, a via hole is formed at the side of the source/drain doped region 11 corresponding to the source/drain, specifically, the first semiconductor layer 7 and the charge trapping structure 200 are patterned to obtain the via hole.
As shown in fig. 6a, the second semiconductor layer 2 of the SOI substrate 100 is doped in the region corresponding to the through hole, resulting in a first doped region 12. The doping element of the first doping region 12 includes, but is not limited to, at least one of boron, phosphorus and arsenic. Doping at the bottom of the via hole can effectively reduce the contact resistance between the body contact electrode 300 and the second semiconductor layer 2.
As shown in fig. 6b, a first dielectric layer 13 is formed at least in the via hole covering the first doped region 12 for body contact electrode 300, gate and source/drain dielectric isolation of each electrode 16 in the semiconductor device. The first dielectric layer 13 fills the via hole and covers the first semiconductor layer 7 and the gate.
As shown in FIG. 6c, the first dielectric layer 13 is patterned to obtain a first contact hole 14, and the first contact hole 14 penetrates the first semiconductor layer 7 and the charge trapping structure 200. Meanwhile, the patterning process is performed on the first dielectric layer 13, and contact holes corresponding to the gate and the source/drain may also be obtained, and certainly, the contact holes corresponding to the gate and the source/drain may also be separately performed after the preparation of the body contact electrode 300 is completed. When the first contact hole, the grid electrode and the contact hole corresponding to the source/drain electrode are formed simultaneously, the subsequent electrode preparation process of the MOS device can be saved.
As shown in fig. 6d, a metal silicide layer 15 is formed on the first doped region 12, specifically, a metal is deposited in the first contact hole 14, and then a rapid thermal anneal is performed to react the metal with silicon to form a metal silicide while activating the doping element. The silicide may further reduce contact resistance. When the source/drain corresponding contact holes are also formed at the same time when the first contact holes 14 are formed, the metal silicide layer 15 is also formed at the source/drain corresponding contact holes.
As shown in fig. 6d, an electrode 16 connected to the metal silicide layer 15 is formed in the first contact hole 14, and the electrode 16 is formed by filling metal. When contact holes corresponding to the gate and the source/drain may be formed at the same time when the first contact hole 14 is formed, the contact holes corresponding to the gate and the source/drain may be also filled with metal.
As shown in fig. 6e, the first dielectric layer 13 and the electrode 16 are planarized, for example by chemical mechanical polishing. Thus, the manufacturing of the semiconductor device provided by the embodiment of the present invention is completed.
In the foregoing description of embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present invention, and shall cover the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (10)

1. A semiconductor device, comprising:
an SOI substrate;
a charge-trapping structure and a first semiconductor layer formed on the SOI substrate are stacked from bottom to top, the charge-trapping structure being a stacked structure formed of a plurality of dielectric layers;
and a body contact electrode formed on the second semiconductor layer of the SOI substrate, the charge-trapping structure for trapping charges in the first semiconductor layer when a voltage is applied to the body contact electrode to form a first electric field for neutralizing a second electric field generated by the charge-trapping structure due to a radiation effect.
2. The semiconductor device according to claim 1, wherein the charge trapping structure is configured to trap electrons of the first semiconductor layer when a positive voltage is applied to the body contact electrode;
and/or the charge trapping structure is configured to release trapped electrons to the first semiconductor layer when a negative voltage is applied to the body contact electrode.
3. The semiconductor device according to claim 1 or 2, wherein the charge trapping structure comprises a first buried oxide layer, a charge trapping layer, and a second buried oxide layer, which are stacked from bottom to top and formed on the SOI substrate, the charge trapping layer being configured to trap electrons of the first semiconductor layer when a positive voltage is applied to the body contact electrode.
4. The semiconductor device according to claim 3, wherein the charge trapping layer is a silicon nitride layer or a silicon oxynitride layer.
5. The semiconductor device according to claim 3, wherein a thickness of the second buried oxide layer is smaller than a thickness of the first buried oxide layer and smaller than a thickness of the charge trapping layer; and/or the thickness of the first buried oxide layer is smaller than that of the charge trapping layer.
6. The semiconductor device of claim 5, wherein the first buried oxide layer is one of a silicon dioxide material layer, an aluminum oxide material layer, and a hafnium oxide material layer; and/or the second buried oxide layer is one of a silicon dioxide material layer, an aluminum oxide material layer and a hafnium oxide material layer.
7. A semiconductor device manufacturing method for manufacturing the semiconductor device according to any one of claims 1 to 6, comprising the steps of:
providing an SOI substrate;
forming a charge-trapping structure and a first semiconductor layer on the SOI substrate in a stacking manner from bottom to top, wherein the charge-trapping structure is a stacked structure formed by a plurality of dielectric layers;
a body contact electrode is formed on the second semiconductor layer of the SOI substrate, the charge-trapping structure being configured to trap charges in the first semiconductor layer when a voltage is applied to the body contact electrode to form a first electric field that is configured to neutralize a second electric field generated by the charge-trapping structure due to radiation effects.
8. The method for manufacturing a semiconductor device according to claim 7, wherein the forming of the charge trapping structure on the SOI substrate by stacking from bottom to top comprises:
forming a first buried oxide layer on the SOI substrate;
thinning the first buried oxide layer;
forming a charge trapping layer on the first buried oxide layer for trapping charges in the first semiconductor layer when a voltage is applied to the body contact electrode;
forming a second buried oxide layer on the charge trapping layer, the second buried oxide layer having a thickness less than the thickness of the first buried oxide layer and less than the thickness of the charge trapping layer; and/or the thickness of the first buried oxide layer is smaller than that of the charge trapping layer.
9. The semiconductor device manufacturing method according to claim 8, wherein the forming of the body contact electrode in the SOI substrate comprises:
patterning the first semiconductor layer and the charge trapping structure to form a through hole;
doping a region of the second semiconductor layer of the SOI substrate corresponding to the through hole to obtain a first doped region;
and forming a metal silicide layer on the first doping region, and forming an electrode on the metal silicide layer to obtain the body contact electrode.
10. The method of claim 9, wherein forming a metal silicide layer on the first doped region and forming an electrode on the metal silicide layer to obtain the body contact electrode comprises:
forming a first dielectric layer covering the first doping region at least in the through hole;
patterning the first dielectric layer to obtain a first contact hole, wherein the first contact hole penetrates through the first semiconductor layer and the charge trapping structure;
and forming a metal layer in the region of the first doping region corresponding to the first contact hole, carrying out heat treatment on the metal layer to form a metal silicide layer in the first doping region, and forming an electrode connected with the metal silicide layer in the first contact hole to obtain the body contact electrode.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103367450A (en) * 2013-05-09 2013-10-23 北京大学 Radiation-hardened SOI (silicon-on-insulator) device and preparation method thereof
CN109087947A (en) * 2017-06-14 2018-12-25 格芯公司 Including having the transistor unit for increasing powerful embedding formula insulating layer
CN110890418A (en) * 2019-12-02 2020-03-17 中国科学院上海微系统与信息技术研究所 Transistor structure with double buried oxide layers and preparation method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7057234B2 (en) * 2002-12-06 2006-06-06 Cornell Research Foundation, Inc. Scalable nano-transistor and memory using back-side trapping
US9941300B2 (en) * 2015-12-16 2018-04-10 Globalfoundries Inc. Structure and method for fully depleted silicon on insulator structure for threshold voltage modification

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103367450A (en) * 2013-05-09 2013-10-23 北京大学 Radiation-hardened SOI (silicon-on-insulator) device and preparation method thereof
CN109087947A (en) * 2017-06-14 2018-12-25 格芯公司 Including having the transistor unit for increasing powerful embedding formula insulating layer
CN110890418A (en) * 2019-12-02 2020-03-17 中国科学院上海微系统与信息技术研究所 Transistor structure with double buried oxide layers and preparation method thereof

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