CN208225884U - Transistor and semiconductor devices - Google Patents
Transistor and semiconductor devices Download PDFInfo
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- CN208225884U CN208225884U CN201820325840.9U CN201820325840U CN208225884U CN 208225884 U CN208225884 U CN 208225884U CN 201820325840 U CN201820325840 U CN 201820325840U CN 208225884 U CN208225884 U CN 208225884U
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Abstract
The utility model provides a kind of transistor and semiconductor devices.Since the gate dielectric layer of transistor has different thickness in different zones, the average thickness that i.e. gate dielectric layer corresponds to the overlapping region of grid conducting layer and source/drain regions is greater than the average thickness that gate dielectric layer corresponds to channel region, therefore, it can not only ensure the switch performance of transistor, and the grid sensing leakage current (GIDL) for improving transistor is also helped, to can further improve the reliability of the semiconductor devices with the transistor.
Description
Technical field
The utility model relates to technical field of semiconductors, in particular to a kind of transistor and a kind of semiconductor devices.
Background technique
With the continuous reduction of dimensions of semiconductor devices, the characteristic size of field effect transistor also reduces rapidly, corresponding
The thickness of gate dielectric layer is also more and more thinner, the problem of bring device reliability energy also increasingly due to thin gate dielectric layer
It is prominent.
Specifically, since transistor device is more and more thinner, produced by transistor is in the off state or under wait state
Grid sensing leakage current (gate-induced drain leakage, GIDL) it is also increasingly severe, this can be to transistor
Reliability generates large effect, and the unstability for leading to transistor and the quiescent dissipation that can make transistor increase.Meanwhile by
In grid induced drain Leakage Current (GIDL), it is serious to constrain the diminution of gate dielectric layer thickness, and then also limits crystalline substance
The size of body pipe can not further reduce.
As it can be seen that how the increase of the integrated level with integrated circuit, the continuous reduction of transistor feature size, reduce device
Leakage current have become high density, low-power consumption semiconductor technology a critical issue.
Utility model content
The purpose of this utility model is to provide a kind of transistor, the transistor has lesser leakage current.
A kind of transistor provided by the utility model, comprising:
One substrate is formed with a source region, a drain region and the grid between the source region and the drain region in the substrate
Pole groove, and the bottom of the gate trench of the substrate is more sunken to down the source region and the drain region, to constitute crystal
Channel region is buried in pipe；
One gate dielectric layer covers the part that the channel region is corresponded in the substrate, and extends over the source region
With side of the drain region in the gate trench；Wherein, the part of the channel region is covered in the gate dielectric layer
First layer portion is constituted, the portion of the side of the source region and the drain region in the gate trench is covered in the gate dielectric layer
Divide the second layer portion that constitutes, the average thickness in the second layer portion is greater than the average thickness in the first layer portion；And
One grid conducting layer is formed on the gate dielectric layer of the substrate and is located in the gate trench, and
And the grid conducting layer extends to the second layer portion from the first layer portion of the gate dielectric layer, so that the grid
Conductive layer all has an overlapping region with the source region and the drain region respectively.
Optionally, the source region and the drain region are close to opening portion and the source region and the institute of the gate trench
The lateral margin boundary for stating drain region all extends to the gate trench close to the side wall of the opening portion；
The gate dielectric layer covers the bottom wall and side wall of the gate trench, and described the of the gate dielectric layer
Two layers of portion cover the gate trench close to the part of the opening portion, so that the second layer portion covers the source region and described
The part of the gate trench sidewalls is extended in drain region；And
The grid conducting layer is filled in the gate trench and the grid conducting layer and is opened close to the gate trench
The part of oral area has the overlapping region with the source region and the drain region.
Optionally, the internal stretch of the source region and the drain region from the top surface of the substrate to the substrate is to
One depth, the top surface of the grid conducting layer are not higher than the top surface of the substrate and are located at the second depth of the substrate；
Also, first depth be greater than second depth so that the source region and the drain region respectively with the grid conducting layer
It is mutually overlapping in the depth intervals of first depth to second depth.
Optionally, the top of the grid conducting layer is lower than the opening portion of the gate trench, to form an accommodating space
Top in the gate trench and positioned at the grid conducting layer；And the transistor further include:
One insulating layer is filled in the accommodating space of the gate trench, to cover the grid conducting layer.
Optionally, the average thickness in the first layer portion of the gate dielectric layer is less than 3nm, the gate dielectric layer
The average thickness in the second layer portion is more than or equal to 3nm.
Optionally, a separation layer is also formed on the substrate, the separation layer covers the substrate and corresponds to the source region
With the top surface of the source region.
Optionally, a well region is also formed in the substrate, the source region and the drain region are both formed in the well region.
Optionally, the first layer portion (110a) of the gate dielectric layer has first thickness and second thickness, described
Second layer portion (110b) has the second thickness, and it is described overlapping that there is the part of the second thickness to be located in the first layer portion
The intersection in region (D) and the channel region (C), and from the intersection of the overlapping region and the channel region to institute
The center of channel region is stated, the first layer portion is reduced to the first thickness by the second thickness.
The further object of the utility model is to provide a kind of semiconductor devices, and the semiconductor devices includes as described above
Transistor.
Optionally, the semiconductor devices is memory, and brilliant using the storage that the transistor constitutes the memory
Body pipe.
Optionally, the memory has at least one active area, and the memory transistor is formed in the active area.
Optionally, the memory transistor there are two being formed in an active area of the memory, and two
The source region of the memory transistor shares.
In transistor provided by the utility model, gate dielectric layer has different thickness in different zones, that is, makes
Overlapping region of the gate dielectric layer in grid conducting layer and source/drain regions has bigger thickness, so as to which crystal is effectively relieved
Grid sensing leakage current (GIDL) phenomenon of pipe；Also, in the case where increase gate dielectric layer corresponds to the thickness of overlapping region,
The thickness of channel region is corresponded to without significantly changing gate dielectric layer, to still be able to ensure the switch performance of transistor.It can
See, transistor provided by the utility model, in the case where complying with the trend of device size constantly reduced, can be opened based on it is not changed
In the case where opening voltage, while the leakage phenomenon of transistor is effectively reduced, to provide the overall performance of transistor.
Detailed description of the invention
Fig. 1 a is the structural schematic diagram of the transistor in the utility model embodiment one；
Fig. 1 b is the enlarged diagram of transistor its gate dielectric layer in the utility model embodiment one；
Fig. 2 is the structural schematic diagram of the semiconductor devices in the utility model embodiment two；
Fig. 3 is the flow diagram of the forming method of the transistor in the utility model embodiment three；
Fig. 4 a~Fig. 4 g is knot of the forming method of the transistor in the utility model embodiment three in its preparation process
Structure schematic diagram.
Wherein, appended drawing reference is as follows:
Substrate；200a- doped region；
Source region；The first area 201a-；
Drain region；202a- second area；
Gate trench；Gate dielectric layer；
110a/210a- first layer portion；110b/210b- second layer portion；
Grid conducting layer；Insulating layer；
Separation layer；250- isolation structure；
260- region of variability；
C- channel region；D- overlapping region；
W- well region；AA- active area；
+ X- first direction；- X- second direction；
L1- first thickness；L2- second thickness.
Specific embodiment
It is to ensure its normal function in existing transistor, it usually needs its gate structure is made to extend to source region and leakage
An overlapping region is all had between area, i.e. gate structure and source region and drain region.However, just because of between gate structure and drain region
There are the overlapping regions, to be easy the phenomenon that causing grid sensing leakage current (GIDL), make grid sensing leakage current
(GIDL) become one of the principal element of device creepage.
In order to solve the above technical problems, traditional method is will to increase the thickness of gate dielectric layer or gently mixed using drain electrode
Miscellaneous (LDD) technology.But the thickness for increasing gate dielectric layer can further result in the increase of cut-in voltage and power consumption, and make
(LDD) technology, which is lightly doped, with drain electrode will increase fabrication processing and cost.
In view of this, the present invention provides a kind of transistor, the transistor can not change opening for transistor
Under the premise of opening voltage and dynamic power consumption, the phenomenon that improving grid sensing leakage current (GIDL) of transistor, to improve transistor
Reliability and the quiescent dissipation of transistor can be reduced, be conducive to the overall performance for promoting transistor.
Below in conjunction with the drawings and specific embodiments to the utility model proposes transistor and forming method thereof, semiconductor device
Part is described in further detail.According to following explanation, will be become apparent from feature the advantages of the utility model.It should be noted that attached
Figure is all made of very simplified form and using non-accurate ratio, only to convenient, lucidly aid illustration is originally practical new
The purpose of type embodiment.
Embodiment one
Fig. 1 a is the structural schematic diagram of the transistor in the utility model embodiment one, and Fig. 1 b is the utility model embodiment
The enlarged diagram of transistor its gate dielectric layer in one.As shown in Fig. 1 a and Fig. 1 b, transistor includes:
One substrate 100 is formed with a source region 101 and a drain region 102 in the substrate 100, and in the substrate 100 from
The source region 101 is used to constitute the channel region C of the transistor to the part in the drain region 102；
One gate dielectric layer 110 covers the part for corresponding to the channel region C in the substrate 100, and extends over institute
State source region 101 and the drain region 102；Wherein, the part that the channel region C is corresponded in the gate dielectric layer 100 constitutes the
One layer of portion 110a, the part that the source region 101 and the drain region 102 are covered in the gate dielectric layer 110 constitute second layer portion
The average thickness of 110b, the second layer portion 110b are greater than the average thickness of the first layer portion 110a；And
One grid conducting layer 120 is formed on the gate dielectric layer 110 of the substrate 100, and the grid is led
Electric layer 120 extends to the second layer portion 110b from the first layer portion 110a of the gate dielectric layer 110, so that the grid
Pole conductive layer 120 has an overlapping region D with the source region 101 and the drain region equal 102 respectively.
That is, the gate dielectric layer 110 due to transistor has different thickness in different zones, and specifically, corresponding ditch
Road region C has first thickness, and corresponding source region 101 and drain region 102 have second thickness, and second thickness is greater than the first thickness
Degree.Wherein, the gate dielectric layer 110 the average thickness of the first layer portion 110a of corresponding channel region C can be according to its crystal
The actual demand of pipe adjusts, to ensure that the conduction property of transistor will not be impacted, to will not make the unlatching of transistor
Voltage increases；On this basis, it can accordingly increase the second layer portion 110b's that source region and drain region are corresponded in gate dielectric layer 110
Average thickness makes the average thickness of second layer portion 110b be greater than the average thickness of first layer portion 110a, can so be effectively relieved
Grid sensing leakage current (GIDL), reduces the leakage current of transistor, to further increase the overall performance of transistor.As it can be seen that this
The transistor that utility model provides on the basis of guaranteeing the conduction property of transistor, can reduce the grid induction electric leakage of transistor
Electric current (GIDL), and then the overall performance of transistor can be improved.In specific embodiment, the gate dielectric layer 110
The second thickness of second layer portion 110b is, for example, to be more than or equal to 3nm, and the of the first layer portion 110a of the gate dielectric layer 110
One thickness is, for example, to be less than 3nm, and the first thickness of the first layer portion 110a may further be 2nm.
It continues to refer to figure 1 shown in b, in preferred scheme, the first layer portion 110a of the gate dielectric layer 110 is not only
With first thickness L1, also there is second thickness L2, wherein second thickness is greater than first thickness.The first layer portion 110a has
The part of the second thickness L2 the overlapping region D and the channel region C intersection, and from the overlapping region
The boundary of D and the channel region C are contracted by second thickness L2 to the center of the channel region C, the first layer portion 110a
Reduce to first thickness L1.It is to be understood that from the channel region C close to the part of overlapping region D to the overlapping region
The thickness of D, the gate dielectric layer 110 gradually increase so that gate dielectric layer 110 channel region C boundary (that is, ditch
The intersection of road region C and overlapping region D) also have biggish thickness accordingly, further alleviate overlapping region D close to channel
The grid sensing leakage current (GIDL) of the boundary of region C.
It should be appreciated that the average thickness of the second layer portion 110b with second thickness be still greater than with first thickness and
The average thickness of the first layer portion 110a of second thickness.
It should be noted that the transistor can be planar ransistor, or groove transistor npn npn.The present embodiment
In, it is explained for constituting transistor npn npn.
It continues to refer to figure 1 shown in a, a gate trench 103 is formed in the substrate 100, the gate trench 103 is located at
Between the source region 101 and the drain region 102, and the bottom of the gate trench 103 of the substrate be more sunken to down it is described
Source region 101 and the drain region 102, bury channel region to constitute in transistor.Wherein, the source region 101 and the drain region 102
The lateral margin boundary of the opening portion and the source region 101 and the drain region 102 that are close to the gate trench 103 all extends to
Side wall of the gate trench 103 close to opening portion.The gate dielectric layer 110 cover the gate trench 103 bottom wall and
Side wall, and the gate dielectric layer 110 covers the side of the source region 101 and the drain region 102 in gate trench 103,
Wherein, the second layer portion 110b of the gate dielectric layer 110 covers the gate trench close to the part of opening portion, so that
The second layer portion 110b covers the portion that 103 side wall of gate trench is extended in the source region 101 and the drain region 102
Point.And the grid conducting layer 120 is filled in the gate trench 103 and the grid conducting layer 120 close to described
The part of 103 opening portion of gate trench has the overlapping region D with the source region 101 and the drain region 102.
As shown in Figure 1a, it for channel transistor, is made of grid conducting layer 120 and gate dielectric layer 110
Gate structure is formed in gate trench 103, and the source region 101 and the drain region 102 are separately positioned on grid and constitute 103
Two sides, therefore, it is trenched side-wall and groove bottom wall along gate trench 103 from source region that channel region C is buried in transistor
101 to the region between the drain region 102.That is, in transistor turns, substrate 100 close to the side wall of gate trench 103 and
In the region (corresponding channel region C) of bottom wall can transoid form a U-shaped conducting channel, be equivalent to from source electrode 101 to drain electrode 102
Current flow paths U-shaped path is presented, to improve the length of conducting channel.In this way, with memory-size
Reduction, even if the absolute distance between source region 101 and drain region 102 reduces, however, being U-shaped lead due to being formed by conducting channel
Electric channel, so as to be effectively improved the short-channel effect of transistor.
Further, the source region 101 and the drain region 102 are from the top surface of the substrate 100 to the substrate 100
Internal stretch to the first depth of the substrate, the top surface of the grid conducting layer 120 is not higher than the substrate 100
Top surface and the second depth for being located at the substrate.Also, first depth is greater than second depth, so that the source region
101 and the drain region 102 respectively with the grid conducting layer 120 in first depth to the depth intervals of second depth
It is interior mutually overlapping.That is, the region between first depth and second depth constitutes the overlapping region D.
In preferred scheme, the top surface of the grid conducting layer 120 is lower than the top surface of the substrate 100, i.e., described
The top surface of grid conducting layer 120 is lower than the top boundary of the source region 101 and the drain region 102.In this way, grid can be reduced
Pole conductive layer 120 covers the area of source region and drain region, so as to be effectively improved electric field change and the phenomenon that generate junction current.
From the above, the top surface of grid conducting layer 120 is lower than the top surface of the substrate 100, that is, the grid
The top of pole conductive layer 120 is lower than the opening portion (or the opening portion that may be considered gate trench) of the gate trench 103,
To the top that may make up an accommodating space in the gate trench 103 and positioned at the grid conducting layer 120.
Optionally, the transistor further includes an insulating layer 130, and the insulating layer 130 is filled in the gate trench 103
The accommodating space in, to cover the grid conducting layer 120.That is, utilizing the accommodating space of the gate trench 103
Better insulation blocking can not only be carried out to grid conducting layer 120 (for example, can avoid the offset deviation due to insulating layer 130
And the problem of causing 120 part of grid conducting layer to expose)；Also, it can also be formed self-aligned by the accommodating space
The insulating layer 130 is conducive to simplify preparation process.
It continues to refer to figure 1 shown in a, a well region W, the source region 101 and the drain region is also formed in the substrate 100
102 are both formed in the well region W, and the ion doping concentration in the well region W is lower than the source region 101 and the drain region 102
In ion doping concentration.And the doping depth of the well region W is lower than the depth of the gate trench 103, so as to be formed
It is centered around in the well region W in the grid conducting layer 120 in the gate trench 103.When the transistor conducts, in well region W
Form conducting channel.Further, the doping type of the well region W can be determined according to the type for being formed by transistor, for example,
When the transistor is N-type transistor, then the well region W can adulterate phosphonium ion (P) accordingly；When the transistor is that p-type is brilliant
Body pipe, then the well region W can adulterate boron ion (B) accordingly.
In addition, being also formed with a separation layer 140 on the substrate 100, the separation layer 140 covers the substrate and corresponds to institute
The top surface of source region 101 and the source region 102 is stated, to avoid the source region 101 and the drain region 102 from the substrate 100
Top surface exposes, so as to carry out insulation blocking to source region and drain region, prevent in subsequent manufacturing process to the source region and
It causes to damage in the drain region.
In the present embodiment, it is formed with gate trench 103 in substrate 100, can be covered based on separation layer 140 described in this described
The part of the gate trench 103 is not corresponded in substrate 100.Or, it can be understood as one, which is formed with, in the separation layer 140 opens
Mouthful, the opening is aligned with the gate trench 103, at this point, the insulating layer 130 is filling the same of the gate trench 103
When, the top surface of the top surface and the separation layer 140 of the insulating layer 130 filled the opening, and then autoregistration can be made to be formed
It flushes.
Embodiment two
Based on above-described transistor, the utility model additionally provides a kind of semiconductor devices, the semiconductor devices
Including transistor as described above.In the present embodiment, by taking the semiconductor devices is memory as an example, and using as described above
Transistor constitute memory memory transistor for be explained.
Fig. 2 is the structural schematic diagram of the semiconductor devices in the utility model embodiment two.As shown in Fig. 2, described partly lead
Body device has at least one active area AA, and the memory transistor is formed in active area AA described in the active area.This
In embodiment, the memory have multiple active area AA, the adjacent active area AA using an isolation structure 250 mutually every
From.
Specifically, the memory transistor includes:
One substrate 200, definition has at least one active area AA on the substrate 200；And the lining in the active area AA
It is formed with a source region 201 and a drain region 202 in bottom 200, and is used for structure from the source region 201 to the substrate in the drain region 202
At the channel region C of memory transistor；
One gate dielectric layer 210 covers the part for corresponding to the channel region C in the substrate 200, and extends over institute
State source region 201 and the drain region 202；Wherein, the part that the channel region C is covered in the gate dielectric layer 210 constitutes the
One layer of portion 210a, the part that the source region 201 and the drain region 202 are covered in the gate dielectric layer 210 constitute second layer portion
The average thickness of 210b, the second layer portion 210b are greater than the average thickness of the first layer portion 210a；And
One grid conducting layer 220 is formed on the gate dielectric layer 210 of the substrate 200, and the grid is led
Electric layer 220 extends to the second layer portion 210b from the first layer portion 210a of the gate dielectric layer 210, so that the grid
Pole conductive layer 220 all has an overlapping region D with the source region 201 and the drain region 202 respectively.
Since in storage transistor, gate dielectric layer has different thickness on different location, so as to ensure
On the basis of the conduction property (for example, the cut-in voltage for not influencing transistor) of memory transistor, improve the grid of memory transistor
Sensing leakage current (GIDL), to reduce the leakage current of memory transistor, so that the overall performance of memory transistor can be improved, into
And the performance of semiconductor devices can be correspondingly improved.Wherein, the first layer portion 210a's of the gate dielectric layer 210 is flat
Equal thickness is, for example, to be less than 3nm, and the average thickness of the second layer portion 210b of the gate dielectric layer 210, which is greater than, to be equal to
3nm。
In the present embodiment, transistor is used to constitute the memory transistor of memory, therefore the grid conducting layer 220 can phase
That answers is connected to the wordline of memory, and the source region 201 can be connected to bit line and the drain region 202 of memory accordingly
It can be connected on the capacitor of memory.
With continued reference to shown in Fig. 2, in the present embodiment, formed there are two described in an active area AA of memory
Memory transistor, and the source region 201 of two memory transistors shares, to constitute a memory transistor pair.
As embodiment one kind, the memory transistor is groove transistor npn npn, to improve storage unit in memory
Concentration.That is, gate trench 203 is formed in substrate 200, the gate dielectric layer 210 and the grid conducting layer
220 are sequentially formed in the gate trench 203.
Further, the top of the grid conducting layer 220 is lower than the opening portion of the gate trench 203, thus in grid
Pole, which is constituted, can be formed above an accommodating space in 203 and positioned at the grid conducting layer 220.And in the accommodating space
It is also filled with insulating layer 230, to carry out insulation blocking to grid conducting layer 220 using the insulating layer 230.
With continued reference to shown in Fig. 2, being also formed with a well region W, the source region 201 and the drain region in the substrate 200
202 are both formed in the well region W.In addition, being also formed with a separation layer 240 on the substrate 200, the separation layer 240 covers
The top surface that the substrate corresponds to the source region 201 and the source region 202 is covered, to avoid the source region 201 and the drain region 202
It is exposed from the top surface of the substrate 200, so as to carry out insulation blocking to source region and drain region, prevents subsequent manufacturing process
In the source region and the drain region are caused to damage.
Embodiment three
Fig. 3 is the flow diagram of the forming method of the transistor in the utility model embodiment three, and Fig. 4 a~Fig. 4 g is
Structural schematic diagram of the forming method of transistor in the utility model embodiment three in its preparation process.In addition, this implementation
The forming method of the semiconductor devices with transistor as described above is combined to be illustrated in example.
In the present embodiment, the semiconductor devices with transistor as described above is memory, therefore below with reference to the accompanying drawings,
And the forming method of binding crystal pipe is illustrated the forming method of memory.
In the step s 100, with reference to shown in Fig. 4 a and Fig. 4 b, a substrate 200 is provided, has one to use in the substrate 200
It is used to form the second area 202a in drain region in the first area 201a and one for forming source region, and from institute in the substrate 200
State the channel region C that first area 201a is used to constitute transistor to the part of the second area 202a.
Further, it is formed with a well region W in the substrate 200, it is subsequent to be formed by source region and drain region is both formed in institute
It states in well region W.Wherein, the source region and the drain region can be formed before forming gate dielectric layer, can be led in this step
Ion implantation technology is crossed to be doped the first area 201a and second area 202a；Grid conducting layer can also formed
Shape later is formed after the gate structure for forming transistor.
In the present embodiment, transistor is formed by as groove transistor npn npn, therefore subsequent needs shape in the substrate 200
At gate trench.Based on this, the forming step of source region, drain region and gate trench can be combined in the present embodiment, with letter
Change process flow.
Specifically, the forming step of the source region, drain region and gate trench includes:
Firstly, ion implantation technology is executed to the substrate 200, with reference to shown in Fig. 4 a to be formed in the substrate 200
Internal stretch of one the doped region 200a, the doped region 200a from the top surface of the substrate 200 to the substrate 200；It needs
It is bright, at this time doped with ion in the first area 201a and second area 20a, and the doped region 200a
It is formed in the well region W, the doping concentration of the doped region 200a is greater than the doping concentration of the well region W；
Then, with reference to shown in Fig. 4 b, a gate trench 203 is formed in the substrate 200, and utilize the gate trench
203 separate the first area 201a and second area 202a, and the doped region being located in the first area 201a
The source region 201 is constituted, the doped region in the second area 202a constitutes the drain region 202.Or it also will be understood that
For, so that the doped region is separated into multistage using the gate trench 203, and be located at the gate trench 203 it is opposite two
Doped region on side has respectively constituted the source region 201 and the drain region 202.
As shown in Figure 4 b, for groove transistor npn npn, from the first area 201a (source region 201) in the substrate 200
It to the part of the second area 202a (drain region 202), i.e., is accordingly that the gate trench 203 is surrounded in the substrate 200
Boundary and from the source region 201 to the part between the drain region 202.Therefore, it is formed by the channel of groove transistor npn npn
Region C is the region for surrounding 203 boundary of gate trench.
It further include forming a separation layer on the substrate 200 before executing ion implantation technology in preferred scheme
240, the separation layer 240 covers the top surface of the substrate 200.In this way, in subsequent execution ion implantation technology to form weight
When doped region 200a, injection ion passes through the separation layer 240 and is injected into the substrate 200, and it is direct to avoid injection ion
From the top surface injection exposed, the problem of damage is caused to substrate due to ion implantation technology is effectively improved.It is based on
This executes etching technics to the separation layer 240 and the substrate 200 simultaneously when being subsequently formed gate trench 203, with
The gate trench 203 is formed, and remaining separation layer 240 is made to cover the portion for corresponding to source region 201 and drain region 202 in substrate 200
Point.
In addition, being formed by transistor for constituting the memory transistor of memory in the present embodiment.It is deposited that is, being equivalent to
The forming method of reservoir, therefore, can define on the substrate 200 has multiple active area AA for being used to form memory transistor,
And it is mutually isolated using isolation structure 250 between adjacent active area AA.It further, can shape in an active area AA
At there are two memory transistors, and two memory transistors can share source region 201, i.e., the described source region 201 is formed in two and deposits
It stores up between transistor.
In step s 200, with reference to shown in Fig. 4 c~Fig. 4 e, a gate dielectric layer 210 is formed on the substrate 200, institute
It states gate dielectric layer 210 and covers the part for corresponding to the channel region C in the substrate 200, and extend over firstth area
The domain 201a and second area 202a.In the present embodiment, before forming the gate dielectric layer 210, in the firstth area
Source region is formed in domain and forms drain region in the second area, therefore the gate dielectric layer 210 extends over the source region 201
With the drain region 202.
Wherein, the part that the channel region C is corresponded in the gate dielectric layer 210 constitutes first layer portion 210a, described
The part that the source region and the drain region are covered in gate dielectric layer 210 constitutes second layer portion 210b, and the second layer portion
The average thickness of 210b is greater than the average thickness of the first layer portion 210a.
That is, be formed by gate dielectric layer 210 has different thickness in different positions.A kind of grid presented below
The preparation method of dielectric layer 210, for controlling the thickness for being formed by gate dielectric layer 210.
It is formed in the first step of gate dielectric layer 210, with specific reference to shown in Fig. 4 c and Fig. 4 d, executing inclining at least twice
Oblique ion injection technology, to form region of variability 260 on side wall of the gate trench 203 close to opening portion.Wherein, institute twice
State angled ion implantation process be between the first area (source region 201) and the second area (drain region 202) respectively with
Ion implanting is executed in the opposite direction partially, respectively in the gate trench 203 on the side wall of the source region 201 and institute
It states side wall of the gate trench close to the drain region 202 and is respectively formed on the region of variability 260.For example, inclined twice ion implanting work
Skill is respectively to be biased to the direction of the first area (source region 201) and be biased to the direction execution of the second area (drain region 202)
Ion implanting.It should be appreciated that " gate trench 203 is by source area 201 and close to the part in drain region 202 " packet described herein
Include: 203 position of gate trench corresponds to the part of the source region 201 and the drain region 202.
Specifically, by forming region of variability on the position in source area 201 and close drain region 202 in gate trench 203
260, the region of variability 260 has higher oxidation efficiency in subsequent oxidation process, thus being capable of shape on region of variability 260
At the bigger oxide layer of thickness.
Further, the region of variability 260 is, for example, the doped region doped with fluorine ion, due in the region of variability 260
Doped with fluorine ion, to have faster oxidation rate, the injection ion of the corresponding angled ion implantation process includes
Fluoride ion, or can be understood as the process gas of the angled ion implantation process is fluoro-gas, such as may include
Boron fluoride (BF3)。
In the present embodiment, the transistor is used to constitute memory transistor, and in an active area AA there are two formation
Share the memory transistor of source region 201, that is, 202, one, drain region source region of successively sequentially having arranged in an active area AA
201 and a drain region 202.Therefore, during executing angled ion implantation process, as illustrated in fig. 4 c, tilt for the first time from
When sub- injection technology, to execute ion implantation technology towards first direction (+X direction) between source region 201 and drain region 202,
In, the first direction (+X direction) is the source region to be biased to left side transistor for the left side transistor in Fig. 4 c
201 direction, and the first direction (+X direction) is for the right transistor in Fig. 4 c, is to be biased to the right transistor
Drain region 202 direction.Referring next to shown in Fig. 4 d, when second of angled ion implantation process, in source region 201 and drain region 202
Between with towards second direction (-X direction) execute ion implantation technology, wherein the second direction (-X direction) and first party
To (+X direction) be opposite direction, and, the second direction (-X direction) relative to the left side transistor in Fig. 4 d and
Speech, is the direction to be biased to the drain region 202 of left side transistor, and the second direction (-X direction) is brilliant relative to the right in Fig. 4 d
It is the direction to be biased to the source region 2012 of the right transistor for body pipe.That is, passing through inclination as above twice in the present embodiment
Ion implantation technology, to be respectively formed on region of variability in side wall of the gate trench 203 by source area 201 and close to drain region 202 respectively
260。
In preferred scheme, the region of variability 260 further extends to part from the source region 201 and the drain region 202
In the channel region C, i.e., the region of variability 260 is also formed on the part channel region C in source area 201 and drain region 202.
As shown in Fig. 4 c and Fig. 4 d, the region of variability 260 crosses the source region 201 and the boundary in the drain region 202 is continued toward the ditch
The center of road region C extends preset distance, wherein the center of the channel region C is, from the source in the substrate 200
The center of the current flow paths in area 201 to the drain region 202.
It should be noted that the forming region of the region of variability 260 can be according to the opening size of gate trench 203, accordingly
Adjusting angle-tilt ion injection when implant angle.For example, in angled ion implantation process, the angle of ion beam and substrate surface
Less than or equal to 80 °.
It is formed in the second step of gate dielectric layer 210, with specific reference to shown in Fig. 4 e, oxidation technology is executed, to form grid
Pole dielectric layer 210 is on the bottom wall and side wall of the gate trench.Wherein, the variation is corresponded in the gate dielectric layer 210
The part in area 260 has second thickness, and the part of region of variability described in non-corresponding has the first thickness in the gate dielectric layer 210
Degree；Also, the oxidation rate of the part of the corresponding region of variability 260 of the gate trench 203 is greater than the gate trench 203
The oxidation rate of the part of region of variability described in non-corresponding, so as to make second thickness be greater than first thickness.
As described above, the region of variability 260 is formed in gate trench 203 by source area 201 and close to the side wall in drain region 202
On, that is, the position in corresponding source region 201 and corresponding drain region 202 has been respectively formed on region of variability 260, therefore gate dielectric layer
The second layer portion 210b in the 210 coverings source region 201 and the drain region 202 has second thickness, and gate dielectric layer 210 is right
The first layer portion 210c of channel region C is answered at least to have first thickness.
In addition, the region of variability 260 also further extends from the source region 201 and the drain region 202 in the present embodiment
Into part channel region C, therefore, first layer of the corresponding channel region C on the region in source area 201 and drain region 202
Portion 210a also has second thickness accordingly.That is, in the present embodiment, the first layer portion 210a of the gate dielectric layer 210
With first thickness and second thickness, wherein the first layer portion 210a has second thickness in the boundary of channel region C, and
And from the boundary of the channel region C to the center of the channel region C, the first layer portion 210a is thick by described second
Degree is reduced to the first thickness.
It can make to be formed by gate dielectric layer 210 as a result, cover the first area (source region 201) and described
The average thickness of the second layer portion 210b in two regions (drain region 202) is greater than the first layer portion 210a's of the corresponding channel region C
Average thickness.
In step S300, with reference to shown in Fig. 4 f and Fig. 4 g, a grid conducting layer 220 is formed in the institute of the substrate 100
It states on gate dielectric layer 210, the grid conducting layer 220 extends from the first layer portion 210a of the gate dielectric layer 210
To the second layer portion 210b so that the grid conducting layer 220 respectively with the first area (source region 201) and described second
Region (drain region 202) all has an overlapping region D.
Second layer portion 210b due to covering source region 201 and drain region 202 in gate dielectric layer 210 has biggish thickness,
To make between grid conducting layer 220 and source region 201 and drain region 202 can be mutually isolated under the biggish dielectric layer of thickness,
To can be relieved the grid sensing leakage current (gate-induced drain leakage, GIDL) for being formed by transistor, into
And reduce the leakage current for being formed by transistor.And the base of the thickness in the second layer portion 210b for increasing gate dielectric layer 210
On plinth, it can be avoided and first layer portion 210a is impacted, therefore still can ensure that the switch performance for being formed by transistor.
Specifically, the forming step of the grid conducting layer 220 is for example are as follows:
Step 1 forms a conductive material layer on the substrate 200, and the conductive material layer covers the substrate 200
And it fills and states gate trench 203；
Step 2 is etched back to technique to conductive material layer execution, removes and cover the lining in the conductive material layer
The part at bottom 200, and retain the part for filling the gate trench 203 in the conductive material layer and led with constituting the grid
Electric layer 220.
With continued reference to shown in Fig. 4 f, in preferred scheme, in being etched back in technique to the conductive material layer, removing
It, can also be further to the conductive material layer being filled in gate trench 203 after the part for covering substrate 200 in conductive material layer
It continues to execute and is etched back to technique, to reduce the height of conductive material layer.In this way, the grid conducting layer of the final formation can be made
220 top is lower than the opening portion of the gate trench 203, so as to form an accommodating space in the gate trench 203
In and be located at the grid conducting layer 220 top.
Referring next to shown in Fig. 4 g, after filling the grid conducting layer 220, can also further comprise: filling one be absolutely
Edge layer 230 is in the accommodating space of the gate trench 203, to cover the grid conducting layer 220.That is, the insulation
Layer 230 can be filled in autoregistration in the accommodating space, so as to utilize the insulating layer 230 to the grid conducting layer
220 carry out insulation blocking.
Further, the insulating layer 230 is with can be used flatening process (for example, chemical mechanical milling tech) autoregistration
Be formed in the gate trench, i.e., be to have a polish stop layer using separation layer 240 in the present embodiment, grinding stop at every
On absciss layer 240, so that the top surface for being formed by insulating layer 230 and the top surface of the separation layer 240 be made to flush.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.
Foregoing description is only the description to the utility model preferred embodiment, not to any limit of the scope of the utility model
Fixed, any change, the modification that the those of ordinary skill in the utility model field does according to the disclosure above content belong to right and want
Seek the protection scope of book.
Claims (12)
1. a kind of transistor characterized by comprising
One substrate is formed with a source region, a drain region and the grid ditch between the source region and the drain region in the substrate
Slot, and the bottom of the gate trench of the substrate is more sunken to down the source region and the drain region, to constitute transistor
Inside bury channel region；
One gate dielectric layer covers the part that the channel region is corresponded in the substrate, and extends over the source region and institute
State side of the drain region in the gate trench；Wherein, the part that the channel region is covered in the gate dielectric layer is constituted
First layer portion covers the part structure of the side of the source region and the drain region in the gate trench in the gate dielectric layer
At second layer portion, the average thickness in the second layer portion is greater than the average thickness in the first layer portion；And
One grid conducting layer is formed on the gate dielectric layer of the substrate and is located in the gate trench, and institute
It states grid conducting layer and extends to the second layer portion from the first layer portion of the gate dielectric layer, so that the Gate Electrode Conductive
Layer all has an overlapping region with the source region and the drain region respectively.
2. transistor as described in claim 1, it is characterised in that:
The source region and the drain region are close to the opening portion of the gate trench and the lateral margin of the source region and the drain region
Boundary all extends to the gate trench close to the side wall of the opening portion；
The gate dielectric layer covers the bottom wall and side wall of the gate trench, and the second layer of the gate dielectric layer
Portion covers the gate trench close to the part of the opening portion, so that the second layer portion covers the source region and the drain region
In extend to the parts of the gate trench sidewalls；And
The grid conducting layer is filled in the gate trench and the grid conducting layer close to the gate trench opening portion
Part and the source region and the drain region there is the overlapping region.
3. transistor as claimed in claim 2, which is characterized in that the source region and the drain region are from the top table of the substrate
For internal stretch towards the substrate to the first depth, the top surface of the grid conducting layer is not higher than the top surface of the substrate
And it is located at the second depth of the substrate；Also, first depth is greater than second depth, so that the source region and described
Drain region is mutually overlapping in the depth intervals of first depth to second depth with the grid conducting layer respectively.
4. transistor as claimed in claim 2, which is characterized in that the top of the grid conducting layer is lower than the gate trench
Opening portion, with formed an accommodating space in the gate trench and be located at the grid conducting layer top；And it is described
Transistor further include:
One insulating layer is filled in the accommodating space of the gate trench, to cover the grid conducting layer.
5. transistor as described in claim 1, which is characterized in that the average thickness in the first layer portion of the gate dielectric layer
Degree is less than 3nm, and the average thickness in the second layer portion of the gate dielectric layer is more than or equal to 3nm.
6. transistor as described in claim 1, which is characterized in that be also formed with a separation layer, the isolation on the substrate
Layer covers the top surface that the substrate corresponds to the source region and the source region.
7. transistor as described in claim 1, which is characterized in that be also formed with a well region in the substrate, the source region and
The drain region is both formed in the well region.
8. transistor as described in any one of claims 1 to 7, which is characterized in that the first layer of the gate dielectric layer
Portion has first thickness and second thickness, and the second layer portion has the second thickness, and the first layer portion has described the
The part of two thickness is located at the intersection of the overlapping region and the channel region, and from the overlapping region and the ditch
The intersection in road region to the center of the channel region, the first layer portion is reduced to first thickness by the second thickness
Degree.
9. a kind of semiconductor devices, which is characterized in that including transistor as described in claim 1.
10. semiconductor devices as claimed in claim 9, which is characterized in that the semiconductor devices is memory, and utilizes institute
State the memory transistor that transistor constitutes the memory.
11. semiconductor devices as claimed in claim 10, which is characterized in that the memory has at least one active area,
The memory transistor is formed in the active area.
12. semiconductor devices as claimed in claim 11, which is characterized in that shape in an active area of the memory
At there are two the memory transistors, and the source region of two memory transistors shares.
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|---|---|---|---|
| CN201820325840.9U CN208225884U (en) | 2018-03-09 | 2018-03-09 | Transistor and semiconductor devices |
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| CN201820325840.9U CN208225884U (en) | 2018-03-09 | 2018-03-09 | Transistor and semiconductor devices |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108511518A (en) * | 2018-03-09 | 2018-09-07 | 睿力集成电路有限公司 | Transistor and forming method thereof, semiconductor devices |
| CN113078113A (en) * | 2020-01-03 | 2021-07-06 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
| WO2022179062A1 (en) * | 2021-02-23 | 2022-09-01 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
-
2018
- 2018-03-09 CN CN201820325840.9U patent/CN208225884U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108511518A (en) * | 2018-03-09 | 2018-09-07 | 睿力集成电路有限公司 | Transistor and forming method thereof, semiconductor devices |
| CN108511518B (en) * | 2018-03-09 | 2024-02-06 | 长鑫存储技术有限公司 | Transistor, forming method thereof and semiconductor device |
| CN113078113A (en) * | 2020-01-03 | 2021-07-06 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
| CN113078113B (en) * | 2020-01-03 | 2023-01-31 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
| WO2022179062A1 (en) * | 2021-02-23 | 2022-09-01 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
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