CN209822641U - Semiconductor device with a plurality of transistors - Google Patents
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- CN209822641U CN209822641U CN201920897831.1U CN201920897831U CN209822641U CN 209822641 U CN209822641 U CN 209822641U CN 201920897831 U CN201920897831 U CN 201920897831U CN 209822641 U CN209822641 U CN 209822641U
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- 239000000758 substrate Substances 0.000 claims description 16
- 239000002019 doping agent Substances 0.000 claims description 8
- 230000003247 decreasing effect Effects 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 description 15
- 238000000137 annealing Methods 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 8
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- 239000011810 insulating material Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
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- 238000002347 injection Methods 0.000 description 3
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- 238000005468 ion implantation Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
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- 238000005516 engineering process Methods 0.000 description 2
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- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
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- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- -1 germanium ions Chemical class 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Abstract
The utility model provides a semiconductor device, the active area of which comprises a well layer and a doping layer which are sequentially stacked, and a grid groove which is arranged on the doping layer and contains a grid insulating layer and a grid electrode; the doping layer comprises a plurality of first doping regions and at least one second doping region, and the second doping region is a heavily doped region; the grid groove is positioned between two adjacent first doping regions, and the second doping region is positioned on one side of at least one first doping region close to the grid groove. The second doped region of the semiconductor device has smaller resistance, improves the conduction current between the grid electrode and the source electrode, increases the switching characteristic of the device, and can also reduce GIDL (gate induced leakage) when the device is closed.
Description
Technical Field
The utility model relates to the field of semiconductor technology, particularly, relate to a semiconductor device.
Background
At present, MOSFETs (metal-oxide semiconductor field effect transistors) are the most commonly used devices in semiconductor manufacturing processes. For example, in modern memory technology architecture, the DRAM minimum memory cell consists of one MOSFET and one storage capacitor, as shown in fig. 1.
In order to achieve the maximum integration of a conventional memory cell, a trench MOSFET is generally used when a MOSFET is used as a memory cell, as shown in fig. 2. In order to prevent excessive GIDL (gate induced drain leakage) leakage in the off state of the device, the trench MOSFET is often designed to have a large resistance in the contact region with the storage capacitor or the bit line, but the large resistance means that the current of the device is small in the on state, and the switching characteristics are not good.
It should be noted that the information of the present invention in the above background section is only for enhancing the understanding of the background of the present invention, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a semiconductor device solves the problem of current semiconductor device conduction current undersize.
According to an aspect of the present invention, there is provided a semiconductor device, including a substrate, and an active region and an isolation region divided on the substrate, the active region including:
a well layer provided on the substrate,
the doping layer is arranged on the well layer and comprises a plurality of first doping regions and at least one second doping region, the doping ions of the first doping regions and the second doping regions are both N doping ions or P doping ions, and the second doping regions are heavily doped regions;
the gate trench is formed in the doping layer and extends to a part of the well layer along the thickness direction of the semiconductor device; the gate trench is positioned between two adjacent first doping regions, and the second doping region is positioned on one side of at least one first doping region close to the gate trench;
the grid insulating layer is arranged in the grid groove;
and the gate electrode is arranged at the bottom in the gate groove and is positioned in the gate insulating layer.
In an exemplary embodiment of the present invention, the well layer is a P-well layer, and the doping ions of the first doping region and the second doping region are N-doping ions.
In an exemplary embodiment of the present invention, a concentration of the dopant ions in the first doped region gradually decreases toward the well layer.
In an exemplary embodiment of the present invention, in the thickness direction of the semiconductor device, a bottom edge of the second doped region is not lower than a top of the gate electrode.
In an exemplary embodiment of the present invention, a bottom edge of the first doped region is not higher than a top of the gate electrode in the thickness direction of the semiconductor device.
In an exemplary embodiment of the present invention, the thickness of the second doped region in a direction perpendicular to the sidewall of the gate trench is 3 to 5 nm.
In an exemplary embodiment of the present invention, the active region further includes an oxide layer covering a surface of the doping layer away from the well layer.
In an exemplary embodiment of the present invention, the isolation region includes an isolation groove, and the isolation groove is filled with an insulating medium.
The utility model discloses a semiconductor device sets up the second doping district of heavy doping near grid slot position in the doping district, because the doping volume is great, this regional resistance is less, and when the device was opened, the second doping district can be flowed through to the electric current, consequently can improve the conduction current between grid and the source electrode to effectively increase the switching characteristic of device. On the other hand, the doped region except the second doped region is the first doped region, and the contact with the storage capacitor and the bit line is mainly the first doped region, so that the overall doping amount of the first doped region can be controlled to be lower, the overall resistance of the source region or the drain region is enabled to be larger as much as possible, and GIDL leakage when the device is closed can be reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
FIG. 1 is a schematic diagram of a DRAM memory cell;
FIG. 2 is a schematic cross-sectional view of a conventional MOSFET;
fig. 3 is a schematic cross-sectional view of a MOSFET of the present invention;
FIG. 4 is a flow chart of the MOSFET manufacturing method of the present invention;
FIG. 5 is a schematic diagram of a prepared word line;
FIG. 6 is a schematic diagram of preparing a dielectric layer;
FIG. 7 is a schematic view of implanting dopant ions into a sidewall of a gate trench;
FIG. 8 is a schematic view of a sidewall of a gate trench forming a second doped region;
FIG. 9 is a schematic view of implanting dopant ions into another sidewall of the gate trench;
FIG. 10 is a schematic view of a second doped region formed on the other sidewall of the gate trench;
fig. 11 is a schematic view of the completed gate insulating layer.
In the figure: 1. a substrate; 2. a P well layer; 3. an N doping layer; 4. a gate electrode; 5. an oxide layer; 6. an isolation trench; 7. a gate insulating layer; 8. a dielectric layer; 31. a first doped region; 32. a second doped region; 71. growing a gate insulating oxide layer; 72. and evaporating a gate insulating oxide layer.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
In the related art, as shown in fig. 2, in the N-doped trench MOSFET, a P-well layer 2 is provided on a substrate 1 in an active region, an N-doped layer 3 is provided on the P-well layer 2, and the N-doped layer 3 is separated by a gate trench, and when a minimum memory cell is fabricated, one side of the minimum memory cell is in contact with a storage capacitor, the other side of the minimum memory cell is in contact with a bit line, both sides of the minimum memory cell are respectively used as a source region and a drain region, and a gate electrode 4 fabricated in the gate. When the device is started, current flows from the source region to the drain region through the surface of the N-type doped layer 3, and the resistance of the source region and the drain region needs to be as small as possible to ensure larger conduction current. When the device is closed, because an overlapping region exists between the gate electrode and the source and drain electrodes during manufacturing, a certain GIDL leakage occurs below the overlapping region, so that the insulating effect cannot be achieved, and the source region and the drain region need to have larger resistance as much as possible to reduce the GIDL leakage. Therefore, the requirements for the source region and the drain region resistance for turning on and off the device are opposite, which brings great manufacturing difficulty.
The utility model discloses provide a MOSFET semiconductor device in the embodiment, can be N doping ditch slot type MOSFET, also can be P doping ditch slot type MOSFET.
As shown in fig. 3, taking an N-doped trench MOSFET as an example, the semiconductor device includes a substrate, on which an active region and an isolation region are divided, wherein a P-well layer 2 is disposed on a substrate 1 in the active region, an N-doped layer 3 is disposed on the P-well layer 2, the N-doped layer 3 is provided with a gate trench, the gate trench extends to a portion of the well layer along a thickness direction of the semiconductor device, the N-doped layer 3 is divided into a left region and a right region, each of the left region and the right region has a first doped region 31, each of the left region and the right region has a second doped region 32, doped ions of the first doped region 31 and the second doped region 32 are both N-doped ions, and the second doped region 32 is a heavily doped region; the second doped regions 32 are located at a side of the corresponding first doped region 31 near the gate trench. A gate insulating layer 7 is arranged in the gate trench, and a gate electrode 4 is arranged at the bottom in the gate trench and is positioned in the gate insulating layer 7.
The first doped region 31 and the corresponding second doped region 32 on the left and right sides of the gate trench of the present embodiment together form a source region and a drain region, and the second doped region 32 is located on one side of the source region or the drain region close to the gate trench, i.e. on the surface of the source region or the drain region. In this structure, the first doped region 31 is mainly in contact with the storage capacitor and the bit line. The second doped region 32 is a heavily doped region, which is a division of the semiconductor field with respect to doping concentration, and is usually greater than 1 × e15cm-2In this embodiment, the doping concentration of this region is also greater than the doping concentration of the first doping region 31.
When the device is turned on, current flows along the surface of the source region or the drain region, and therefore flows through the second doped region 32, and since the second doped region 32 is a heavily doped region and the doping amount is large, the resistance (Rcc 'and Rbl' in the figure) of the region is small, so that the on-state current is increased, and the switching characteristic of the device is effectively improved. In addition, because the contact with the storage capacitor and the bit line is mainly the first doping area, the whole doping amount of the first doping area can be controlled to be lower, so that the whole resistance of the source electrode area or the drain electrode area is enabled to be larger as much as possible, and the GIDL leakage is reduced.
The semiconductor device according to the embodiment of the present invention will be described in detail below:
referring to fig. 3, the well layer of the MOSFET of this embodiment is a P-well layer 2, the doping layer on the P-well layer 2 includes two first doping regions 31 respectively located at two sides of the gate trench, and one side of each first doping region 31 close to the gate trench is provided with a second doping region 32, so that the on-state currents of the source region and the drain region are both increased. The doping ions of the first doping region 31 and the second doping region 32 are both N-doping ions. N-doped ions refer to ions that are doped electronically and may include at least one of phosphorus, arsenic, and antimony. The doping ion species of the first doping region 31 and the second doping region 32 may be the same or different.
In the present embodiment, the content of the N-doped ions in the second doped region 32 is not less than 1 × e15cm-2The content can enable the source electrode area or the drain electrode area to obtain smaller surface resistance, and the conducting current is obviously increased, so that the switching characteristic of the MOSFET device is greatly improved.
In the thickness direction of the MOSFET device, the bottom edge of the second doped region 32 is not lower than the top of the gate electrode 4, thereby preventing the second doped region 32 and the gate electrode 4 from forming an overlapping region to avoid an additional GIDL increase due to heavy doping. In the direction perpendicular to the side wall of the gate trench, the thickness of the second doped region 32 is 3-5 nm, which can satisfy the passing of a large amount of current, and has a small influence on the overall resistance of the whole source region or the whole drain region. Meanwhile, the bottom edge of the first doped region is not higher than the top of the gate electrode.
In this embodiment, the N-doped ion concentration in the first doped region 31 gradually decreases toward the P-well layer 2, so that the N-doped ion concentration on the upper surface of the first doped region 31 is higher (for example, it may be heavily doped) and has a lower resistance, so that the on-state current is higher, and the N-doped ion concentration in the direction toward the P-well layer 2 is lower (for example, it may be lightly doped) and has a higher resistance, so that the GIDL leakage when the device is turned off can be reduced. The N-doped ions adopting the gradient distribution can further ensure larger conduction current on the basis of improving GIDL electric leakage. In other embodiments, the N-doped ion distribution in the first doped region 31 may also be in other forms, such as a uniform distribution.
In other embodiments of the present invention, there may be only one second doping region 32, which is disposed on one side of the gate trench and can also increase the on-current to a certain extent. The detailed structure is not described herein.
In this embodiment, the active region further includes a protection layer covering the doped layer and away from the surface of the well layer, and the protection layer may be an oxide layer 5 for protecting the active region. The isolation region comprises an isolation trench 6, for example, a shallow trench may be used for isolation, and the isolation trench 6 is filled with an insulating medium.
Referring to fig. 4, the method for manufacturing the N-doped trench MOSFET specifically includes the following steps:
step S100, providing a silicon substrate 1, sequentially forming a P well layer 2 and an N doping layer 3 which are arranged in a stacked mode on the substrate 1, and forming an active region and an isolation region;
step S200, a grid groove is formed in the doping layer of the active region, and the grid groove extends to a part of the well layer along the thickness direction of the semiconductor device; covering a gate insulating material on the inner wall of the bottom of the gate groove, and forming a gate electrode 4 at the bottom of an area surrounded by the gate insulating material;
step S300, implanting dopant ions into at least one sidewall of both sides of the gate trench and annealing, wherein the dopant ions will diffuse into the silicon through the gate insulating material to form the second doped region 32. The second doped region 32 is a heavily doped region; the doping ions of the first doping region 31 and the second doping region 32 are both N-doping ions or P-doping ions;
step S400, covering a gate insulating material on the top of the gate electrode in the gate trench, and completing the preparation of the gate insulating layer 7 to form the semiconductor device.
The second doped region 32 of the method is performed on the basis of the formed word line, i.e. steps S100 and S200 described above. Referring to fig. 5, the process may specifically be: firstly, a P well layer 2, an N doping layer 3, a silicon wafer oxidation layer 5 and an isolation groove 6 are prepared on a substrate 1, and an isolation region (STI) and an active region (AA) are divided. Then, a gate trench is opened on the N doping layer 3 of the active region, a grown gate insulating oxide layer 71 is formed on the inner wall of the gate trench, a gate electrode 4 is formed in the region surrounded by the gate insulating oxide layer, and the height of the gate electrode 4 is ideally higher than the surface of the P-well layer 2.
Step S300 of the method is a step of preparing the second doped region 32, which is formed by doping ions again in the formed N-doped layer 3. In this step, the second doped region 32 is formed by a combination of ion implantation and annealing. Ion implantation refers to the implantation of dopant ions into a semiconductor in the form of ion beams, and annealing allows the ions to diffuse from the surface into the body, with a gradual downward trend.
The N dopant ions implanted into the second doping region 32 may include at least one of phosphorus, arsenic and antimony, and the implantation amount is not less than 1 × e15cm-2. In other preparation methods, the N-doped ions can also be other ions and are implantedThe amount can also be other values, and can be specifically adjusted according to the requirement of the resistance.
In this step, before forming the second doped region 32, diffusion-inhibiting ions capable of inhibiting diffusion of the doping ions of the second doped region 32 are co-implanted into the sidewall of the gate trench in which the second doped region 32 is to be formed, and then N-doping ions are implanted, so that it is possible to prevent the second doped region 32 from being too thick due to too fast diffusion of the ions in the high-temperature diffusion process, and thus the resistance of the entire source region or drain region is reduced, which may further increase GIDL. It is also prevented that the diffusion of heavily doped ions into the portion of the first doped region 31 below the top surface of the gate electrode 4, i.e., the bottom edge of the second doped region 32 is lower than the top of the gate electrode 4, due to the too fast diffusion during the ion annealing process, will also cause an additional GIDL increase. The mechanism for inhibiting diffusion ions from reducing diffusion is mainly to utilize these particles to bind interstitial atoms in the silicon wafer, and interstitial atoms are the main factor for causing diffusion of N-doped ions. The diffusion rate of the N-doped ions in the second doped region 32 is reduced, so that the range of the implanted N-doped ions can be controlled more easily in the manufacturing process, shallower junctions can be formed, and smaller semiconductor sizes can be manufactured. The diffusion-inhibiting ions may include at least one of fluorine, carbon, and germanium ions, and are implanted in an amount of 1 × e15～9×e15cm-2。
Since the N-doped ions and the diffusion-inhibiting ions of the second doped region 32 need to be implanted from the sidewall of the gate trench, an inclined ion implantation manner can be adopted during the implantation, so that the ions can be uniformly implanted into the doped region. Usually, an inclined substrate is selected, the inclination angle is determined according to the width and the depth of the gate trench, the bottom injection cannot be performed due to the excessively large inclination angle, the region to be injected cannot be performed due to the excessively small inclination angle, and the injection effect is best when the inclination angle is about 80 degrees.
And when annealing is carried out after all the ions are implanted, the annealing temperature is 950-1000 ℃, and the annealing time is 8-12 s. By adopting the annealing process, the thickness of the second doped region 32 in the direction vertical to the side wall of the gate trench can be controlled within 3-5 nm, and the requirement of conducting current in a source region or a drain region is met.
In this step, in order to further prevent N-doped ions from diffusing below the top surface of the gate electrode 4, before the second doped region 32 is formed, a dielectric layer 8 covering the gate electrode 4 may be formed on the gate electrode 4, and the presence of the dielectric layer 8 prevents ions from being injected into an overlapping region between the gate electrode 4 and the source/drain during ion injection, so that the ion concentration is not increased in the overlapping region, and the GIDL effect is not increased. The dielectric layer 8 may be an insulating material such as silicon oxide or silicon nitride, and may be the same material as the gate insulating layer 7 or a different material from the gate insulating layer 7. Because the ion diffusion distance is about 10-15 nm, the thickness of the dielectric layer 8 is also 10-15 nm, and N doped ions can be prevented from diffusing to the part of the first doped region below the top surface of the gate electrode 4.
Referring to fig. 6 to 10, the specific preparation process of step S300 may be:
step S310, a dielectric layer 8 with the thickness of about 10-15 nm is deposited on the formed gate electrode 4.
Step S320, inclining the substrate, implanting diffusion-inhibiting ions at the position where the gate insulating oxide layer 71 is grown on the left sidewall of the gate trench, and implanting doping ions at the same position.
Step S330, inclining the substrate, injecting diffusion-inhibiting ions at the position where the gate insulating oxide layer 71 grows on the right side wall of the gate trench, and then injecting doping ions at the same position.
Step S340, annealing to diffuse the doping ions to form the second doping region 32.
The second doped region 32 is formed through the step S300, and the portion of the N-doped layer 3 where the second doped region 32 is removed is the first doped region 31, as shown in the figure, the second doped region 32 is located on one side of the first doped region 31 close to the gate trench.
Referring to fig. 11, step 400 specifically includes: and forming an evaporation gate insulating oxide layer 72 above the dielectric layer 8 in the gate trench to complete the preparation of the gate insulating layer 7, so that the whole gate electrode 4 is insulated from the N doping layer 3, and finally the preparation of the semiconductor device is completed.
In the above manufacturing process, two gate trenches are formed in the active region, and a first doped region 31 and a second doped region 32 are respectively disposed on the left and right sides of each gate trench. In other manufacturing methods, the second doped region 32 may be disposed only on one side of one gate trench, and may also reduce the resistance of the side to increase the on-current. The detailed structure and preparation process are not described herein. In addition, the preparation method of the N-doped trench MOSFET is given above, and similar structure and preparation method can be adopted for the P-doped trench MOSFET, which is not listed here.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
Claims (8)
1. A semiconductor device comprising a substrate, and an active region and an isolation region divided on the substrate, wherein the active region comprises:
a well layer provided on the substrate,
the doping layer is arranged on the well layer and comprises a plurality of first doping regions and at least one second doping region, the doping ions of the first doping regions and the second doping regions are both N doping ions or P doping ions, and the second doping regions are heavily doped regions;
the gate trench is formed in the doping layer and extends to a part of the well layer along the thickness direction of the semiconductor device; the gate trench is positioned between two adjacent first doping regions, and the second doping region is positioned on one side of at least one first doping region close to the gate trench;
the grid insulating layer is arranged in the grid groove;
and the gate electrode is arranged at the bottom in the gate groove and is positioned in the gate insulating layer.
2. The semiconductor device according to claim 1, wherein the well layer is a P-well layer, and the doping ions of the first and second doping regions are both N-doping ions.
3. The semiconductor device according to claim 1, wherein a concentration of dopant ions in the first doped region is gradually decreased toward the well layer.
4. The semiconductor device according to claim 1, wherein a bottom edge of the second doped region is not lower than a top of the gate electrode in a thickness direction of the semiconductor device.
5. The semiconductor device according to claim 4, wherein a bottom edge of the first doped region is not higher than a top of the gate electrode in a thickness direction of the semiconductor device.
6. The semiconductor device according to claim 1, wherein a thickness of the second doped region in a direction perpendicular to the gate trench sidewall is 3 to 5 nm.
7. The semiconductor device of claim 1, wherein the active region further comprises:
and the oxide layer covers the surface of the doping layer far away from the well layer.
8. The semiconductor device of claim 1, wherein the isolation region comprises an isolation trench filled with an insulating dielectric.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112086454A (en) * | 2019-06-14 | 2020-12-15 | 长鑫存储技术有限公司 | Semiconductor device and method for manufacturing the same |
| CN113497124A (en) * | 2020-04-07 | 2021-10-12 | 长鑫存储技术有限公司 | Semiconductor device and method for manufacturing the same |
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2019
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112086454A (en) * | 2019-06-14 | 2020-12-15 | 长鑫存储技术有限公司 | Semiconductor device and method for manufacturing the same |
| CN113497124A (en) * | 2020-04-07 | 2021-10-12 | 长鑫存储技术有限公司 | Semiconductor device and method for manufacturing the same |
| CN113497124B (en) * | 2020-04-07 | 2023-08-11 | 长鑫存储技术有限公司 | Semiconductor device and method for manufacturing the same |
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