CN113223998A - 具有金属间介电图案的半导体元件及其制作方法 - Google Patents
具有金属间介电图案的半导体元件及其制作方法 Download PDFInfo
- Publication number
- CN113223998A CN113223998A CN202010079602.6A CN202010079602A CN113223998A CN 113223998 A CN113223998 A CN 113223998A CN 202010079602 A CN202010079602 A CN 202010079602A CN 113223998 A CN113223998 A CN 113223998A
- Authority
- CN
- China
- Prior art keywords
- inter
- metal
- metal dielectric
- layer
- contact hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 166
- 239000002184 metal Substances 0.000 claims abstract description 165
- 239000004020 conductor Substances 0.000 claims abstract description 45
- 238000000034 method Methods 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000000059 patterning Methods 0.000 claims abstract description 9
- 239000010949 copper Substances 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- JPNWDVUTVSTKMV-UHFFFAOYSA-N cobalt tungsten Chemical compound [Co].[W] JPNWDVUTVSTKMV-UHFFFAOYSA-N 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 229910000838 Al alloy Inorganic materials 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 80
- 239000000463 material Substances 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 239000007769 metal material Substances 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000012937 correction Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- -1 silicon carbide nitride Chemical class 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明公开一种具有金属间介电图案的半导体元件及其制作方法,其中该制作半导体元件的方法为,首先形成第一金属间介电层于基底上,然后图案化第一金属间介电层以形成多个金属间介电图案于基底上、一凹槽环绕金属间介电图案以及一第二金属间介电图案环绕该凹槽,形成一金属层于凹槽内并环绕第一金属间介电图案,形成一第二金属间介电层于第一金属间介电图案、金属层以及第二金属间介电图案上,再形成多个接触洞导体于第二金属间介电层内,其中接触洞导体不重叠第一金属间介电图案。
Description
技术领域
本发明涉及一种制作半导体元件的方法,尤其是涉及一种利用图案化制作工艺形成金属间介电图案以及图案化金属层的方法。
背景技术
随着半导体元件尺寸的逐渐缩小,内连线结构的线宽的逐渐变窄也使得传输信号的线阻值(line resistance,R)变大。此外,导线间的间距缩小也使得寄生电容(parasiticcapacitance,C)变大。因此,使得信号因RC延迟的状况增加,导致芯片运算速度减慢,降低了芯片的效能。
寄生电容(C)与介电层的介电常数或k值(k-value)呈线性相关。低介电常数介电材料可降低芯片上整个内连线结构的电容值、降低信号的RC延迟以及增进芯片效能。降低整体的电容同时降低了耗电量。对于超大型集成电路(ULSI)的设计而言,采用低介电常数材料以及低阻值的金属材料,可以使得整个内连线结构达到最佳效能。因此,现有技术通常试图通过将金属间的间隙以低介电常数材料填满以降低RC延迟。
然而在一般半导体元件的制作工艺中,较下层的金属内连线与低介电常数所构成的金属间介电层之间时常因应力不同,例如较下层的金属内连线相对于基底易产生拉伸应力(tensile stress)而金属间介电层则产生压缩应力(compressive stress),而此应力间的不平衡最终即于接触洞导体的密集区(dense region)产生裂痕并影响元件运作。因此需要一种内连线结构以及其制造方法来克服上述问题。
发明内容
本发明一实施例揭露一种制作半导体元件的方法。首先形成第一金属间介电层于基底上,然后图案化第一金属间介电层以形成多个金属间介电图案于基底上、一凹槽环绕金属间介电图案以及一第二金属间介电图案环绕该凹槽,形成一金属层于凹槽内并环绕第一金属间介电图案,形成一第二金属间介电层于第一金属间介电图案、金属层以及第二金属间介电图案上,再形成多个接触洞导体于第二金属间介电层内,其中接触洞导体不重叠第一金属间介电图案。
本发明另一实施例揭露一种半导体元件,其主要包含一图案化金属层设于基底上、多个接触洞导体设于图案化金属层上以及多个第一金属间介电图案镶嵌于图案化金属层内,其中第一金属间介电图案于一上视角度下设于接触洞导体之间且不重叠接触洞导体。
本发明又一实施例揭露一种半导体元件,其主要包含一图案化金属层设于基底上、多个第一金属间介电图案镶嵌于图案化金属层内以及多个接触洞导体设于图案化金属层上,其中接触洞导体不重叠第一金属间介电图案。
附图说明
图1至图5为本发明一实施例制作半导体元件的方法示意图;
图6为本发明一实施例的一半导体元件的结构示意图;
图7为本发明一实施例的一半导体元件的结构示意图。
主要元件符号说明
12 基底 14 金属间介电层
16 第一金属间介电图案 18 凹槽
20 第二金属间介电图案 22 金属层
24 停止层 26 金属间介电层
28 接触洞导体 30 沟槽导体
32 金属内连线
具体实施方式
请参照图1,图1左侧为本发明一实施例制作半导体元件的上视图,而图1右侧则为左侧沿着切线AA’的剖面示意图。如图1所示,首先提供一基底12,例如一由半导体材料所构成的基底12,其中半导体材料可选自由硅、锗、硅锗复合物、硅碳化物(silicon carbide)、砷化镓(galliumarsenide)等所构成的群组。基底12上可包含例如金属氧化物半导体(metal-oxide semiconductor,MOS)晶体管等主动(有源)元件、被动(无源)元件、导电层以及例如层间介电层(interlayer dielectric,ILD)(图未示)等介电层覆盖于其上。更具体而言,基底12上可包含平面型或非平面型(如鳍状结构晶体管)等MOS晶体管元件,其中MOS晶体管可包含金属栅极以及源极/漏极区域、间隙壁、外延层、接触洞蚀刻停止层等晶体管元件,层间介电层较可设于基底12上并覆盖MOS晶体管,且层间介电层可具有多个接触插塞电连接MOS晶体管的栅极以及/或源极/漏极区域。由于平面型或非平面型晶体管与层间介电层等相关制作工艺均为本领域所熟知技术,在此不另加赘述。
然后于层间介电层上形成一金属间介电层14,其中金属间介电层14可包含但不局限于氮掺杂碳化物层(nitrogen doped carbide,NDC)或氮碳化硅(silicon carbonnitride,SiCN)。需注意的是,由于金属间介电层14在此阶段未被图案化,因此从上视角度来看仍呈现一整面型态并完全覆盖于下层的层间介电层以及/或基底12表面。
请参照图2,图2左侧为本发明一实施例接续图1制作半导体元件的上视图,而图2右侧则为左侧沿着切线AA’的剖面示意图。如图2所示,然后进行一图案转移制作工艺图案化金属间介电层14以形成多个第一金属间介电图案16、一凹槽18以及一第二金属间介电图案20。更具体而言,本阶段图案化金属间介电层14的步骤可先形成一图案化掩模(图未示),例如一图案化光致抗蚀剂于金属间介电层14上,然后利用图案化掩模为掩模以蚀刻去除部分金属间介电层14,由此将层间介电层14图案化形成多个第一金属间介电图案16于基底12或层间介电层上、一凹槽18环绕第一金属间介电层图案16以及一第二金属间介电图案20环绕凹槽18。从左侧的上视剖面来看,本阶段所形成的每个第一金属间介电图案16较佳包含相同尺寸、各第一金属间介电图案16较佳包含矩形如正方形或长方形且第一金属间介电图案16较佳均匀分布或以阵列方式平均分布于凹槽18内。
请参照图3,图3左侧为本发明一实施例接续图2制作半导体元件的上视图,而图3右侧则为左侧沿着切线AA’的剖面示意图。如图3所示,接着形成一金属层22于凹槽18内并填满凹槽18,其中所形成的金属层由于具有凹槽的轮廓因此较佳环绕并包围所有第一金属间介电图案16并可称之为图案化金属层22,且在此阶段包围第一金属间介电层16的整块图案化金属层22均为相等电位。在本实施例中,金属层22较佳包含铜,但依据本发明其他实施例金属层22又可包含但不局限于例如钨(W)、铝(Al)、钛铝合金(TiAl)、钴钨磷化物(cobalttungsten phosphide,CoWP)或其组合。
请参照图4至图6,图4为本发明一实施例接续图3制作半导体元件的上视图,图5左侧为图4沿着切线AA’的剖面示意图,图5右侧为图4沿着切线BB’的剖面示意图,而图6则为本发明一实施例制作半导体元件的上视图。如图4至图5所示,接着先依序形成一停止层24以及一金属间介电层26并覆盖金属层22、第一金属间介电图案16以及第二金属间介电图案20,然后利用单镶嵌或双镶嵌制作工艺进行一次或多次微影暨蚀刻制作工艺去除部分金属间介电层26及部分停止层24以形成多个接触洞(图未示)暴露出下面的金属层22,其中接触洞较佳不重叠任何第一金属间介电图案16与第二金属间介电图案20。
然后于接触洞中填入所需的金属或导电材料,例如包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等的阻障层材料以及选自钨(W)、铜(Cu)、铝(Al)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungsten phosphide,CoWP)等低电阻材料或其组合的金属层。接着进行一平坦化制作工艺,例如以化学机械研磨制作工艺去除部分金属材料以形成多个由接触洞导体(via conductor)28与沟槽导体(trench conductor)30所构成的接触插塞或金属内连线32于接触洞内电连接下层的金属层22。由于单镶嵌或双镶嵌制作工艺乃本领域所熟知技术,在此不另加赘述。此外在本实例中金属内连线32较佳包含铜,金属间介电层26、第一金属间介电图案16以及第二金属间介电图案20可包含例如氧化硅、四乙氧基硅烷(tetraethyl orthosilicate,TEOS)、氮掺杂碳化物层(nitrogen doped carbide,NDC)或氮碳化硅(silicon carbon nitride,SiCN)而停止层24则包含氮化硅,但不局限于此。
需注意的是,为了凸显接触洞导体28与下层金属层22之间的排列,图4的上视图仅揭露接触洞导体28的位置但未绘示出沟槽导体30。此外除了设于第一层的图案化金属层22可利用前述图案化制作工艺将金属层22镶嵌于被图案化的第一金属间介电图案16及第二金属间介电图案20中,依据本发明其他实施例又可将图案化第一层金属层22的制作工艺应用至第二层金属内连线如沟槽导体30甚至更上层金属内连线结构的制作,例如第二层金属内连线经由前述图案化制作工艺所形成的图案,包括金属层的图案以及/或金属间介电图案等均可选择与第一层金属内连线的图案相同或不同,这些变化型均属本发明所涵盖的范围。
请继续参照图4至图6,图4至图6又揭露本发明一实施例的一半导体元件的结构示意图。如图4及图6所示,半导体元件主要包含一图案化金属层22设于基底12上、多个接触洞导体28设于图案化金属层22上、多个第一金属间介电图案16镶嵌于图案化金属层22内以及一第二金属间介电图案20环绕图案化金属层22。
在本实施例中,接触洞导体28是在一上视角度下沿着一第一方向(例如X方向)排列于图案化金属层22上,第一金属间介电图案16是在一上视角度下沿着同样第一方向排列于接触洞导体28之间且不重叠接触洞导体28,其中第一金属间介电图案16较佳平均分布于图案化金属层22上而非聚集(cluster)于接触洞导体28周围。由于图案化金属层22与第一金属间介电图案16较佳在同一层,因此由剖面来看图案化金属层22顶部较佳切齐第一金属间介电图案16顶部。另外,依据本发明一实施例,若第一层金属内连线结构中的第一金属间介电图案16是沿着一第一方向如X方向排列,第二层金属内连线结构中的金属间介电图案可与第一层的与第一层的金属间介电图案以相同方式排列或不同方式排列,例如可比照第一金属间介电图案16同样沿着X方向排列或可选择沿着Y方向排列,这些变化型均属本发明所涵盖的范围。
从形状来看图案化金属层22于上视角度下包含一四边形,各接触洞导体28于上视角度下包含一正方形且各第一金属间介电图案16于上视角度下包含一正方形,其中本实施例中各第一金属间介电图案16的面积虽较佳大于各接触洞导体28面积,但不局限于此,依据本发明其他实施例各第一金属间介电图案16的面积又可选择等于或小于各接触洞导体28面积,这些变化型均属本发明所涵盖的范围。
另外如图6所示,相较于前述实施例于图2图案化金属间介电层14的时候形成正方形的第一金属间介电图案16,本发明另一实施例又可调整光掩模所覆盖的区域以形成约略长方形的第一金属间介电图案16于凹槽内。之后再比照图3至图5的制作工艺依序形成图案化金属层22、停止层24、金属间介电层26以及金属内连线32等元件,此变化型也属本发明所涵盖的范围。
请继续参照图7,图7揭露本发明一实施例的一半导体元件的结构示意图。如图7所示,相较于前述实施例于图4所揭露半导体元件的上视图中第一金属间介电图案16及接触洞导体28均呈现正方形,依据本发明另一实施例又可于形成上述元件时调整光掩模的图案或经光学近接修正(optical proximity correction,OPC)等校正步骤后使金属间介电图案16及接触洞导体28均呈现约略圆形,此变化型也属本发明所涵盖的范围。
综上所述,本发明较佳先形成一第一金属间介电层于基底上,然后图案化该第一金属间介电层以形成多个第一金属间介电图案、一凹槽环绕第一金属间介电图案以及一第二金属间介电图案环绕凹槽。接着填入金属层于凹槽内,再形成第二金属间介电层以及多个接触洞导体于第二金属间介电层内并电连接下方的金属层。依据本发明的优选实施例,利用上述设计于金属层内镶嵌多个以阵列方式或平均分布的金属间介电图案可有效平衡下层金属内连线结构与上层金属内连线结构之间所产生的应力,而不单单只消除局部或单颗接触洞导体周围所产生的应力,由此改善整个金属内连线结构中除了密集区以外的所有区域容易因应力分布不均而产生裂痕的问题。
以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,都应属本发明的涵盖范围。
Claims (20)
1.一种制作半导体元件的方法,其特征在于,包含:
形成第一金属间介电层于基底上;
图案化该第一金属间介电层以形成多个第一金属间介电图案于该基底上、一凹槽环绕该多个第一金属间介电图案以及第二金属间介电图案环绕该凹槽;
形成金属层于该凹槽内并环绕该多个第一金属间介电图案;
形成第二金属间介电层于该多个第一金属间介电图案、该金属层以及该第二金属间介电图案上;以及
形成多个接触洞导体于该第二金属间介电层内,其中该多个接触洞导体不重叠该多个第一金属间介电图案。
2.如权利要求1所述的方法,其中该金属层顶部切齐该多个第一金属间介电图案。
3.如权利要求1所述的方法,其中该金属层包含铜、铝、钨、钛铝合金或钴钨磷化物。
4.如权利要求1所述的方法,其中该多个接触洞导体是在上视角度下沿着第一方向排列于该金属层上。
5.如权利要求4所述的方法,其中该多个第一金属间介电图案在上视角度下沿着该第一方向排列于该多个接触洞导体之间。
6.如权利要求1所述的方法,其中该金属层于上视角度下包含四边形。
7.如权利要求1所述的方法,其中各该接触洞导体于上视角度下包含正方形或圆形。
8.如权利要求1所述的方法,其中各该第一金属间介电图案于上视角度下包含正方形或圆形。
9.如权利要求1所述的方法,其中各该第一金属间介电图案于上视角度下包含长方形。
10.一种半导体元件,其特征在于,包含:
图案化金属层,设于基底上;
多个接触洞导体,设于该图案化金属层上;以及
多个第一金属间介电图案,镶嵌于该图案化金属层内,其中该多个第一金属间介电图案于上视角度下设于该多个接触洞导体之间且不重叠该多个接触洞导体。
11.如权利要求10所述的半导体元件,其中该多个接触洞导体是在上视角度下沿着第一方向排列于该图案化金属层上。
12.如权利要求11所述的半导体元件,其中该多个第一金属间介电图案是在上视角度下沿着该第一方向排列于该多个接触洞导体之间。
13.如权利要求10所述的半导体元件,其中该图案化金属层于上视角度下包含四边形。
14.如权利要求10所述的半导体元件,其中各该接触洞导体于一上视角度下包含一正方形或一圆形。
15.如权利要求10所述的半导体元件,其中各该第一金属间介电图案于上视角度下包含正方形或圆形。
16.如权利要求10所述的半导体元件,其中各该第一金属间介电图案于上视角度下包含长方形。
17.如权利要求10所述的半导体元件,另包含第二金属间介电图案环绕该图案化金属层。
18.一种半导体元件,其特征在于,包含:
图案化金属层,设于基底上;
多个第一金属间介电图案,镶嵌于该图案化金属层内;以及
多个接触洞导体,设于该图案化金属层上,其中该多个接触洞导体不重叠该多个第一金属间介电图案。
19.如权利要求18所述的半导体元件,另包含:
第二金属间介电图案,环绕该图案化金属层;
第二金属间介电层,设于该多个第一金属间介电图案、该图案化金属层以及该第二金属间介电图案上;以及
该多个接触洞导体,设于该第二金属间介电层内。
20.如权利要求18所述的半导体元件,其中该图案化金属层顶部切齐该多个第一金属间介电图案顶部。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010079602.6A CN113223998B (zh) | 2020-02-04 | 2020-02-04 | 具有金属间介电图案的半导体元件的制作方法 |
CN202111318146.7A CN114188302B (zh) | 2020-02-04 | 2020-02-04 | 具有金属间介电图案的半导体元件及其制作方法 |
US16/843,903 US11201116B2 (en) | 2020-02-04 | 2020-04-09 | Semiconductor device having inter-metal dielectric patterns and method for fabricating the same |
US17/529,212 US11749601B2 (en) | 2020-02-04 | 2021-11-17 | Semiconductor device having inter-metal dielectric patterns and method for fabricating the same |
US18/224,592 US12094820B2 (en) | 2020-02-04 | 2023-07-21 | Semiconductor device having inter-metal dielectric patterns and method for fabricating the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010079602.6A CN113223998B (zh) | 2020-02-04 | 2020-02-04 | 具有金属间介电图案的半导体元件的制作方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202111318146.7A Division CN114188302B (zh) | 2020-02-04 | 2020-02-04 | 具有金属间介电图案的半导体元件及其制作方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN113223998A true CN113223998A (zh) | 2021-08-06 |
CN113223998B CN113223998B (zh) | 2022-10-04 |
Family
ID=77062741
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202010079602.6A Active CN113223998B (zh) | 2020-02-04 | 2020-02-04 | 具有金属间介电图案的半导体元件的制作方法 |
CN202111318146.7A Active CN114188302B (zh) | 2020-02-04 | 2020-02-04 | 具有金属间介电图案的半导体元件及其制作方法 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202111318146.7A Active CN114188302B (zh) | 2020-02-04 | 2020-02-04 | 具有金属间介电图案的半导体元件及其制作方法 |
Country Status (2)
Country | Link |
---|---|
US (3) | US11201116B2 (zh) |
CN (2) | CN113223998B (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11659771B2 (en) * | 2020-11-25 | 2023-05-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for integrating MRAM and logic devices |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20010061495A (ko) * | 1999-12-28 | 2001-07-07 | 박종섭 | 반도체 소자의 층간 절연막용 붕소화 실리콘 탄화막 및이를 이용한 금속 배선 형성 방법 |
CN1426107A (zh) * | 2001-12-11 | 2003-06-25 | 矽统科技股份有限公司 | 将盖层设置于内金属介电层上的内连线结构及其制作方法 |
CN1521827A (zh) * | 2003-01-30 | 2004-08-18 | 矽统科技股份有限公司 | 在镶嵌结构中形成阻障层的方法 |
CN1967845A (zh) * | 2005-11-15 | 2007-05-23 | 东部电子股份有限公司 | 半导体器件及其制造方法 |
US20070166988A1 (en) * | 2005-12-29 | 2007-07-19 | Dongbu Electronics Co., Ltd. | Aluminum metal line of a semiconductor device and method of fabricating the same |
CN110581215A (zh) * | 2018-06-07 | 2019-12-17 | 联华电子股份有限公司 | 形成磁阻式随机存取存储器单元的方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6613592B1 (en) | 2002-04-25 | 2003-09-02 | Taiwan Semiconductor Manufacturing Company | IMD oxide crack monitor pattern and design rule |
US7089522B2 (en) | 2003-06-11 | 2006-08-08 | Chartered Semiconductor Manufacturing, Ltd. | Device, design and method for a slot in a conductive area |
KR100590205B1 (ko) * | 2004-01-12 | 2006-06-15 | 삼성전자주식회사 | 반도체 장치의 배선 구조체 및 그 형성 방법 |
US8456009B2 (en) * | 2010-02-18 | 2013-06-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure having an air-gap region and a method of manufacturing the same |
US8790975B2 (en) * | 2011-03-04 | 2014-07-29 | Globalfoundries Inc. | Semiconductor device comprising a capacitor formed in the metallization system based on dummy metal features |
US8569129B2 (en) * | 2011-05-31 | 2013-10-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Device-manufacturing scheme for increasing the density of metal patterns in inter-layer dielectrics |
US9577023B2 (en) * | 2013-06-04 | 2017-02-21 | Globalfoundries Inc. | Metal wires of a stacked inductor |
US8890084B1 (en) | 2013-09-03 | 2014-11-18 | United Microelectronics Corp. | Method for analyzing circuit pattern |
US9508722B2 (en) * | 2013-11-22 | 2016-11-29 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor arrangment with capacitor |
US9230913B1 (en) * | 2014-08-12 | 2016-01-05 | Globalfoundries Inc. | Metallization layers configured for reduced parasitic capacitance |
CN106033741B (zh) * | 2015-03-20 | 2020-09-15 | 联华电子股份有限公司 | 金属内连线结构及其制作方法 |
TWI753993B (zh) * | 2017-01-20 | 2022-02-01 | 日商東京威力科創股份有限公司 | 內連線結構及其形成方法 |
US10784198B2 (en) * | 2017-03-20 | 2020-09-22 | Samsung Electronics Co., Ltd. | Power rail for standard cell block |
US11600519B2 (en) * | 2019-09-16 | 2023-03-07 | International Business Machines Corporation | Skip-via proximity interconnect |
-
2020
- 2020-02-04 CN CN202010079602.6A patent/CN113223998B/zh active Active
- 2020-02-04 CN CN202111318146.7A patent/CN114188302B/zh active Active
- 2020-04-09 US US16/843,903 patent/US11201116B2/en active Active
-
2021
- 2021-11-17 US US17/529,212 patent/US11749601B2/en active Active
-
2023
- 2023-07-21 US US18/224,592 patent/US12094820B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20010061495A (ko) * | 1999-12-28 | 2001-07-07 | 박종섭 | 반도체 소자의 층간 절연막용 붕소화 실리콘 탄화막 및이를 이용한 금속 배선 형성 방법 |
CN1426107A (zh) * | 2001-12-11 | 2003-06-25 | 矽统科技股份有限公司 | 将盖层设置于内金属介电层上的内连线结构及其制作方法 |
CN1521827A (zh) * | 2003-01-30 | 2004-08-18 | 矽统科技股份有限公司 | 在镶嵌结构中形成阻障层的方法 |
CN1967845A (zh) * | 2005-11-15 | 2007-05-23 | 东部电子股份有限公司 | 半导体器件及其制造方法 |
US20070166988A1 (en) * | 2005-12-29 | 2007-07-19 | Dongbu Electronics Co., Ltd. | Aluminum metal line of a semiconductor device and method of fabricating the same |
CN110581215A (zh) * | 2018-06-07 | 2019-12-17 | 联华电子股份有限公司 | 形成磁阻式随机存取存储器单元的方法 |
Also Published As
Publication number | Publication date |
---|---|
CN114188302A (zh) | 2022-03-15 |
US20230361034A1 (en) | 2023-11-09 |
US11749601B2 (en) | 2023-09-05 |
US20220077058A1 (en) | 2022-03-10 |
US12094820B2 (en) | 2024-09-17 |
US20210242129A1 (en) | 2021-08-05 |
CN114188302B (zh) | 2022-12-13 |
US11201116B2 (en) | 2021-12-14 |
CN113223998B (zh) | 2022-10-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10373905B2 (en) | Integrating metal-insulator-metal capacitors with air gap process flow | |
US7514354B2 (en) | Methods for forming damascene wiring structures having line and plug conductors formed from different materials | |
KR101278279B1 (ko) | 더미 비아를 제공함으로써 금속화 층의 접착력을증가시키는 기술 | |
US20160218038A1 (en) | Novel patterning approach for improved via landing profile | |
CN106033741B (zh) | 金属内连线结构及其制作方法 | |
US10811353B2 (en) | Sub-ground rule e-Fuse structure | |
KR20090004469A (ko) | 반도체 장치 | |
JP2006344965A (ja) | 配線構造の形成方法,配線構造およびデュアルダマシン構造 | |
US11437312B2 (en) | High performance metal insulator metal capacitor | |
CN109545735B (zh) | 金属内连线结构及其制作方法 | |
US12094820B2 (en) | Semiconductor device having inter-metal dielectric patterns and method for fabricating the same | |
US6638849B2 (en) | Method for manufacturing semiconductor devices having copper interconnect and low-K dielectric layer | |
CN112582398B (zh) | 半导体器件及其形成方法 | |
US20190304928A1 (en) | Advanced crack stop structure | |
US12074107B2 (en) | Structure and method of forming a semiconductor device with resistive elements | |
US6399471B1 (en) | Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application | |
KR100871551B1 (ko) | 반도체 소자 및 그 제조방법 | |
US9842810B1 (en) | Tiled-stress-alleviating pad structure | |
US20240096796A1 (en) | Integrated circuit device | |
TWI746851B (zh) | 金屬內連線結構及其製作方法 | |
US11942424B2 (en) | Via patterning for integrated circuits | |
US20240071929A1 (en) | Dielectric caps for power and signal line routing | |
US20230102662A1 (en) | Top via interconnects with line wiggling prevention | |
CN111293072A (zh) | 半导体元件及其制作方法 | |
CN116648133A (zh) | 半导体器件、金属-绝缘体-金属电容器结构及形成方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |