CN113221498A - Method for reducing metal area - Google Patents
Method for reducing metal area Download PDFInfo
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- CN113221498A CN113221498A CN202110459064.8A CN202110459064A CN113221498A CN 113221498 A CN113221498 A CN 113221498A CN 202110459064 A CN202110459064 A CN 202110459064A CN 113221498 A CN113221498 A CN 113221498A
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- 239000002184 metal Substances 0.000 title claims abstract description 193
- 238000000034 method Methods 0.000 title claims abstract description 41
- 230000010354 integration Effects 0.000 claims abstract description 8
- 230000002093 peripheral effect Effects 0.000 claims abstract description 7
- 230000011218 segmentation Effects 0.000 claims abstract description 6
- 238000013461 design Methods 0.000 claims description 12
- 230000006870 function Effects 0.000 claims description 12
- 238000004513 sizing Methods 0.000 claims description 11
- 238000012795 verification Methods 0.000 claims description 10
- 230000009467 reduction Effects 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000000638 solvent extraction Methods 0.000 claims description 3
- 230000006872 improvement Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
Abstract
The invention discloses a method for reducing metal area, which comprises the following steps: step one, carrying out graph segmentation on a large metal block, comprising the following steps: the original pattern of the large metal block is subtracted from the pattern of the through holes or the contact holes included in the large metal block, and then the original pattern of the large metal block from which the pattern of the through holes or the contact holes is subtracted is divided into a plurality of block patterns. Step two, sequentially verifying and classifying each block graph, comprising the following steps: subtracting the block pattern from the original pattern of the large metal block to form an intermediate pattern; if the middle graph and the graph of the metal line on the peripheral side of the large metal block are kept as an integral structure, the block graph is verified to be of a first type, and otherwise, the block graph is verified to be of a second type; step three, carrying out graph integration, comprising: and integrating all the second type of block patterns and the patterns of the areas provided with the through holes or the contact holes in the original patterns to form new patterns of the large metal blocks. The invention can automatically reduce the area of the large metal block, save time and labor cost and improve efficiency.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to a method for reducing a metal area.
Background
In the layout design process, it is sometimes necessary to place more patterns, such as through holes, in a limited interval. As shown in fig. 1A, the layout is an enlarged view of a region where a large metal block exists in the existing layout, and a metal line 102 and a via 103 exist in a region shown in a layout 101A corresponding to fig. 1A, and the via 103 is used for realizing connection between different metal layers. There is a large metal block in the area shown by the dashed circle 104, which would have a width greater than the width of the metal line 102. In some process design rules, when the area of the large metal block is larger than a certain value, the placement of the through holes needs to be increased, for example, in one process, more than 2 through holes 103 need to be punched in the region of the large metal block with the area larger than 0.3 micrometers × 0.3 micrometers.
FIG. 1B is an enlarged view of the layout of FIG. 1A with additional vias near the large metal block; it can be seen that a through hole 103 is added in the area indicated by the dashed circle 104.
In addition, in practical situations, the circuit may be too dense, and two through holes cannot be formed, so that the area of the large metal block needs to be reduced to meet the requirement of the design rule.
In the existing method, the correction of the layout, such as the increase of the through holes or the reduction of the area of the large metal blocks, is manually completed, which consumes time and labor, because the number of the graphs in the layout is large, and the number of the large metal blocks needing to be corrected can be thousands.
As shown in fig. 2A, as an existing layout thumbnail, as can be seen from the layout 101c in fig. 2A, there are many dense and rough patterns on the layout 101c, and the thumbnail cannot display a specific pattern structure, and is only used to indicate that there are many patterns in the layout 101 c.
As shown in fig. 2B, the layout 101d is a position diagram of the large metal blocks in fig. 2A, and only the large metal blocks that need to be corrected are displayed in the layout 101d, and it can be seen that many dense and dense patterns are displayed in fig. 2B, and the thumbnail cannot display a specific pattern structure, which is used to indicate that only a large number of large metal blocks that need to be corrected are present in the layout 101 d.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a method for reducing the metal area, which can automatically reduce the area of a large metal block, save time and labor cost and improve efficiency.
In order to solve the above technical problems, the method for reducing the metal area provided by the invention comprises the following steps:
the method comprises the following steps of firstly, carrying out graph segmentation on a large metal block needing area reduction, wherein the width of the large metal block is larger than the width of a metal wire on a layout, and a through hole or a contact hole is arranged in the region of the large metal block.
The graph partitioning comprises: and subtracting the area of the large metal block, in which the through holes or the contact holes are arranged, from the original graph of the large metal block, and then dividing the original graph of the large metal block, in which the area of the through holes or the contact holes is subtracted, into a plurality of block graphs.
Step two, sequentially carrying out verification and classification on each block graph, wherein the verification step of each block graph comprises the following steps:
and subtracting the block pattern from the original pattern of the large metal block and forming a middle pattern of the large metal block.
If the middle pattern of the large metal block and the pattern of the metal wire on the peripheral side of the large metal block are kept as an integral structure, the block pattern is verified to be of a first type; otherwise, the block graph is verified as a second class.
Step three, carrying out graph integration, comprising: and integrating the block patterns of the second type and the patterns of the areas, provided with the through holes or the contact holes, in the original patterns of the large metal block to form new patterns of the large metal block, and removing the block patterns of the first type in the new patterns of the large metal block to realize area reduction of the large metal block.
In a further improvement, in the first step, according to the specification of a design rule, the number of through holes or contact holes required to be arranged in the area of the large metal block is greater than the number of through holes or contact holes arranged in the large metal block.
In the third step, according to the specification of the design rule, the number of the through holes or the contact holes required to be arranged in the area of the large metal block after the graph integration is less than or equal to the number of the through holes or the contact holes arranged in the large metal block.
The further improvement is that before the step one, the method further comprises the following steps: and picking out the original graph of the large metal block from the layout data.
In a further improvement, the original pattern of the large metal block is automatically picked out from the layout data through a SIZING function.
In a further improvement, the SIZING function is implemented in the C + + language.
In a further improvement, the SIZING function picks out the original patterns of all the large metal blocks included in the layout data.
In a further improvement, the steps one to three are circularly carried out until the area of all the large metal blocks is reduced.
In a further improvement, in the first step, the original pattern subtraction area of the large metal block further includes an overlapping area between the via hole or the contact hole and the large metal block due to overlay error.
According to the design rule, the number of the contact holes or the through holes arranged in the interval of the area of the large metal block larger than 0.3 micrometer multiplied by 0.3 micrometer is more than 2.
In a further improvement, the contact hole is arranged at the bottom of the first metal layer and is positioned at the top of a gate structure, a source region or a drain region of the semiconductor device.
In a further refinement, the via is disposed between metal layers above the first metal layer.
The further improvement is that the pattern of the through hole is a square block, and the pattern of the contact hole is a square block.
In a further improvement, the side length of the through hole is smaller than the width of the metal wire, and the side length of the contact hole is smaller than the width of the metal wire.
In a further improvement, the metal line is also provided with the via hole or the contact hole.
In a further improvement, in the second step, when the block pattern is verified to be of the second type, the connection between the middle pattern of the large metal block and the pattern of the metal line on the peripheral side of the large metal block is broken or the width of the connection is reduced.
The invention can automatically realize the reduction of the area of the large metal block and make the area of the large metal block meet the requirement of the design rule, can save time and labor cost and can improve the efficiency.
In addition, as for a layout, a large number of large metal blocks are often arranged, and the automatic reduction of all the large metal blocks in the layout can be realized, so that the time and labor cost can be greatly saved, and the efficiency can be greatly improved.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1A is an enlarged view of an area in a prior art layout where large metal blocks are present;
FIG. 1B is an enlarged view of the layout of FIG. 1A with additional vias near the large metal block;
FIG. 2A is a prior art layout thumbnail;
FIG. 2B is a view of the position of FIG. 2A where a large metal block is present;
FIG. 3 is a flow chart of a method of reducing metal area in accordance with an embodiment of the present invention;
FIG. 4A is a diagram of a metal line near a large metal block in a layout according to a method of an embodiment of the present invention;
FIG. 4B is a diagram of a large metal block picked from FIG. 4A;
FIG. 4C is a graph of the large metal block of FIG. 4B after graphical segmentation;
FIG. 4D is an intermediate pattern formed during verification of a second class of tile patterns in accordance with an embodiment of the present invention;
fig. 4E is an intermediate pattern formed during verification of a first type of tile pattern in a method according to an embodiment of the present invention.
Detailed Description
FIG. 3 is a flow chart of a method for reducing metal area according to an embodiment of the present invention; the method for reducing the metal area of the embodiment of the invention comprises the following steps:
before the subsequent step one, the method comprises the following steps: the original pattern of the large metal block 202 is picked from the layout data. As shown in fig. 4A, it is a graph of a metal line 201 near a large metal block 202 in the layout of the method according to the embodiment of the present invention; as shown in fig. 4A, a large metal block 202 is provided on a metal line 201, and 2 contact holes 203 and 1 via hole 204 are provided on the large metal block 202.
Preferably, the original pattern of the large metal block 202 is automatically picked out from the layout data by the SIZING function. The SIZING function is implemented in the C + + language. The SIZING function can be implemented using functions already available in the layout tool, or alternatively programmed; the SIZING function can sort out the large metal blocks 202 that are required based on the size of the metal.
The SIZING function picks out the original patterns of all the large metal blocks 202 included in the layout data.
For the graph in FIG. 4A, the large metal block 202 may be sorted out; FIG. 4B shows a diagram of the large metal block 202, taken alone from FIG. 4A.
Step one, carrying out graph segmentation on a large metal block 202 which needs to be subjected to area reduction, wherein the width of the large metal block 202 is larger than that of a metal wire 201 on a layout, and a through hole 204 or a contact hole 203 is arranged in the region of the large metal block 202.
The graph partitioning comprises: the original pattern of the large metal block 202 is divided into a plurality of block patterns by subtracting the area of the large metal block 202 where the through hole 204 or the contact hole 203 is arranged from the original pattern of the large metal block 202, and then dividing the original pattern of the large metal block 202 where the area of the through hole 204 or the contact hole 203 is subtracted from the original pattern of the large metal block.
In the embodiment of the present invention, the original pattern subtraction area of the large metal block 202 further includes an overlapping area between the via hole 204 or the contact hole 203 and the large metal block 202 due to an overlay error. Therefore, the formation of the through hole 204 or the contact hole 203 is not adversely affected by the overlay error after the large metal block 202 is reduced.
As shown in fig. 4C, the large metal block 202 of fig. 4B is divided into 9 blocks, i.e., the marks 2021, 2022, and 2029, respectively.
Step two, sequentially carrying out verification and classification on each block graph, wherein the verification step of each block graph comprises the following steps:
the tiling pattern is subtracted from the original pattern of the large metal block 202 and an intermediate pattern of the large metal block 202 is formed.
If the middle pattern of the large metal block 202 and the pattern of the metal line 201 on the peripheral side of the large metal block 202 remain as an integral structure, the tile pattern is verified as a first type; otherwise, the block graph is verified as a second class. In the embodiment of the present invention, when the tile pattern is verified as the second type, the connection between the middle pattern of the large metal block 202 and the pattern of the metal line 201 on the peripheral side of the large metal block 202 is broken or the width of the connection is reduced.
Fig. 4D shows an intermediate pattern formed during verification of a second type of block pattern in the method according to the embodiment of the present invention; in fig. 4D, the block pattern to be verified is the block pattern corresponding to the mark 2021, and the middle pattern formed by subtracting the block pattern 2021 from the large metal block 202 is denoted by a mark 202a, and it can be seen that the middle pattern 202a and the metal line 201 are not connected at the dotted circle 301, and therefore are not an integral structure, so that the block pattern 2021 is classified into the second category.
Fig. 4E shows an intermediate pattern formed in the verification process of a first type of block pattern in the method according to the embodiment of the present invention; the block pattern in fig. 4E is the block pattern corresponding to the mark 2022, and the middle pattern after subtracting the block pattern 2022 is denoted by the mark 202b, which shows that the middle pattern 202b and the two layers of metal lines 201 can still form a complete connection, so the pattern structure after removing the block pattern 2022 is still the whole structure, and the block pattern 2022 is classified as the first type.
Similarly, the block patterns 2021, 2022 to 2029 can be divided into two categories by verifying each of the block patterns corresponding to the marks 2023, 2024 to 2029, and finally, the block patterns 2021, 2027 and 2028 can be classified into the second category and the block patterns 2022 to 2026 and 2029 can be classified into the first category.
Step three, carrying out graph integration, comprising: and integrating all the block patterns of the second type and the patterns of the areas, provided with the through holes 204 or the contact holes 203, in the original patterns of the large metal block 202 to form new patterns of the large metal block 202, and removing all the block patterns of the first type in the new patterns of the large metal block 202 to realize area reduction of the large metal block 202.
In the embodiment of the present invention, in the first step, according to the specification of the design rule, the number of the through holes 204 or the contact holes 203 required to be arranged in the area of the large metal block 202 is greater than the number of the through holes 204 or the contact holes 203 arranged in the large metal block 202. After the area of the large metal block 202 is reduced, there are: in the third step, according to the specification of the design rule, the number of the through holes 204 or the contact holes 203 required to be arranged in the area of the large metal block 202 after the pattern integration is less than or equal to the number of the through holes 204 or the contact holes 203 arranged in the large metal block 202. Therefore, the area of the large metal block 202 is reduced without adding the via hole 204 or the contact hole 203. In one or more processes, the number of the contact holes 203 or the through holes 204 arranged in the interval of the area of the large metal block 202 larger than 0.3 micrometer x 0.3 micrometer is more than 2 according to the design rule.
The above steps one to three are to automatically shrink one of the large metal blocks 202. Since a layout has a large number of large metal blocks 202, the steps from the first step to the third step are performed in a circulating manner until the area of all the large metal blocks 202 is reduced.
The contact hole 203 is arranged at the bottom of the first metal layer and the contact hole 203 is positioned at the top of the gate structure, the source region or the drain region of the semiconductor device.
The vias 204 are disposed between metal layers above the first metal layer.
The through hole 204 is in a square shape, and the contact hole 203 is in a square shape.
The side length of the through hole 204 is smaller than the width of the metal wire 201, and the side length of the contact hole 203 is smaller than the width of the metal wire 201.
The metal line 201 is also provided with the via 204 or the contact 203.
According to the embodiment of the invention, the large metal block 202 is subjected to graph segmentation to obtain a plurality of block graphs, then the block graphs are verified and classified to determine whether the block graphs can be removed from the large metal block 202, and then the large metal block 202 with the reduced area is formed by graph integration.
In addition, as for a layout, a large number of large metal blocks 202 are often provided, and the embodiment of the invention can automatically reduce all the large metal blocks 202 in the layout, so that the embodiment of the invention can greatly save time and labor cost and greatly improve efficiency.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (16)
1. A method for reducing metal area is characterized by comprising the following steps:
the method comprises the following steps that firstly, graph segmentation is carried out on a large metal block needing area reduction, the width of the large metal block is larger than the width of a metal wire on a layout, and a through hole or a contact hole is arranged in the region of the large metal block;
the graph partitioning comprises: subtracting the area of the large metal block, in which the through holes or the contact holes are arranged, from the original graph of the large metal block, and then dividing the original graph of the large metal block, in which the area of the through holes or the contact holes is subtracted, into a plurality of block graphs;
step two, sequentially carrying out verification and classification on each block graph, wherein the verification step of each block graph comprises the following steps:
subtracting the block graph from the original graph of the large metal block and forming a middle graph of the large metal block;
if the middle pattern of the large metal block and the pattern of the metal wire on the peripheral side of the large metal block are kept as an integral structure, the block pattern is verified to be of a first type; otherwise, the block graph is verified to be of a second type;
step three, carrying out graph integration, comprising: and integrating the block patterns of the second type and the patterns of the areas, provided with the through holes or the contact holes, in the original patterns of the large metal block to form new patterns of the large metal block, and removing the block patterns of the first type in the new patterns of the large metal block to realize area reduction of the large metal block.
2. The method of reducing metal area of claim 1, wherein: in the first step, according to the rule of design, the number of through holes or contact holes required to be arranged in the area of the large metal block is larger than the number of through holes or contact holes arranged in the large metal block.
3. The method of reducing metal area of claim 2, wherein: in the third step, according to the specification of the design rule, the number of the through holes or the contact holes required to be arranged in the area of the large metal block after the graph integration is less than or equal to the number of the through holes or the contact holes arranged in the large metal block.
4. The method of reducing metal area of claim 1, wherein: before the first step, the method further comprises the following steps: and picking out the original graph of the large metal block from the layout data.
5. The method of reducing metal area of claim 4, wherein: and automatically picking out the original graph of the large metal block from the layout data through an SIZING function.
6. The method of reducing metal area of claim 5, wherein: the SIZING function is implemented in the C + + language.
7. The method of reducing metal area of claim 5, wherein: the SIZING function picks out the original graphs of all the large metal blocks included in the layout data.
8. The method of reducing metal area of claim 5, wherein: and circularly performing the first step to the third step until the area of all the large metal blocks is reduced.
9. The method of reducing metal area of claim 1, wherein: in the first step, the original pattern subtraction area of the large metal block further includes an overlapping area between the via hole or the contact hole and the large metal block due to overlay error.
10. A method of reducing metal area as claimed in claim 2 or 3, wherein: according to the specification of design rules, the number of the contact holes or the through holes arranged in the interval of the area of the large metal block larger than 0.3 micrometer multiplied by 0.3 micrometer is more than 2.
11. The method of reducing metal area of claim 1, wherein: the contact hole is arranged at the bottom of the first metal layer and is positioned at the top of a grid structure, a source region or a drain region of the semiconductor device.
12. The method of reducing metal area of claim 1, wherein: the through holes are arranged between the metal layers above the first metal layer.
13. The method of reducing metal area of claim 1, wherein: the through hole is in a square shape, and the contact hole is in a square shape.
14. The method of reducing metal area of claim 13, wherein: the side length of the through hole is smaller than the width of the metal wire, and the side length of the contact hole is smaller than the width of the metal wire.
15. The method of reducing metal area of claim 14, wherein: the through hole or the contact hole is also provided on the metal line.
16. The method of reducing metal area of claim 1, wherein: in the second step, when the block pattern is verified to be of the second type, the connection between the middle pattern of the large metal block and the pattern of the metal line on the peripheral side of the large metal block is disconnected or the width of the connection part is reduced.
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| CN202110459064.8A CN113221498A (en) | 2021-04-27 | 2021-04-27 | Method for reducing metal area |
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