CN113206062A - 半导体装置与制造半导体装置的方法 - Google Patents

半导体装置与制造半导体装置的方法 Download PDF

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CN113206062A
CN113206062A CN202110203188.XA CN202110203188A CN113206062A CN 113206062 A CN113206062 A CN 113206062A CN 202110203188 A CN202110203188 A CN 202110203188A CN 113206062 A CN113206062 A CN 113206062A
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layer
sacrificial
epitaxial
source
epitaxial structure
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黄旺骏
陈豪育
程冠伦
王志豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US17/115,679 external-priority patent/US11637101B2/en
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Publication of CN113206062A publication Critical patent/CN113206062A/zh
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Abstract

一种半导体装置与制造半导体装置的方法，半导体装置包含栅极结构、源极/漏极磊晶结构、前侧互连结构、背侧通孔件、隔离材料及侧壁间隔物。源极/漏极磊晶结构在栅极结构的一侧上。前侧互连结构在源极/漏极磊晶结构的前侧上。背侧通孔件连接至源极/漏极磊晶结构的背侧。隔离材料在背侧通孔件的一侧上且接触栅极结构。侧壁间隔物在背侧通孔件与隔离材料之间。隔离材料的高度大于侧壁间隔物的高度。

Description

半导体装置与制造半导体装置的方法
技术领域
本揭露涉及半导体装置及其制造方法。
背景技术
半导体集成电路(integrated circuit；IC)产业已经历指数式增长。IC材料及设计上的技术进步已产生多代IC，其中每一代具有比前一代小且复杂的电路。在IC演化的过程中，功能密度(即，每晶片面积的互连装置的数目)已大体上增大，而几何形状大小(即，使用制造制程能够产生的最小组件(或线))已减小。此缩小制程通常通过提高生产效率及降低相关联成本来提供益处。
发明内容
根据一些实施方式，一种半导体装置包含栅极结构、源极/漏极磊晶结构、前侧互连结构、背侧通孔件、隔离材料及侧壁间隔物。源极/漏极磊晶结构在栅极结构的一侧上。前侧互连结构在源极/漏极磊晶结构的一前侧上。背侧通孔件连接至源极/漏极磊晶结构的背侧。隔离材料在背侧通孔件的一侧上且接触栅极结构。侧壁间隔物在背侧通孔件与隔离材料之间。隔离材料的高度大于侧壁间隔物的高度。
根据一些实施方式，一种半导体装置包含多个通道层、栅极结构、第一源极/漏极磊晶结构、内部间隔物、背侧通孔件、侧壁间隔物及隔离材料。通道层以一间隔分开的方式一个配置在另一个上。栅极结构围绕每一通道层。第一源极/漏极磊晶结构在栅极结构的一侧上且连接至通道层。内部间隔物介于栅极结构与第一源极/漏极磊晶结构之间。背侧通孔件连接至第一源极/漏极磊晶结构的背侧。侧壁间隔物接触栅极结构且在背侧通孔件的一侧上。隔离材料在背侧通孔件的该侧上且接触栅极结构及侧壁间隔物。
根据一些实施方式，一种制造半导体装置的方法包含在基板中蚀刻凹部。在基板中的凹部中形成牺牲磊晶插塞。在牺牲磊晶插塞上方形成源极/漏极磊晶结构。在源极/漏极磊晶结构的一侧上形成栅极结构。移除基板，使得牺牲磊晶插塞突出于源极/漏极磊晶结构的一背侧。在牺牲磊晶插塞的一侧上形成侧壁间隔物，使得牺牲磊晶插塞的一部分由侧壁间隔物暴露。在由侧壁间隔物暴露的牺牲磊晶插塞的部分上形成牺牲磊晶结构。在牺牲磊晶结构的一侧及侧壁间隔物上形成隔离材料。用背侧通孔件替换牺牲磊晶插塞及牺牲磊晶结构。
附图说明
本揭露的态样将在结合附图阅读时自以下详细描述最佳地了解。请注意，根据产业中的标准方法，各种特征未按比例绘制。实际上，为了论述清楚起见，各种特征的尺寸可以任意地增大或减小。
图1至图20E说明根据本揭露的一些实施方式的处于各种阶段的制造半导体装置的方法；
图21A为根据本揭露的一些实施方式的半导体装置的透视图；
图21B为沿着图21A中的线B-B截取的横截面图；
图21C为沿着图21A中的线C-C截取的横截面图；
图21D为沿着图21A中的线D-D截取的横截面图。
【符号说明】
105:硬遮罩
102:沟槽
104:半导体条带
108:第一牺牲层
110:基板
110a:前侧
110b:背侧
112:基底部分
112r:源极区域凹部
120:半导体堆叠
122:第一半导体层
123:凹部
124:第二半导体层
130:隔离结构
140:第二牺牲层
142:沟槽
150:虚设鳍结构
152:介电层
154:虚设鳍
158:凹部
160:遮罩层
170:牺牲栅极介电层
180:虚设栅极结构
182:虚设栅极层
184:衬垫层
186:遮罩层
190:栅极间隔物
205:遮罩层
210:内部间隔物
220:牺牲磊晶插塞
230:底部磊晶结构
235:气隙
240:顶部磊晶结构
250:前侧接触蚀刻终止层
255:前侧层间介电质
257:沟槽
260:栅极结构
261:最底部表面
262:栅极介电层
264:栅极电极
266:界面层
270:前侧金属合金层
280:触点
290:前侧多层互连
292:介层孔或触点
294:金属线
310:侧壁间隔物
310’:毯覆层
312:背侧表面
314:最上层表面
320:牺牲磊晶结构
324:侧壁
326:底部表面
330:隔离材料
332:开口
334:凹部
340:背侧接触蚀刻终止层
350:背侧金属合金层
360:背侧通孔件
362:第一部分
362s:侧壁
364:第二部分
364s:侧壁
366:第三部分
366s:侧壁
370:背侧多层互连
372:通孔件或触点
374:金属线
375:界面
410:载体基板
A:区域
B-B:线
C-C:线
D-D:线
D:漏极区域
H1:高度
H2:高度
H3:高度
L:通道长度
S:源极区域
T1:厚度
W1:宽度
W2:宽度
θ1:角
θ2:角
θ3:角
具体实施方式
以下揭示内容提供用于实施提供的标的的不同特征的许多不同实施方式或实例。组件及配置的特征实例将在下文描述以简化本揭露。当然，这些各者仅为实例且不欲为限制性的。举例而言，在随后的描述中的第一特征形成于第二特征上方或上可包含第一特征及第二特征是直接接触地形成的实施方式，且亦可包含额外特征可形成于第一特征与第二特征之间，使得第一特征及第二特征不可直接接触的实施方式。另外，本揭露可在各种实例中重复参考数字及/或字母。此重复是出于简单及清楚的目的且本身并不规定论述的各种实施方式及/或组态之间的关系。
此外，为了方便用于描述如诸图中所图示的一个元件或特征与另一元件或特征的关系的描述，在本文中可使用空间相对术语，诸如“在……下面”、“在……之下”、“下部”、“在……之上”、“上部”及类似术语。空间相对术语意欲涵盖除了诸图中所描绘的定向以外的元件在使用或操作时的不同定向。装置可另外定向(旋转90度或处于其他定向)，且本文中所使用的空间相关描述符可类似地加以相应解释。
如本文中所使用，“大约”、“约”、“近似”或“实质上”应大体上意味着在给定值或范围的20％内或10％或5％内。本文中给出的数值数量是近似值，此意味着术语“大约”、“约”、“近似”或“实质上”可以在未明确说明的情况下进行推断。
环绕式栅极(gate all around；GAA)晶体管结构可通过任何合适方法来图案化。举例而言，这些结构可使用包含双图案化或多图案化制程的一或多种光微影制程来图案化。一般地，双图案化或多图案化制程组合光微影制程与自对准制程，从而产生间距例如小于使用单一的直接光微影制程另外可获得的间距的图案。举例而言，在一个实施方式中，在一基板上方形成一牺牲层且使用光微影制程来图案化该牺牲层。使用自对准制程与该经图案化的牺牲层并排形成间隔物。接着移除该牺牲层，且剩余间隔物因而可用以图案化GAA结构。
本揭露是关于半导体装置及其形成方法。更特别地，本揭露的一些实施方式是关于包含放大的背侧通孔件的GAA装置，这些放大的背侧通孔件用于改良背侧通孔件的电效能。本文中提供的GAA装置包含p型GAA装置或n型GAA装置。此外，GAA装置可具有与单一的连续栅极结构或多个栅极结构相关联的一或多个通道区域(例如，纳米线)。一般技术者可辨识可自本揭露的态样获益的半导体装置的其他实例。举例而言，如本文中所描述的一些实施方式亦可应用于鳍式晶体管(FinFET)装置、亚米茄栅极(Ω-栅极)装置及/或派栅极(π-栅极)装置。
图1至图20E说明根据本揭露的一些实施方式的处于各种阶段的制造半导体装置的方法。在一些实施方式中，图1至图20E中所示的半导体装置可为在处理集成电路(integrated circuit；IC)或其部分期间制造的中间装置，IC可包含静态随机存取记忆体(static random access memory；SRAM)、逻辑电路、被动组件(诸如电阻器、电容器及感应器)及/或主动组件(诸如p型场效晶体管(p-type field effect transistor；PFET)、n型FET(n-type FET；NFET)、多栅极FET、金属氧化物半导体场效晶体管(metal-oxidesemiconductor field effect transistor；MOSFET)、互补金属氧化物半导体(complementary metal-oxide semiconductor；CMOS)晶体管、双极晶体管、高电压晶体管、高频率晶体管、其他记忆细胞及其组合。
参考图1。提供基板110，此基板可为晶圆的一部分。基板110具有前侧110a及与前侧110a相反的背侧110b。在一些实施方式中，基板110可包含硅(Si)。替代地，基板110可包含锗(Ge)、硅锗(SiGe)、砷化镓(GaAs)或其他适当半导体材料。在一些实施方式中，基板110可包含绝缘体上半导体(semiconductor-on-insulator；SOI)结构，诸如埋入式介电层。亦替代地，基板110可包含诸如通过被称为氧植入分离(separation by implantation ofoxygen；SIMOX)技术的方法、晶圆结合、SEG或另一启动方法形成的埋入式介电层，诸如埋入式氧化物(buried oxide；BOX)层。在各种实施方式中，基板110可包含多种基板结构及材料中的任一者。
形成第一牺牲层108在基板110的前侧110a上。第一牺牲层108可在基板110上磊晶生长，使得第一牺牲层108形成结晶层。第一牺牲层108及基板110具有不同或相同的材料及/或成分。在一些实施方式中，第一牺牲层108由硅锗(SiGe)或硅制成。在一些实施方式中，省略第一牺牲层108。
半导体堆叠120经由磊晶在第一牺牲层108上形成，使得半导体堆叠120形成结晶层。半导体堆叠120包含交替堆叠的第一半导体层122及第二半导体层124。第一半导体层122及第二半导体层124由具有不同晶格常数的材料制成，且可包含一或多层Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb或InP。在一些实施方式中，第一半导体层122及第二半导体层124由硅、硅化合物、硅锗、锗或锗化合物制成。在图1中，安置三层第一半导体层122及三层第二半导体层124。然而，这些层的数目不限于三，且可低至1(每一层)且在一些实施方式中，形成2层或4至10层的第一半导体及第二半导体层中的每一者。通过调整堆叠的层的数目，能够调整GAA FET装置的驱动电流。
在一些实施方式中，第一半导体层122可为具有大于零的锗原子百分比的SiGe层。在一些实施方式中，第一半导体层122的锗百分比在处于约15百分比与约100百分比之间的范围内。在一些实施方式中，第一半导体层122的厚度在处于约3nm与约20nm之间的范围内。
在一些实施方式中，第二半导体层124可为不含锗的纯硅层。第二半导体层124亦可为例如具有低于约1百分比的锗原子百分比的实质上纯粹的硅层。此外，第二半导体层124可为本质的(intrinsic)，这些第二半导体层不掺杂p型及n型杂质。在一些实施方式中，第二半导体层124的厚度在介于约3nm与约60nm之间的范围内。
形成经图案化的硬遮罩105在半导体堆叠120上方。在一些实施方式中，经图案化的硬遮罩105由氮化硅、氧氮化硅、碳化硅、碳氮化硅或类似物形成。经图案化的硬遮罩105覆盖半导体堆叠120的一部分，同时留下半导体堆叠120的另一部分未被覆盖。
参考图2。图1的半导体堆叠120、第一牺牲层108及基板110是使用经图案化的硬遮罩105作为遮罩来图案化以形成沟槽102。相应地，形成多个半导体条带104。沟槽102延伸至基板110中，且具有实质上彼此平行的纵向方向。沟槽102在基板110中形成基底部分112，其中基底部分112突出于基板110，且半导体条带104分别在基板110的基底部分112之上形成。替代地，半导体堆叠120及牺牲层108的剩余部分因此被称为半导体条带104。
可为浅沟槽隔离(shallow trench isolation；STI)区域的隔离结构130在沟槽102中形成。该形成可包含例如使用可流动化学气相沉积(flowable chemical vapordeposition；FCVD)用介电层填充沟槽102及执行化学机械抛光(chemical mechanicalpolish；CMP)以使介电材料的顶表面与硬遮罩105的顶表面齐平。接着使隔离结构130凹陷。所得隔离结构130的顶表面可与第一牺牲层108的底表面齐平，或可处于第一牺牲层108的顶表面与底表面之间的中间位准。
参考图3。第二牺牲层140在隔离结构130之上形成且分别覆盖半导体条带104。在一些实施方式中，第二牺牲层140由诸如硅锗或其他合适材料的半导体材料制成。在一些其他实施方式中，第二牺牲层140可为介电材料。第二牺牲层140彼此分离，使得沟槽142形成于这些第二牺牲层之间。
多个虚设鳍结构150分别形成于沟槽142中。在一些实施方式中，一介电层在第二牺牲层140之上共形地形成，且一填充材料填充于沟槽142中。接着执行平坦化(例如，CMP)制程以移除该介电层及该填充材料的多余部分以分别在沟槽142中形成虚设鳍结构150。因而，每一虚设鳍结构150包含介电层152及在介电层152之上的虚设鳍154。在一些实施方式中，利用ALD制程或其他合适制程来沉积介电层152。在一些实施方式中，介电层152及虚设鳍154包含氮化硅、氧化硅、氧氮化硅、SiCN、SiCON、SiOC或其他合适材料。举例而言，介电层152包含氮化硅，且虚设鳍154包含二氧化硅。
随后，使虚设鳍结构150凹陷以在这些虚设鳍结构上形成凹部158。在一些实施方式中，执行多个蚀刻制程以使虚设鳍结构150凹陷。这些蚀刻制程包含干式蚀刻制程、湿式蚀刻制程或其组合。遮罩层160接着分别形成于凹部158中。在一些实施方式中，遮罩层160由氮化硅、氧氮化硅、碳化硅、碳氮化硅或类似物形成。举例而言，遮罩材料在第二牺牲层140及虚设鳍结构150上形成，且执行平坦化(例如，CMP)制程以移除遮罩材料的多余部分以形成遮罩层160。
参考图4。移除第二牺牲层140及经图案化的硬遮罩105，且共形地形成牺牲栅极介电层170在遮罩层160、虚设鳍结构150及第一及第二半导体层122及124上。在一些实施方式中，牺牲栅极介电层170包含二氧化硅、氮化硅、高κ介电材料或其他合适材料。在各种实例中，通过以下各者来沉积牺牲栅极介电层170：ALD制程、CVD制程、次大气压化学气相沉积(subatmospheric CVD；SACVD)制程、可流动CVD制程、PVD制程或其他合适制程。举例说明，牺牲栅极介电层170可用以防止后续处理(例如，虚设栅极结构的后续形成)损害第一及第二半导体层122及124。
随后，形成虚设栅极结构180在牺牲栅极介电层170上。每一虚设栅极结构180包含虚设栅极层182、形成于虚设栅极层182上方的衬垫层184及形成于衬垫层184上方的遮罩层186。在一些实施方式中，可在牺牲栅极介电层170上方形成虚设栅极材料(未示出)，且在虚设栅极材料上方形成衬垫层184及遮罩层186。接着使用衬垫层184及遮罩层186作为遮罩来图案化虚设栅极材料以形成虚设栅极层182。因而，虚设栅极层182、衬垫层184及遮罩层186被称为虚设栅极结构180。在一些实施方式中，虚设栅极层182可由多晶硅(poly-Si)、多晶硅锗(poly-SiGe)或其他合适材料制成。衬垫层184可由氮化硅或其他合适材料制成，且遮罩层186可由二氧化硅或其他合适材料制成。
参考图5。栅极间隔物190分别在虚设栅极结构180的侧壁上形成。栅极间隔物190可包含密封间隔物及主间隔物(未示出)。栅极间隔物190包含一或多种介电材料，诸如氧化硅、氮化硅、氧氮化硅、SiCN、SiCxOyNz或其组合。密封间隔物在虚设栅极结构180的侧壁上形成且主间隔物在密封间隔物上形成。栅极间隔物190能够使用诸如以下各者的沉积方法形成：电浆增强化学气相沉积(plasma enhanced chemical vapor deposition；PECVD)、低压化学气相沉积(low-pressure chemical vapor deposition；LPCVD)、次大气压化学气相沉积(sub-atmospheric chemical vapor deposition)或类似沉积方法。栅极间隔物190的形成可包含毯覆形成间隔物层，及接着执行蚀刻操作以移除这些间隔物层的水平部分。栅极间隔物层的剩余垂直部分形成栅极间隔物190。
随后，使用虚设栅极结构180及栅极间隔物190作为遮罩来图案化第一及第二半导体层122及124及第一牺牲层108，使得基板110的基底部分112的部分暴露。在此蚀刻制程期间，遮罩层160可在未被虚设栅极结构180或栅极间隔物190覆盖的区域处凹陷。在一些实施方式中，图案化制程是利用非等向性干式蚀刻制程来执行。在一些实施方式中，干式蚀刻制程蚀刻第一及第二半导体层122及124及第一牺牲层108(例如，Si及SiGe)比蚀刻遮罩层160(例如，金属氧化物、SiON及SiOCN)快得多。归因于此蚀刻选择性，干式蚀刻制程垂直地图案化第一及第二半导体层122及124及第一牺牲层108而不全部蚀刻遮罩层160。在图5中，遮罩层160的被虚设栅极结构180或栅极间隔物190覆盖的部分具有大于遮罩层160的凹陷部分的高度的高度。
参考图6。第一半导体层122经水平地凹陷(蚀刻)，因此第一半导体层122的边缘实质上位于栅极间隔物190下方且形成凹部123。第一半导体层122的蚀刻包含湿式蚀刻及/或干式蚀刻。
参考图7。内部间隔物210分别形成于第一半导体层122的凹部123(参见图6)中。举例而言，在图6的结构上方形成介电材料层，且执行一或多个蚀刻操作以形成这些内部间隔物210。在一些实施方式中，内部间隔物210包含基于氮化硅的材料(诸如SiN、SiON、SiOCN或SiCN及其组合)且不同于栅极间隔物190的材料。在一些实施方式中，内部间隔物210为氮化硅。内部间隔物210可完全填充凹部123，如图7所示。介电材料层可使用CVD(包含LPCVD及PECVD)、PVD、ALD或其他合适制程形成。蚀刻操作包含一或多个湿式及/或干式蚀刻操作。在一些实施方式中，蚀刻在一些实施方式中为等向性蚀刻。
参考图8A及图8B，其中图8B为沿着图8A中的线B-B截取的横截面图。在图7的结构上方形成遮罩层205。为了清楚起见，遮罩层205用虚线来图示。遮罩层205形成以覆盖基底部分112的漏极区域D而不覆盖基底部分112的至少一个源极区域S，接着凹陷基底部分112的源极区域S，从而在基底部分112中产生至少一个源极区域凹部112r。在一些实施方式中，遮罩层205可为通过合适光微影制程形成的光阻剂遮罩。举例而言，光微影制程可包含在如图7中图示的结构上方旋涂一光阻剂层、执行曝光后烘烤制程及显影该光阻剂层以形成遮罩层205。在一些实施方式中，图案化抗蚀剂以形成经图案化的遮罩元件可使用电子束(e-beam)微影制程或极紫外光(extreme ultraviolet；EUV)微影制程来执行。
一旦遮罩层205形成，源极区域凹部112r即能够使用例如非等向性蚀刻制程在源极区域S中形成。在一些实施方式中，非等向性蚀刻可通过利用电浆源及反应气体的干式化学蚀刻来执行。举例说明而非限制，电浆源可为感应耦合电浆(inductively coupledplasma；ICR)源、变压器耦合电浆(TCP)源、电子回旋共振(electron cyclotronresonance；ECR)源或类似者，且反应气体可为基于氟的气体(诸如SF6、CH2F2、CH3F、CHF3或类似物)、基于氯的其他(例如，Cl2)、溴化氢气体(HBr)、氧气(O2)、类似物或其组合。
参考图9A至图9C，其中图9B为沿着图9A中的线B-B截取的横截面图，且图9C为沿着图9A中的线C-C截取的横截面图。执行磊晶生长制程以在源极区域凹部112r中生长磊晶材料，直至磊晶材料堆积填充源极区域凹部112r的牺牲磊晶插塞220。磊晶材料具有不同于基板110的组成，因此导致牺牲磊晶插塞220与基板110之间的不同蚀刻选择性。举例而言，基板110为硅且牺牲磊晶插塞220为硅锗。在一些实施方式中，牺牲磊晶插塞220为不含p型掺杂剂(例如，硼)及n型掺杂剂(例如，磷)的硅锗，此是因为牺牲磊晶插塞220将在后续制程中移除且不充当最终IC产品的晶体管的源极端子。
参考图10。分别在基板110的基底部分112及牺牲磊晶插塞220上形成底部磊晶结构230。在一些实施方式中，半导体材料沉积在基底部分112及牺牲磊晶插塞220上以形成底部磊晶结构230。这些半导体材料包含诸如锗(Ge)或硅(Si)的单元素半导体材料、诸如砷化镓(GaAs)或砷化铝镓(AlGaAs)的化合物半导体材料或诸如硅锗(SiGe)或磷化砷镓(GaAsP)的半导体合金。底部磊晶结构230具有合适的结晶取向(例如，(100)、(110)或(111)结晶取向)。磊晶制程包含CVD沉积技术(例如，气相磊晶(vapor-phase epitaxy；VPE)及/或超高真空CVD(ultra-high vacuum CVD；UHV-CVD))、分子束磊晶及/或其他合适制程。在一些实施方式中，底部磊晶结构230为本质的(intrinsic)。亦即，底部磊晶结构230是未掺杂的。未掺杂的底部磊晶结构230有益于减小自顶部磊晶结构240至基板110的漏电流。底部磊晶结构230的顶表面可处于最底部内部间隔物210的底表面与顶表面之间的中间位准处。
顶部磊晶结构240分别在底部磊晶结构230上形成。在一些实施方式中，半导体材料沉积在底部磊晶结构230上以形成顶部磊晶结构240。这些半导体材料包含诸如锗(Ge)或硅(Si)的单元素半导体材料、诸如砷化镓(GaAs)或砷化铝镓(AlGaAs)的化合物半导体材料或诸如硅锗(SiGe)或磷化砷镓(GaAsP)的半导体合金。顶部磊晶结构240具有合适的结晶取向(例如，(100)、(110)或(111)结晶取向)。在一些实施方式中，顶部磊晶结构240包含源极/漏极磊晶结构。在一些实施方式中，在需要N型装置的情况下，顶部磊晶结构240可包含磊晶生长的磷化硅(SiP)或碳化硅(SiC)。在一些实施方式中，在需要P型装置的情况下，顶部磊晶结构240可包含磊晶生长的硅锗(SiGe)。磊晶制程包含CVD沉积技术(例如，气相磊晶(vapor-phase epitaxy；VPE)及/或超高真空CVD(ultra-high vacuum CVD；UHV-CVD))、分子束磊晶及/或其他合适制程。所要p型或n型杂质在磊晶制程时可以或不可经掺杂。掺杂可通过离子植入制程、电浆浸没离子植入(plasma immersion ion implantation；PIII)制程及/或固体源极扩散制程、其他合适制程或其组合来达成。
虚设鳍结构150用以限制用于磊晶生长顶部磊晶结构240的间隔物。结果，顶部磊晶结构240限定在虚设鳍结构150之间。此可用以生产任何所要大小的顶部磊晶结构240，特别地生产小顶部磊晶结构240以用于减小寄生电容。举例而言，顶部磊晶结构240的宽度(即，邻近两个虚设鳍结构150之间的空间)在约3nm至约100nm的范围内。此外，气隙235可在顶部磊晶结构240下形成。举例而言，气隙235由顶部磊晶结构240、底部磊晶结构230、虚设鳍结构150及隔离结构130界定。在一些实施方式中，顶部磊晶结构240接触虚设鳍结构150，且底部磊晶结构230与虚设鳍结构150间隔分开。
共形地形成前侧接触蚀刻终止层(contact etch stop layer；CESL)250在虚设鳍结构150及顶部磊晶结构240上方。在一些实施方式中，前侧接触蚀刻终止层250可为一或多个受力层。在一些实施方式中，前侧接触蚀刻终止层250具有拉伸应力且由氮化硅(Si3N4)形成。在一些其他实施方式中，前侧接触蚀刻终止层250包含诸如氧氮化物的材料。在又一些其他实施方式中，前侧接触蚀刻终止层250可具有包含多个层的复合结构，诸如上覆于氧化硅层的氮化硅层。前侧接触蚀刻终止层250可使用电浆增强CVD(plasma enhanced CVD；PECVD)形成，然而，亦可使用其他合适的方法，诸如低压CVD(low pressure CVD；LPCVD)、原子层沉积(atomic layer deposition；ALD)及类似方法。
接着在前侧接触蚀刻终止层250上形成前侧层间介电质(interlayerdielectric；ILD)255。前侧层间介电质255可通过化学气相沉积(chemical vapordeposition；CVD)、高密度电浆CVD、旋涂、溅射或其他合适方法形成。在一些实施方式中，前侧层间介电质255包含氧化硅。在一些其他实施方式中，前侧层间介电质255可包含氮氧化硅、氮化硅、包含硅、氧、碳及/或,氢的化合物(例如，氧化硅、SiCOH及SiOC)、低k材料或有机材料(例如，聚合物)。在前侧层间介电质255形成之后，执行诸如CMP的平坦化操作，使得衬垫层184及遮罩层186(参见图9A)被移除且暴露虚设栅极层182及遮罩层160。
参考图11A至图11D，其中图11B为沿着图11A中的线B-B截取的横截面图，图11C为沿着图11A中的线C-C截取的横截面图，且图11D为沿着图11A中的线D-D截取的横截面图。接着移除虚设栅极层182及牺牲栅极介电层170(参见图10)，由此暴露第二半导体层124。前侧层间介电质255在虚设栅极层182的移除期间保护顶部磊晶结构240。虚设栅极层182可使用电浆干式蚀刻及/或湿式蚀刻移除。当虚设栅极层182为多晶硅且前侧层间介电质255为氧化硅时，诸如氢氧化四甲基铵溶液(TMAH)溶液的湿蚀刻剂可用以选择性地移除虚设栅极层182。此后使用电浆干式蚀刻及/或湿式蚀刻移除虚设栅极层182。随后，牺牲栅极介电层170亦被移除。因而，最上层半导体层124暴露。
在虚设栅极层182(参见图10)被移除之后，移除剩余第一半导体层122(参见图9A)，由此形成第二半导体层124的片状物(或线或棒或柱)。第一半导体层122可使用能够选择性地蚀刻第一半导体层122的蚀刻剂来移除或蚀刻。
在一些实施方式中，界面层266视情况形成以围绕第二半导体层124的暴露表面及基板110的基底部分112的暴露表面。在各种实施方式中，界面层266可包含诸如氧化硅(SiO2)或氧氮化硅(SiON)的介电材料，且可通过化学氧化、热氧化、原子层沉积(atomiclayer deposition；ALD)、化学气相沉积(chemical vapor deposition；CVD)及/或其他合适方法形成。
在栅极间隔物190或内部间隔物210之间形成及/或填充栅极结构260。亦即，栅极结构260环绕(包裹)半导体层124。栅极间隔物190安置在栅极结构260的相对侧上。每一栅极结构26包含栅极介电层262及栅极电极264。栅极电极264包含一或多个功函数金属层及一填充金属。栅极介电层262是共形地形成。第二半导体层124被称为半导体装置的通道。栅极介电层262围绕第二半导体层124，且第二半导体层124之间的空间在栅极介电层262沉积之后仍保留。在一些实施方式中，栅极介电层262包含高k材料(k大于7)，诸如氧化铪(HfO2)、氧化锆(ZrO2)、氧化镧(La2O3)、氧化铪铝(HfAlO2)、氧化铪硅(HfSiO2)、氧化铝(Al2O3)或其他合适材料。在一些实施方式中，栅极介电层262可通过执行ALD制程或其他合适制程形成。
栅极电极264的功函数金属层在栅极介电层262上共形地形成，且功函数金属层在一些实施方式中围绕第二半导体层124。功函数金属层可包含诸如TiN、TaN、TiAlSi、TiSiN、TiAl、TaAl或其他合适材料的材料。在一些实施方式中，功函数金属层可通过执行ALD制程或其他合适制程形成。
栅极电极264的填充金属填充栅极间隔物190之间及内部间隔物210之间的剩余空间。亦即，功函数金属层接触栅极介电层262及填充金属且在栅极介电层262与填充金属之间。填充金属可包含诸如钨或铝的材料。在栅极介电层262及栅极电极264沉积之后，接着可执行诸如CMP制程的平坦化制程以移除栅极介电层262及栅极电极264的多余部分以形成栅极结构260。
参考图12。前侧层间介电质255经图案化以在栅极结构260的相对侧上形成沟槽257，接着图案化前侧接触蚀刻终止层250以暴露顶部磊晶结构240。在一些实施方式中，执行多个蚀刻制程以图案化前侧层间介电质255及前侧接触蚀刻终止层250。这些蚀刻制程包含干式蚀刻制程、湿式蚀刻制程或其组合。
在沟槽257中形成触点280。因而，触点280分别接触顶部磊晶结构240。在一些实施方式中，一些触点280互连邻近的顶部磊晶结构240。在一些实施方式中，触点280可由诸如W、Co、Ru、Al、Cu或其他合适材料的金属制成。在触点280沉积之后，接着可执行平坦化制程，诸如化学机械平坦化(chemical mechanical planarization；CMP)制程。因而，触点280的顶表面及前侧层间介电质255的顶表面实质上共面。在一些实施方式中，可在触点280与顶部磊晶结构240之间形成前侧金属合金层(诸如硅化物)270。此外，可在触点280形成之前且在前侧金属合金层270之后在沟槽257中形成阻障层。阻障层可由TiN、TaN或其组合制成。
参考图13。在基板110上方形成包含金属层及金属间介电质(inter-metaldielectric；IMD)的前侧多层互连结构(multilayer interconnection；MLI)290以电性连接半导体装置的各种特征或结构(例如，触点280及/或栅极结构260)。前侧多层互连结构290包含诸如通孔件或触点292的垂直互连件，及诸如金属线294(参见图20B)的水平互连件。各种互连特征可实施包含铜、钨及硅化物的各种导电材料。在一些实例中，使用镶嵌制程以形成铜多层互连结构。
随后，在前侧多层互连结构290之上形成载体基板410。举例而言，载体基板410结合至前侧多层互连结构290。载体基板410可为硅(掺杂或未掺杂的)，或可包含诸如锗的其他半导体材料；化合物半导体；或其组合。载体基板410可在对半导体装置的背侧的后续处理期间提供结构支撑且在一些实施方式中可保留在最终产品中。在一些其他实施方式中，载体基板410可在对半导体装置的背侧的后续处理完成之后移除。在一些实施方式中，载体基板410是通过例如熔融结合而结合至多层互连结构290的最上层介电层。
参考图14A至图14D，其中图14B为沿着图14A中的线B-B截取的横截面图，图14C为沿着图14A中的线C-C截取的横截面图，且图14D为沿着图14A中的线D-D截取的横截面图。图13的结构上下“翻转”，且移除基板110及第一牺牲层108(参见图11D及图13)。因而，暴露牺牲磊晶插塞220及不接触牺牲磊晶插塞220的其他底部磊晶结构230。在一些实施方式中，移除制程包含自基板110的背侧薄化基板110，直至牺牲磊晶插塞220暴露。接着通过使用选择性蚀刻制程来移除基板110，此选择性蚀刻制程以比其蚀刻牺牲磊晶插塞220(例如，硅锗)及隔离结构130(例如，介电材料)快的蚀刻速率蚀刻基板110及第一牺牲层108(例如，硅)。在一些实施方式中，用于选择性地移除基板110的选择性蚀刻制程可为湿式蚀刻制程，此湿式蚀刻制程使用诸如四甲基氢氧化铵(tetramethylammonium hydroxide；TMAH)、氢氧化钾(KOH)、NH4OH、类似物或其组合的湿式蚀刻溶液。
参考图15A至图15D，其中图15B为沿着图15A中的线B-B截取的横截面图，图15C为沿着图15A中的线C-C截取的横截面图，且图15D为沿着图15A中的线D-D截取的横截面图。侧壁间隔物的绝缘材料的毯覆层310’是通过使用CVD或其他合适方法共形地形成。毯覆层310’是以共形方式沉积，使得此毯覆层形成以在诸如侧壁的垂直表面、水平表面及牺牲栅极结构的顶部上具有实质上相等的厚度。如图15A至图15D所示，毯覆层310’形成以覆盖隔离结构130、栅极结构260的背侧表面、内部间隔物210的背侧表面及牺牲磊晶插塞220。在一些实施方式中，毯覆层310’沉积至在约2nm至约10nm范围内的厚度T1。在一些实施方式中，毯覆层310’的绝缘材料为低于κ材料。在一些实施方式中，毯覆层310’为基于氮化物的材料，诸如SiN、SiON、SiOCN或SiCN及其组合。
参考图16A至图16D，其中图16B为沿着图16A中的线B-B截取的横截面图，图16C为沿着图16A中的线C-C截取的横截面图，且图16D为沿着图16A中的线D-D截取的横截面图。接着使用非等向性制程来蚀刻毯覆层310’(参见图15A至图15D)以在牺牲磊晶插塞220的基底部分的相反侧上形成侧壁间隔物310，使得牺牲磊晶插塞220的另一部分由侧壁间隔物310暴露。对毯覆层310’执行的非等向性蚀刻可为例如反应离子蚀刻(reactive ion etching；RIE)。在非等向性蚀刻制程期间，自水平表面移除大部分的绝缘材料，从而在垂直表面(诸如牺牲磊晶插塞220的侧壁)上留下介电间隔物层。在一些实施方式中，可执行回蚀制程以减小侧壁间隔物310的高度，使得侧壁间隔物310直接接触牺牲磊晶插塞220的基底部分，同时暴露牺牲磊晶插塞220的另一部分。此外，栅极结构260的部分及隔离结构130的侧壁的部分接触侧壁间隔物310，如图16D所示。如图16C所示，一些不接触牺牲磊晶插塞220的底部磊晶结构230接触一些侧壁间隔物310。在一些实施方式中，侧壁间隔物310的高度H1小于约40nm，例如，约0nm至约40nm。
参考图17A至图17D，其中图17B为沿着图17A中的线B-B截取的横截面图，图17C为沿着图17A中的线C-C截取的横截面图，且图17D为沿着图17A中的线D-D截取的横截面图。通过执行例如选择性生长制程，在未被侧壁间隔物310覆盖的牺牲磊晶插塞220的部分上形成牺牲磊晶结构320。举例而言，形成另一遮罩层以覆盖图16A的结构，且图案化该遮罩层以暴露牺牲磊晶插塞220，且在牺牲磊晶插塞220上形成牺牲磊晶结构320。遮罩层可在牺牲磊晶结构320形成之后移除。在一些实施方式中，牺牲磊晶结构320为不含p型掺杂剂(例如，硼)及n型掺杂剂(例如，磷)的，此是因为牺牲磊晶结构320将在后续制程中移除且不充当最终IC产品的晶体管的源极端子。牺牲磊晶结构320与牺牲磊晶插塞220的组合结构在横截面图中可为锤形状的，且因此被称为牺牲锤形通孔件，此牺牲锤形通孔件在后续处理中将用锤形背侧通孔件替换。举例说明而非限制，牺牲磊晶结构320中的锗原子百分比在约10％至约50％的范围内。在一些实施方式中，牺牲磊晶结构320及牺牲磊晶插塞220具有相同或实质上相同的材料。替代地，牺牲磊晶结构320及牺牲磊晶插塞220具有相同或类似的蚀刻选择性。
归因于牺牲磊晶插塞220的不同表面的不同晶体平面上的不同生长速率，牺牲磊晶结构320的生长包含横向生长及垂直生长。刻面(facets)因此形成为牺牲磊晶结构320的表面。举例说明而非限制，在图17B的横截面图中，牺牲磊晶结构320具有合适的结晶取向(例如，(110)及(111)结晶取向)，使得牺牲磊晶结构320具有六边形横截面。举例而言，牺牲磊晶结构320的底部表面326为(111)刻面(即，底部表面326为面向栅极结构260的面朝下刻面)，且牺牲磊晶结构320的侧壁324为(110)刻面(侧壁刻面)。磊晶制程包含CVD沉积技术(例如，气相磊晶(vapor-phase epitaxy；VPE)及/或超高真空CVD(ultra-high vacuumCVD；UHV-CVD))、分子束磊晶及/或其他合适制程。在一些实施方式中，角θ1形成于牺牲磊晶结构320的底部表面326与侧壁324之间，且角θ1在约140度至约180度(例如，约144.7度至约180度)的范围内，该范围是由牺牲磊晶结构320的材料及/或结晶取向判定。
在一些实施方式中，牺牲磊晶结构320能够通过磊晶沉积/部分蚀刻制程生长，生长重复磊晶沉积/部分蚀刻制程至少一次以扩展牺牲磊晶结构的横向宽度。此重复沉积/部分蚀刻制程亦被称作循环沉积蚀刻(cyclic deposition-etch；CDE)制程。在一些实施方式中，牺牲磊晶结构320是通过选择性磊晶生长(selective epitaxial growth；SEG)生长。举例而言，牺牲磊晶结构320是使用反应气体(诸如作为蚀刻气体的HCl、作为Ge前驱体气体的GeH4、二氯硅烷(dichlorosilane,DCS)及/或作为Si前驱体气体的SiH4、H2及/或作为载体气体的N2)以磊晶方式生长。在一些实施方式中，蚀刻气体可为其他含氯气体或含溴气体，诸如Cl2、BCl3、BiCl3、BiBr3或类似物。如上文论述的CDE制程仅为用于解释如何在牺牲磊晶插塞220上形成牺牲磊晶结构320的一个实例，且其他合适技术亦可用于形成牺牲磊晶结构320。
参考图18A至图18D，其中图18B为沿着图18A中的线B-B截取的横截面图，图18C为沿着图18A中的线C-C截取的横截面图，且图18D为沿着图18A中的线D-D截取的横截面图。形成隔离材料330以填充隔离结构130之间的其余空间。由于牺牲磊晶插塞220被牺牲磊晶结构320及侧壁间隔物310覆盖，因此隔离材料330与牺牲磊晶插塞220间隔分开。在一些实施方式中，隔离材料330可通过合适方法(诸如自旋、化学气相沉积(chemical vapordeposition；CVD))及电浆增强CVD(plasma-enhanced CVD；PECVD))由例如低κ介电材料(具有比二氧化硅低的介电常数的材料)形成，低κ介电材料诸如：氧氮化硅、磷硅酸盐玻璃(phosphosilicate glass；PSG)、硼磷硅酸盐玻璃(borophosphosilicate glass；BPSG)、氟硅玻璃(fluorinated silicate glass；FSG)、SiOxCy、SiOxCyHz、旋涂玻璃(Spin-On-Glass)、旋涂聚合物(Spin-On-Polymer)、碳化硅材料、其化合物、其复合物、其组合或类似材料。亦可使用其他材料，诸如超低κ材料(例如，具有小于约2.9的介电常数)，诸如κ＝2.5至2.6。替代地，隔离材料330及隔离结构130具有实质上相同的材料，例如，氧化物材料。这些材料及制程是作为实例提供且可使用其他材料及制程。
随后，用背侧通孔件360替换牺牲磊晶结构320及牺牲磊晶插塞220(参见图19A至图19D)。确切地说，移除牺牲磊晶结构320及牺牲磊晶插塞220，使得开口332形成于隔离材料330之间及隔离结构130之间。使用例如CMP、氢氟酸/硝酸/乙酸(HF/Nitric/Acetic,HNA)及/或TMAH蚀刻来执行牺牲磊晶结构320及牺牲磊晶插塞220的移除。牺牲磊晶结构320及牺牲磊晶插塞220的移除为选择性蚀刻制程，选择性蚀刻制程以比用于蚀刻隔离结构130及隔离材料330的蚀刻速率高得多的蚀刻速率移除牺牲磊晶结构320及牺牲磊晶插塞220。然而，隔离结构130的部分可被无意地移除，如图18C所示。
在一些实施方式中，部分地移除恰在牺牲磊晶插塞220下面的底部磊晶结构230。在另外一些实施方式中，亦移除恰在经移除的底部磊晶结构230下面的顶部磊晶结构240的一部分。此外，部分地移除内部间隔物210，使得凹部334可邻近内部间隔物210形成。
参考图19A至图19D，其中图19B为沿着图19A中的线B-B截取的横截面图，图19C为沿着图19A中的线C-C截取的横截面图，且图19D为沿着图19A中的线D-D截取的横截面图。背侧接触蚀刻终止层340在开口332及凹部334(参见图18B)中共形地形成。在一些实施方式中，背侧接触蚀刻终止层340由Si3N4形成。在一些其他实施方式中，背侧接触蚀刻终止层340包含诸如氧氮化物的材料。在又一些其他实施方式中，背侧接触蚀刻终止层340可具有包含多个层的复合结构，诸如上覆于氧化硅层的氮化硅层。背侧接触蚀刻终止层340可使用电浆增强CVD(plasma enhanced CVD；PECVD)形成，然而，亦可使用其他合适的方法，诸如低压CVD(low pressure CVD；LPCVD)、原子层沉积(atomic layer deposition；ALD)及类似方法。
随后，移除背侧接触蚀刻终止层340的水平部分以暴露经蚀刻的顶部磊晶结构240，此经蚀刻的顶部磊晶结构充当半导体装置的源极。同时，充当半导体装置的漏极的其他磊晶结构240被隔离材料330覆盖。
在经蚀刻的顶部磊晶结构240之上形成至少一个背侧金属合金层350。可为硅化物层的背侧金属合金层350是通过自对准硅化物(硅化物(salicide))制程在开口332中(参见图18B)且在暴露的顶部磊晶结构240上方形成。在一些实施方式中，背侧金属合金层350可包含选自以下各者的材料：硅化钛、硅化钴、硅化镍、硅化铂、硅化镍铂、硅化铒、硅化钯、其组合或其他合适材料。在一些实施方式中，背侧金属合金层350可包含锗。
接着在开口332中(参见图18B)且在背侧金属合金层350之上形成背侧通孔件360。因而，背侧通孔件360电性连接至经蚀刻的顶部磊晶结构240。在一些实施方式中，背侧通孔件360可由诸如W、Co、Ru、Al、Cu或其他合适材料的金属制成。在背侧通孔件360沉积之后，接着可执行平坦化制程，诸如化学机械平坦化(chemical mechanical planarization；CMP)制程。在一些实施方式中，可在背侧通孔件360形成之前形成阻障层于开口322中。阻障层可由TiN、TaN或其组合制成。
参考图20A至图20D，其中图20B为沿着图20A中的线B-B截取的横截面图，图20C为沿着图20A中的线C-C截取的横截面图，且图20D为沿着图20A中的线D-D截取的横截面图。在隔离结构130及隔离材料330上方形成包含金属层及金属间介电质(inter-metaldielectric；IMD)的背侧多层互连(multilayer interconnection；多层互连结构)370以电连接半导体装置的各种特征或结构(例如，一或多个背侧通孔件360)。背侧多层互连结构370包含诸如通孔件或触点372的垂直连接件及诸如金属线374的水平连接件。各种互连特征可实施包含铜、钨及硅化物的各种导电材料。在一些实例中，使用镶嵌制程以形成铜多层互连结构。
接着自前侧多层互连结构290移除载体基板410(参见图19A至图19D)，且结构再次上下“翻转”。因而，半导体装置形成。确切地说，半导体装置包含作为半导体装置的通道层的第二半导体层124。第二半导体层124以一间隔分开的方式一个配置在另一个之上。栅极结构260围绕或包裹第二半导体层124中的每一者。在一些实施方式中，第二半导体层124的通道长度L在约5nm至约150nm的范围内。半导体装置还包含作为半导体装置的源极及/或漏极的S/D磊晶结构(例如，顶部磊晶结构240及/或底部磊晶结构230)。S/D磊晶结构电连接至第二半导体层124且在栅极结构260的相反侧上。S/D磊晶结构能够经由触点280自半导体装置的前侧连接至外部电路。S/D磊晶结构中的一些(例如，连接至背侧通孔件360的顶部磊晶结构240)能够经由背侧通孔件360自半导体装置的背侧更连接至外部电路。栅极结构260及S/D磊晶结构中的每一者具有面向上的前侧及面向下的背侧。前侧多层互连结构290在栅极结构260及S/D磊晶结构的前侧上方，且背侧通孔件360连接至S/D磊晶结构中的一者的背侧。
图20E为图20B中的区域A的放大图。参考图20B及图20E，背侧通孔件360包含第一部分362、第二部分364及介于第一部分362与第二部分364之间的第三部分366。第一部分362比第二部分364更接近顶部磊晶结构240。第一部分362具有实质上恒定的宽度，第二部分364具有实质上恒定的宽度，且第三部分366具有渐缩侧壁366s。亦即，第三部分366具有大于第一部分362的宽度变化及第二部分364的宽度变化的宽度变化。第一部分362的宽度W1小于第二部分364的宽度W2，使得第三部分366自第二部分364朝向第一部分362渐缩。在一些实施方式中，第一部分362的宽度W1在约5nm至约25nm的范围内。在一些实施方式中，第二部分364的宽度W2在约10nm至约45nm的范围内。此外，背侧通孔件360的高度H2在约15nm至约50nm的范围内。
在一些实施方式中，角θ1在第三部分366的侧壁366s与第一部分362的侧壁362s之间形成，且角θ2大于约140度且小于约180度，例如，约144.7度至约179度。角θ2由牺牲磊晶结构320(参见图17B)的形状判定。在一些实施方式中，角θ2在第三部分366的侧壁366s与第二部分364的侧壁364s之间形成，且角θ1大于约140度且小于约180度，例如，约144.7度至约179度。角θ2由牺牲磊晶结构320(参见图17B)的形状判定。在一些实施方式中，角θ3在第二部分364的侧壁364s与背侧多层互连结构370与背侧通孔件360之间的界面375之间形成，且角θ3在约54.7度至约90度的范围内，例如，约90度。
在一些实施方式中，半导体装置还包含侧壁间隔物310，这些侧壁间隔物在背侧通孔件360的第一部分362的相对侧上。侧壁间隔物310与背侧通孔件360的第二部分364偏移且与背侧通孔件360的第一部分362对准。如图20A所示，侧壁间隔物310更接触底部磊晶结构230。侧壁间隔物310的高度H1小于约40nm。若高度大于约40nm，则牺牲磊晶插塞220(参见图17B)可能不具有用于生长牺牲磊晶结构320的足够表面区域(参见图17B)。背侧通孔件360的高度H2大于侧壁间隔物310的高度H1，使得第二部分364的宽度W2大于第一部分362的宽度W1。在一些实施方式中，侧壁间隔物310中的每一者具有厚度T1，该厚度小于约15nm。若厚度T1大于约15nm，侧壁间隔物310不能共形地形成且在隔离结构130之间合并。此外，侧壁间隔物310与虚设鳍结构150间隔分开。侧壁间隔物310的最上层表面314比栅极结构260的最底部表面261高。此外，侧壁间隔物310与虚设鳍结构150间隔分开。
在一些实施方式中，半导体装置还包含隔离材料330，这些隔离材料在背侧通孔件360的相对侧上。如图20B及图20E所示，隔离材料330包含接触侧壁间隔物310的背侧表面312的一部分。此外，如图20B及图20D所示，隔离材料330接触栅极结构260的栅极介电层262、内部间隔物210中的一些、底部磊晶结构230中的一些、侧壁间隔物310及隔离结构130。此外，在一些实施方式中，侧壁间隔物310夹在隔离材料330与隔离结构130之间及隔离材料与背侧通孔件360之间。侧壁间隔物310具有不同于隔离材料330及/或隔离结构130的材料。举例而言，侧壁间隔物310为氮化物层且隔离材料330及/或隔离结构130为氧化物层。隔离材料330的高度H3大于侧壁间隔物310的高度H1。
在一些实施方式中，半导体装置还包含背侧接触蚀刻终止层340，该背侧接触蚀刻终止层横向地围绕背侧通孔件360。背侧接触蚀刻终止层340与背侧通孔件360的侧壁共形。背侧接触蚀刻终止层340接触隔离材料330及侧壁间隔物310。在一些实施方式中，归因于凹部334(参见图18B)的形成，背侧接触蚀刻终止层340包含接触内部间隔物210的具有较大宽度的一部分。
如图20B及图20E所示，背侧通孔件340的大小由于牺牲磊晶结构320(参见图17B)的形成而扩大。因而，背侧通孔件340与背侧多层互连结构370的通孔件372之间的接触面积增大。此组态减小包含背侧通孔件340本身及背侧通孔件340与背侧多层互连结构370的通孔件372之间的界面的总(寄生)电阻且更提高装置效能。此外，侧壁间隔物310的高度H1能够调谐牺牲磊晶结构320的形状(参见图17B)，且能够获得背侧通孔件340的所要形状。
图21A为根据本揭露的一些实施方式的半导体装置的透视图，图21B为沿着图21A中的线B-B截取的横截面图，图21C为沿着图21A中的线C-C截取的横截面图，且图21D为沿着图21A中的线D-D截取的横截面图。图21A至图21D中的半导体装置与图20A至图20E中的半导体装置之间的区别在于侧壁间隔物310的存在。在图21A至图21D中，省略这些侧壁间隔物310(参见图20A至图20E)。图21A至图21D中的半导体装置的其他相关结构细节与图20A至图20E中的半导体装置类似或实质上相同，且因此，在下文将不重复此方面的描述。
根据一些实施方式，一种半导体装置包含栅极结构、源极/漏极磊晶结构、前侧互连结构、背侧通孔件、隔离材料及侧壁间隔物。源极/漏极磊晶结构在栅极结构的一侧上。前侧互连结构在源极/漏极磊晶结构的一前侧上。背侧通孔件连接至源极/漏极磊晶结构的背侧。隔离材料在背侧通孔件的一侧上且接触栅极结构。侧壁间隔物在背侧通孔件与隔离材料之间。隔离材料的高度大于侧壁间隔物的高度。
根据一些实施方式，半导体装置还包含背侧接触蚀刻终止层，与背侧通孔件的侧壁共形。根据一些实施方式，背侧接触蚀刻终止层接触隔离材料及侧壁间隔物。根据一些实施方式，背侧通孔件包含第一部分及第二部分。第二部分比第一部分宽。第一部分介于第二部分与源极/漏极磊晶结构之间。根据一些实施方式，半导体装置还包含金属合金层，接触背侧通孔件的第一部分及源极/漏极磊晶结构。根据一些实施方式，侧壁间隔物偏移背侧通孔件的第二部分且对准背侧通孔件的第一部分。根据一些实施方式，半导体装置还包含内部间隔物，在栅极结构与背侧通孔件之间。根据一些实施方式，侧壁间隔物接触内部间隔物。根据一些实施方式，隔离材料接触内部间隔物。
根据一些实施方式，一种半导体装置包含多个通道层、栅极结构、第一源极/漏极磊晶结构、内部间隔物、背侧通孔件、侧壁间隔物及隔离材料。通道层以一间隔分开的方式一个配置在另一个上。栅极结构围绕每一通道层。第一源极/漏极磊晶结构在栅极结构的一侧上且连接至通道层。内部间隔物介于栅极结构与第一源极/漏极磊晶结构之间。背侧通孔件连接至第一源极/漏极磊晶结构的背侧。侧壁间隔物接触栅极结构且在背侧通孔件的一侧上。隔离材料在背侧通孔件的该侧上且接触栅极结构及侧壁间隔物。
根据一些实施方式，侧壁间隔物更接触内部间隔物。根据一些实施方式，半导体装置还包含第二源极/漏极磊晶结构，在栅极结构的另一侧上且连接至通道层，且侧壁间隔物更接触第二源极/漏极磊晶结构。根据一些实施方式，半导体装置还包含一第二源极/漏极磊晶结构，在栅极结构的另一侧上且连接至通道层，且隔离材料更接触第二源极/漏极磊晶结构。根据一些实施方式，侧壁间隔物的最上层表面比栅极结构的最底部表面高。根据一些实施方式，半导体装置还包含虚设鳍结构，邻近于栅极结构及第一源极/漏极磊晶结构且与侧壁间隔物间隔分开。
根据一些实施方式，一种制造半导体装置的方法包含在基板中蚀刻凹部。在基板中的凹部中形成牺牲磊晶插塞。在牺牲磊晶插塞上方形成源极/漏极磊晶结构。在源极/漏极磊晶结构的一侧上形成栅极结构。移除基板，使得牺牲磊晶插塞突出于源极/漏极磊晶结构的一背侧。在牺牲磊晶插塞的一侧上形成侧壁间隔物，使得牺牲磊晶插塞的一部分由侧壁间隔物暴露。在由侧壁间隔物暴露的牺牲磊晶插塞的部分上形成牺牲磊晶结构。在牺牲磊晶结构的一侧及侧壁间隔物上形成隔离材料。用背侧通孔件替换牺牲磊晶插塞及牺牲磊晶结构。
根据一些实施方式，上述的方法还包含在蚀刻基板中的凹部之前，形成隔离结构在基板中。根据一些实施方式，形成侧壁间隔物使得侧壁间隔物接触隔离结构。根据一些实施方式，形成侧壁间隔物包含形成毯覆介电层在牺牲磊晶插塞的侧壁上方且与牺牲磊晶插塞的侧壁共形。回蚀毯覆介电层以形成侧壁间隔物。根据一些实施方式，形成隔离材料使得隔离材料与牺牲磊晶插塞间隔分开。
前述内容概述几个实施方式的特征，使得熟悉此项技术者可更好地理解本揭露的态样。熟悉此项技术者应了解，这些技术者可容易将本揭露用作为设计或修改用于实现与本文中介绍的实施方式的相同目的及/或达成与本文中介绍的实施方式的相同优点的其他制程及结构的基础。熟悉此项技术者亦应认识到，这些等效构造不背离本揭露的精神及范畴，且这些技术者可在不离本揭露的精神及范畴的情况下作出本文中的各种改变、取代及改动。

Claims (10)

1.一种半导体装置，其特征在于，包含：
一栅极结构；
一源极/漏极磊晶结构，在该栅极结构的一侧上；
一前侧互连结构，在该源极/漏极磊晶结构的一前侧上；
一背侧通孔件，连接至该源极/漏极磊晶结构的一背侧；
一隔离材料，在该背侧通孔件的一侧上且接触该栅极结构；以及
一侧壁间隔物，在该背侧通孔件与该隔离材料之间，其中该隔离材料的一高度大于该侧壁间隔物的一高度。
2.根据权利要求1所述的半导体装置，其特征在于，该背侧通孔件包含：
一第一部分；以及
一第二部分，比该第一部分宽，其中该第一部分介于该第二部分与该源极/漏极磊晶结构之间。
3.根据权利要求2所述的半导体装置，其特征在于，该侧壁间隔物偏移该背侧通孔件的该第二部分且对准该背侧通孔件的该第一部分。
4.根据权利要求1所述的半导体装置，其特征在于，还包含一内部间隔物，在该栅极结构与该背侧通孔件之间。
5.根据权利要求4所述的半导体装置，其特征在于，该侧壁间隔物接触该内部间隔物。
6.一种半导体装置，其特征在于，包含：
多个通道层，以一间隔分开的方式一个配置在另一个上；
一栅极结构，围绕每一所述通道层；
一第一源极/漏极磊晶结构，在该栅极结构的一侧上且连接至所述多个通道层；
一内部间隔物，在该栅极结构与该第一源极/漏极磊晶结构之间；
一背侧通孔件，连接至该第一源极/漏极磊晶结构的一背侧；
一侧壁间隔物，接触该栅极结构且在该背侧通孔件的一侧上；及
一隔离材料，在该背侧通孔件的该侧上且接触该栅极结构及该侧壁间隔物。
7.根据权利要求6所述的半导体装置，其特征在于，该侧壁间隔物的一最上层表面比该栅极结构的一最底部表面高。
8.根据权利要求6所述的半导体装置，其特征在于，还包含一虚设鳍结构，邻近于该栅极结构及该第一源极/漏极磊晶结构且与该侧壁间隔物间隔分开。
9.一种制造半导体装置的方法，其特征在于，包含：
蚀刻一凹部在一基板中；
形成一牺牲磊晶插塞在该基板中的该凹部中；
形成一源极/漏极磊晶结构在该牺牲磊晶插塞上方；
形成一栅极结构在该源极/漏极磊晶结构的一侧上；
移除该基板，使得该牺牲磊晶插塞突出于该源极/漏极磊晶结构的一背侧；
形成一侧壁间隔物在该牺牲磊晶插塞的一侧上，使得该牺牲磊晶插塞的一部分被该侧壁间隔物暴露；
形成一牺牲磊晶结构在被该侧壁间隔物暴露的该牺牲磊晶插塞的该部分上；
形成一隔离材料在该牺牲磊晶结构的一侧及该侧壁间隔物上；及
用一背侧通孔件替换该牺牲磊晶插塞及该牺牲磊晶结构。
10.根据权利要求9所述的方法，其特征在于，形成该侧壁间隔物包含：
形成一毯覆介电层在该牺牲磊晶插塞的侧壁上方且与该牺牲磊晶插塞的多个侧壁共形；及
回蚀该毯覆介电层以形成该侧壁间隔物。
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