CN113203936A - Chip testing device, system and method - Google Patents
Chip testing device, system and method Download PDFInfo
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- CN113203936A CN113203936A CN202110275945.4A CN202110275945A CN113203936A CN 113203936 A CN113203936 A CN 113203936A CN 202110275945 A CN202110275945 A CN 202110275945A CN 113203936 A CN113203936 A CN 113203936A
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- 238000004806 packaging method and process Methods 0.000 claims description 20
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
Abstract
The invention provides a chip testing device, a system and a method for testing a chip, wherein the chip testing device comprises a testing base and a testing circuit; the test base is provided with a groove for fixing a packaged chip to be tested, the edge of the groove comprises a multi-step structure, the multi-step structure enables the groove to fix packaged chips to be tested with different sizes, and a group of conductive contacts are arranged on each of a plurality of step table tops with different heights of the multi-step structure; each group of conductive contacts comprises a first conductive contact and a second conductive contact, the first conductive contact and the second conductive contact are respectively electrically connected with the test circuit, the test circuit is used for sending a test input signal to the packaged chip to be tested through the first conductive contact, obtaining a test output signal of the packaged chip to be tested through the second conductive contact, and judging whether the packaged chip to be tested is abnormal or not according to the test output signal. The chip testing device provided by the invention can be compatible with the test of packaged chips with different sizes.
Description
Technical Field
The invention relates to the technical field of chips, in particular to a chip testing device, a chip testing system and a chip testing method.
Background
At present, the integrated circuit chip industry is rapidly developed, the chip yield is increasingly increased, in the integrated circuit chip production process, the chip testing is a very important step, after the chip packaging is completed, the chip packaging is generally required to be subjected to FT (Final Test) testing to ensure the outgoing quality of the chip, however, the current chip testing device is poor in universality, and different chip testing devices are required to be adopted for packaged chips with different sizes.
Disclosure of Invention
Based on the above situation, the present invention is directed to a chip testing apparatus, a chip testing system and a chip testing method, which are compatible with testing of packaged chips with different sizes.
In order to achieve the above object, the technical solution of the present invention provides a chip testing apparatus, which includes a testing base and a testing circuit;
the test base is provided with a groove for fixing a packaged chip to be tested, the edge of the groove comprises a multi-step structure, the multi-step structure enables the groove to fix packaged chips to be tested with different sizes, a group of conductive contacts are respectively arranged on a plurality of step table tops with different heights of the multi-step structure, and the different groups of conductive contacts are used for being in electric contact with pins of the packaged chips to be tested with different sizes;
each group of conductive contacts comprises a first conductive contact and a second conductive contact, the first conductive contact and the second conductive contact are respectively electrically connected with the test circuit, the test circuit is used for sending a test input signal to a packaged chip to be tested through the first conductive contact, obtaining a test output signal of the packaged chip to be tested through the second conductive contact, and judging whether the packaged chip to be tested is abnormal or not according to the test output signal.
Furthermore, the chip testing device also comprises image acquisition equipment and a mechanical arm, wherein the image acquisition equipment and the mechanical arm are respectively connected with the testing circuit;
the image acquisition equipment is used for acquiring images of the test base;
the test circuit is also used for identifying a positioning pattern on the packaging chip to be tested in the image acquired by the image acquisition equipment, judging whether the placing position of the packaging chip to be tested on the test base deviates or not according to the identified positioning pattern, and controlling the mechanical arm to adjust the placing position of the packaging chip to be tested if the placing position deviation of the packaging chip to be tested is judged.
Furthermore, the test circuit comprises a main control chip and a memory arranged outside the main control chip;
the memory is used for acquiring and storing the test program and the test case file from the external equipment;
the main control chip is connected with the memory and the first conductive contact and used for reading the test program and the test case file from the memory and sending the test program and the test case file to the packaging chip to be tested through the first conductive contact;
the main control chip is further used for judging whether the packaged chip to be tested is abnormal or not according to the test output signal output by the packaged chip to be tested at the second conductive contact.
Furthermore, an internal memory of the main control chip comprises a first partition and a second partition, the first partition is used for storing and operating a chip test control program, the second partition is used for storing an upgrade file of the chip test control program, and the chip test control program is used for realizing test control on the packaged chip to be tested;
the master control chip is configured with: and reading an address mark of the internal memory when the main control chip is powered on, and carrying the upgrade file of the second partition to the first partition if the upgrade mark is read.
Furthermore, the chip testing device further comprises an alarm module connected with the main control chip, and the main control chip is further used for controlling the alarm module to execute alarm operation if the packaged chip to be tested is judged to be abnormal.
Furthermore, the alarm module comprises an acousto-optic alarm module, a short message alarm module and a call alarm module;
the master control chip is configured with: when the packaged chip to be tested is judged to be abnormal, the sound and light alarm module is controlled to execute sound and light alarm operation, if the response information of the sound and light alarm operation is not received within first preset time, the short message alarm module is controlled to execute short message alarm operation, and if the response information of the short message alarm operation is not received within second preset time, the call alarm module is controlled to execute call alarm operation.
Further, the memory comprises a pluggable memory.
Furthermore, the chip testing device further comprises a network communication module connected with the main control chip, and the main control chip is further used for sending the abnormal judgment result of the packaged chip to be tested to the cloud server through the network communication module.
Furthermore, the chip testing device further comprises an infrared sensor connected with the main control chip, and the main control chip is further used for judging whether the packaging chip to be tested is placed on the testing base or not according to an output signal of the infrared sensor.
Furthermore, the test base and the test circuit are arranged on a test base plate, an electric connection structure is arranged at the position of the test base corresponding to the conductive contact, and the electric connection structure penetrates through the test base plate in the direction perpendicular to the test base plate, so that the conductive contact is electrically connected with the test circuit.
In order to achieve the above object, the technical solution of the present invention further provides a chip testing system, which includes a cloud server and the above chip testing apparatus;
and the cloud server is used for acquiring and storing the test result of the packaged chip to be tested from the chip test device.
In order to achieve the above object, the technical solution of the present invention further provides a method for testing a chip by using the chip testing apparatus, where the method includes:
step S1: placing the packaged chip to be tested on a step table surface with the corresponding height of the multi-step structure according to the size of the packaged chip to be tested, so that the packaged chip to be tested is fixed and pins of the packaged chip to be tested are in electric contact with a corresponding group of conductive contacts on the multi-step structure;
step S2: the test circuit sends a test input signal to the packaged chip to be tested through a first conductive contact in the corresponding group of conductive contacts, wherein the test input signal comprises a test program and a test case file;
step S3: and the test circuit acquires the test output signal of the packaged chip to be tested through the second conductive contact in the corresponding group of conductive contacts, and judges whether the packaged chip to be tested is abnormal or not according to the test output signal.
Further, before step S2, the method further includes:
and the test circuit judges whether the test base is provided with the packaged chip to be tested or not, and if not, the test circuit controls the mechanical arm to load the packaged chip to be tested on the test base.
Further, before step S2, the method further includes:
the test circuit controls the image acquisition equipment to acquire images of the test base;
the test circuit identifies a positioning pattern on the packaged chip to be tested in the image acquired by the image acquisition equipment, and judges whether the placement position of the packaged chip to be tested on the test base deviates or not according to the identified positioning pattern;
and if the placement position of the packaged chip to be tested deviates, the test circuit controls the mechanical arm to adjust the placement position of the packaged chip to be tested.
Further, the step S3 further includes:
if the packaged chip to be tested is judged to be abnormal, the test circuit controls the sound-light alarm module to execute sound-light alarm operation;
if the response information of the sound-light alarm operation is not received within a first preset time, the test circuit controls the short message alarm module to execute the short message alarm operation;
and if the response information of the short message alarm operation is not received within second preset time, the test circuit controls the call alarm module to execute the call alarm operation.
Further, the step S3 further includes:
and the test circuit sends the abnormal judgment result of the packaged chip to be tested to the cloud server.
The chip testing device provided by the invention comprises a testing base, wherein the testing base is provided with a groove for fixing a packaged chip to be tested, the edge of the groove comprises a multi-step structure, the packaged chips to be tested with different sizes can be fixed through the testing base, a group of conductive contacts are respectively arranged on a plurality of step table tops with different heights of the multi-step structure, when the packaged chip to be tested is fixed on the testing base, pins of the packaged chip to be tested can be in electric contact with the corresponding conductive contacts on the testing base, and then the packaged chip to be tested is electrically connected to a testing circuit, so that the testing circuit can send a testing input signal to the packaged chip to be tested and obtain a testing output signal of the packaged chip to be tested, and the chip testing device provided by the invention can be compatible with the testing of the packaged chips with different sizes.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 is a top view of a test base provided in accordance with an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of a test base provided in an embodiment of the present invention;
fig. 3 is a schematic diagram of a chip testing apparatus and a cloud server according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating a position of a packaged chip to be tested on a test base according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a partition of an internal memory in a main control chip according to an embodiment of the present invention.
Detailed Description
The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in order to avoid obscuring the nature of the present invention, well-known methods, procedures, and components have not been described in detail.
Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.
Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".
In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.
It should be noted that step numbers (letter or number numbers) are used to refer to some specific method steps in the present invention only for the purpose of convenience and brevity of description, and the order of the method steps is not limited by letters or numbers in any way. It will be clear to a person skilled in the art that the order of the steps of the method in question, as determined by the technology itself, should not be unduly limited by the presence of step numbers.
The embodiment of the invention provides a chip testing device, which comprises a testing base and a testing circuit, wherein the testing base is provided with a testing circuit;
the test base is provided with a groove for fixing a packaged chip to be tested, the edge of the groove comprises a multi-step structure, the multi-step structure enables the groove to fix packaged chips to be tested with different sizes, a plurality of step table tops with different heights of the multi-step structure are respectively provided with a group of conductive contacts, the different groups of conductive contacts are used for being in electrical contact with pins of the packaged chips to be tested with different sizes, and each group of conductive contacts is respectively used for being in electrical contact with the pin of the packaged chip to be tested with one size;
each group of conductive contacts comprises a first conductive contact and a second conductive contact, the first conductive contact and the second conductive contact are respectively electrically connected with the test circuit, the test circuit is used for sending a test input signal to a packaged chip to be tested through the first conductive contact, obtaining a test output signal of the packaged chip to be tested through the second conductive contact, and judging whether the packaged chip to be tested is abnormal or not according to the test output signal.
The chip testing device provided by the embodiment of the invention comprises a testing base, wherein the testing base is provided with a groove for fixing a packaged chip to be tested, the edge of the groove comprises a multi-step structure, the packaged chips to be tested with different sizes can be fixed through the testing base, a group of conductive contacts are respectively arranged on a plurality of step table tops with different heights of the multi-step structure, when the packaged chip to be tested is fixed on the testing base, pins of the packaged chip to be tested can be in electric contact with the corresponding conductive contacts on the testing base, and then the packaged chip to be tested is electrically connected to a testing circuit, so that the testing circuit can send a testing input signal to the packaged chip to be tested and obtain a testing output signal of the packaged chip to be tested, and the chip testing device provided by the invention can be compatible with the testing of the packaged chips with different sizes.
Compared with the mode that a plurality of grooves with different sizes are respectively arranged on the test base and each groove with different sizes is respectively used for fixing a chip with one size, the mode can realize the test of the chips with different sizes through one groove, the required number of the grooves can be greatly reduced, and the size of the chip test device can be effectively reduced.
According to the chip testing device provided by the embodiment of the invention, the edge of the groove on the testing base is set to be of the multi-step structure, so that fixing spaces with different sizes are formed in the same groove, the fixing spaces with different sizes are matched with the packaged chips to be tested with different sizes, the packaged chips to be tested are prevented from moving in the horizontal direction during testing, and poor electric contact is avoided.
For example, referring to fig. 1, fig. 1 is a schematic view of a test base provided in an embodiment of the present invention, a groove for fixing a packaged chip to be tested is provided on the test base 100, an edge of the groove includes a multi-step structure including a plurality of step lands 104, 105, and 106 with different heights, the step land 104 is a bottom surface of the groove and is a step land with a lowest height, three fixing spaces with different sizes are formed through the multi-step structure, and include a fixing space with a size of H1 × L1, a fixing space with a size of H2 × L2, and a fixing space with a size of H3 × L3, so that packaged chips with three different sizes can be compatible.
The fixed space with the size of H1 xL 1 is used for fixing a packaged chip to be tested with the size slightly smaller than H1 xL 1, the packaged chip to be tested with the size is supported by the step table 104, the fixed space with the size of H2 xL 2 is used for fixing a packaged chip to be tested with the size slightly smaller than H2 xL 2, the packaged chip to be tested with the size is supported by the step table 105, the fixed space with the size of H3 xL 3 is used for fixing a packaged chip to be tested with the size slightly smaller than H3 xL 3, and the packaged chip to be tested with the size is supported by the step table 106;
a first group of conductive contacts including a plurality of conductive contacts 101 including a plurality of first conductive contacts and a plurality of second conductive contacts are arranged on the step table 104, and the group of conductive contacts is used for electrically contacting pins of a packaged chip to be tested with the size being slightly smaller than H1 xL 1;
a second group of conductive contacts is arranged on the step table 105, and comprises a plurality of conductive contacts 102, wherein the plurality of conductive contacts comprises a plurality of first conductive contacts and a plurality of second conductive contacts, and the group of conductive contacts is used for electrically contacting pins of a packaged chip to be tested, the size of which is slightly smaller than H2 xL 2;
a third group of conductive contacts is arranged on the step table 106, and comprises a plurality of conductive contacts 103, wherein the plurality of conductive contacts comprise a plurality of first conductive contacts and a plurality of second conductive contacts, and the group of conductive contacts is used for electrically contacting pins of a packaged chip to be tested, the size of which is slightly smaller than H3 xL 3;
in the embodiment of the present invention, the number of each set of conductive contacts and the layout manner on the step mesa may be determined by the pin layout manner of the fixed packaged chip to be tested, which is not particularly limited in the present invention.
In the embodiment of the invention, the sizes and the pin information of various packaged chips to be tested can be collected in advance, so that the specific information of the groove, the multi-step structure and the conductive contact on the test base can be determined, and the compatibility with different packaged chips can be realized.
For each group of conductive contacts, a first conductive contact and a second conductive contact are respectively electrically connected with the test circuit, the test circuit sends a test input signal to the packaged chip to be tested through the first conductive contact, obtains a test output signal of the packaged chip to be tested through the second conductive contact, and judges whether the packaged chip to be tested is abnormal or not according to the test output signal;
wherein the number of the first conductive contacts and the number of the second conductive contacts in each group of conductive contacts can be determined by the packaged chip to be tested.
For example, in an embodiment, the test base and the test circuit of the chip testing apparatus are disposed on a test substrate, and the test base is disposed with an electrical connection structure corresponding to the conductive contact, and the electrical connection structure penetrates through the test base in a direction perpendicular to the test substrate, so as to achieve electrical connection between the conductive contact and the test circuit, where the test base may be a PCB.
For example, referring to FIG. 2, for each conductive contact, it is connected to the printed circuit on the test base 300, and thus to the test circuitry, by an electrical connection structure 110 that extends through the test base 100.
For example, referring to fig. 3, the chip testing apparatus provided in the embodiment of the present invention includes a testing substrate 300, the testing substrate 300 is provided with a testing base 100 and a testing circuit, the testing base 100 is provided with a groove for fixing a packaged chip 11 to be tested, and the edge of the groove includes a multi-step structure, the multi-step structure enables the groove to fix packaged chips to be tested with different sizes, and the testing base 100 may adopt the structure shown in fig. 1 and fig. 2;
the test circuit includes a main control chip 210 and a memory 220 disposed outside the main control chip 210;
the Memory 220 is used for acquiring and storing the test program and the test case file from an external device, for example, the external device may be an upper computer, the Memory 220 may be a pluggable Memory, for example, an SD Card (Secure Digital Memory Card), and a corresponding SD Card slot is arranged on the test bottom board 300;
the main control chip 210 is connected with the memory 220 and a first conductive contact in each group of conductive contacts, and the main control chip 210 is used for reading the test program and the test case file from the memory 220 and sending the test program and the test case file to the packaged chip to be tested through the first conductive contact;
the main control chip 210 is further configured to determine whether the packaged chip to be tested is abnormal according to a test output signal output by the packaged chip to be tested at the second conductive contact;
for example, in an embodiment, the second conductive contact may be connected to the main control chip 210, the main control chip 210 may determine whether the packaged chip to be tested is abnormal according to a test output signal on the second conductive contact, in another embodiment, the second conductive contact may also be connected to a FLASH memory in the test circuit, the test output signal of the packaged chip to be tested may be output to the FLASH memory first, the main control chip may analyze and process data in the FLASH memory to determine whether the chip is abnormal, for example, when a QSPI module of the chip is tested, a QSPI pin of the packaged chip to be tested is connected to a FLASH memory through the second conductive contact, and the main control chip sends a test command to the packaged chip to be tested to achieve a test function.
Preferably, the main control chip 210 may have a wear leveling function, which may implement wear leveling control of the SD card, and help to prolong the service life of the memory.
Preferably, in an embodiment, the chip testing apparatus further includes an image capturing device 410 and a robot arm 420, wherein the image capturing device 410 and the robot arm 420 are respectively connected to the testing circuit;
the image acquisition device 410 is configured to acquire an image of the test socket 100, where the image acquisition device may include a camera, and may monitor a position of a packaged chip to be tested in real time;
the test circuit is also used for identifying the positioning pattern on the to-be-tested packaging chip in the image collected by the image collecting equipment 410, judging whether the placing position of the to-be-tested packaging chip on the test base deviates or not according to the identified positioning pattern, and controlling the mechanical arm to adjust the placing position of the to-be-tested packaging chip if the placing position deviation of the to-be-tested packaging chip is judged, and the mechanical arm 420 can adopt a full-automatic intelligent mechanical arm and can adjust the position of the to-be-tested packaging chip.
For example, the image capturing device 410 and the mechanical arm 420 are disposed on a testing machine 400, a communication interface 250 connected to the testing machine 400 is provided on the testing base plate 300 to implement communication connection between the image capturing device 410 and the mechanical arm 420 and the main control chip 210 in the testing circuit, the main control chip 210 can analyze and process the image captured by the image capturing device 410, determine whether the placement position of the to-be-tested packaged chip is shifted by using the positioning pattern on the packaged chip, and control the mechanical arm to adjust the position of the to-be-tested packaged chip.
For example, the positioning pattern on the packaged chip to be tested may include a plurality of positioning points with different sizes and/or shapes;
for example, referring to fig. 4, the positioning pattern on the package chip 11 to be tested includes three positioning points 12, 13, and 14 with different sizes, and the main control chip 210 can determine whether the placement position of the package chip 11 to be tested is shifted by identifying the positions of the three positioning points in the image acquired by the image acquisition device 410, as shown in fig. 4, when the main control chip 210 identifies the positions of the three positioning points as (a), the main control chip 210 determines that the placement position of the package chip 11 to be tested is correct, and when the main control chip 210 identifies the positions of the three positioning points as (b), (c), or (d), the main control chip 210 determines that the placement position of the package chip 11 to be tested is shifted.
Preferably, in this embodiment, the chip testing apparatus further includes an alarm module 230 connected to the main control chip 210, and the main control chip 210 is further configured to control the alarm module 230 to execute an alarm operation if it is determined that the packaged chip to be tested is abnormal, so that a user can know a test result in time and perform a next processing in time.
For example, in one embodiment, the alarm module 230 may include an audio-visual alarm module, a short message alarm module, and a call alarm module;
the master control chip 210 is configured with: when the packaged chip to be tested is judged to be abnormal, the sound and light alarm module is controlled to execute sound and light alarm operation, if the response information of the sound and light alarm operation is not received within first preset time, the short message alarm module is controlled to execute short message alarm operation, and if the response information of the short message alarm operation is not received within second preset time, the call alarm module is controlled to execute call alarm operation.
The sound and light alarm module can comprise a buzzer and a multi-color lamp, and the short message alarm module and the call alarm module can be realized through a GPRS module;
after the main control chip 210 receives the abnormal information output by the packaged chip to be tested, it determines that the packaged chip to be tested is abnormal, and executes the following alarm operations:
1. triggering sound and light alarm. The main control chip 210 can control the operation of the buzzer and the multi-color lamps by pulling up the I/O level, wherein if the system maintainer presses down the alarm key within three minutes of audible and visual alarm, the main control chip 210 detects the low level (response information of audible and visual alarm operation), and the audible and visual alarm stops; if no response is given after the acousto-optic alarm is carried out for three minutes, triggering short message reminding, and continuing the acousto-optic alarm;
2. and (5) short message notification and alarm. The main control chip 210 can control the GPRS module to send a reminding short message to a preset telephone number through a serial port AT instruction, so as to implement a short message alarm operation. If the main control chip 310 receives the response message (the response message of the short message alarm operation, if the short message is received) within two minutes, the alarm module stops running; if no response exists after two minutes after the short message is reminded, triggering a call alarm operation, and continuing the acousto-optic alarm;
3. and the telephone informs the alarm. The main control chip 210 can control the GPRS module to make a call to a preset telephone number through a serial port AT instruction, so as to implement a call alarm operation, and if the call is connected, the alarm module stops running; if the phone does not respond, the main control chip 210 controls the GPRS module to make a call again through the serial port AT instruction, the call is stopped when three times of calls are made continuously without responses, the sound and light alarm continues to work, and the main control chip 210 closes the GPRS module.
In an embodiment, a peripheral interface may be further provided on the test backplane 300 to provide access to a handheld device having a display screen, and a user may connect the handheld device to the peripheral interface, and when the main control chip 210 detects the access of the handheld device through the peripheral interface, fault information may be output to the handheld device through a specific protocol, thereby facilitating the user to implement quick troubleshooting after learning to alarm.
Preferably, in an embodiment, the chip testing apparatus further includes a network communication module 240 connected to the main control chip 210, and the main control chip 210 is further configured to send an abnormal judgment result of the packaged chip to be tested to the cloud server 500 through the network communication module 240, where the network communication module may include an ethernet interface and/or a wireless communication module.
For example, the test result of the chip testing device can be uploaded to the cloud server in an information encryption mode, and a user can conveniently inquire the test result through the cloud server at any time and any place. The test result of the chip testing device may include information such as the test time, the name of the packaged chip to be tested, and the abnormality determination result of the packaged chip to be tested.
Preferably, in an embodiment, the chip testing apparatus further includes an infrared sensor connected to the main control chip, and the main control chip is further configured to determine whether a package chip to be tested is placed on the test base according to an output signal of the infrared sensor, that is, the main control chip 210 may detect whether the package chip to be tested is placed on the test base 100 through the infrared sensor, where if the package chip to be tested is not detected, the main control chip 210 may send control information to the test machine 400, and control the mechanical arm 420 on the test machine 400 to load the package chip to be tested on the test base 100;
in addition, a peripheral circuit 260 is further disposed on the test board, and the peripheral circuit 260 may include a power supply circuit for supplying power to modules such as the test base and the main control chip, and may further include a protection circuit such as a voltage and current detection module.
Preferably, in an embodiment, an internal memory of the main control chip 210 includes a first partition and a second partition, where the first partition is used to store and run a chip test control program, the second partition is used to store an upgrade file of the chip test control program, and the chip test control program is used to implement test control on a packaged chip to be tested;
the master control chip 210 is configured with: and reading an address mark of the internal memory when the main control chip is powered on, and carrying the upgrade file of the second partition to the first partition if the upgrade mark is read.
The second partition is added in the internal memory of the main control chip, and the upgrading packet of the chip test control program is stored in the second partition, so that the situation that the main control chip cannot work due to the fact that the chip test control program is abnormal in the upgrading process and the running program is erased before upgrading can be avoided.
For example, referring to fig. 5, an internal flash memory of the main control chip 210 includes three partitions, which are a Boot area, an APP area (i.e., a first partition) and a Backup area (i.e., a second partition), where the Boot area is used to run a Boot program of the main control chip, the APP area is used to store and run a chip test control program, and the Backup area is used to store an upgrade file (upgrade package) of the chip test control program.
The test control program can realize test operation control and alarm control, when the main control chip needs to be upgraded later, the test bottom plate can be connected with an upper computer, an upgrade package of the test control program of the chip is issued to the main control chip through the upper computer, after the test bottom plate receives the upgrade package, the main control chip verifies all data in the upgrade package, a check value in the upgrade package is read, the main control chip calculates the data in the upgrade package to obtain a CRC value, the CRC value is compared with the check value to judge whether the CRC value is consistent, if so, the upgrade package is complete, and an address mark of an internal flash memory is changed into an upgrade mark from a normal mark; if the data are inconsistent, the main control chip sends the upgrade packet data abnormal information to the upper computer, so that the upper computer sends the upgrade packet again after receiving the information;
when the test bottom board powers on the main control chip, the main control chip firstly runs a starting program of the chip in a Boot area, the starting program reads an address mark of an internal flash memory, if a default value is read out, the starting is represented as the first starting, the test control program is triggered to run in an APP area, and the main control chip starts to execute the self-checking operation of the chip test device; if the normal mark is read out, the chip test control program does not need to be upgraded, the test control program is triggered to run in the APP area, and the main control chip starts to execute the self-checking operation of the chip test device; if the upgrading mark is read, the main control chip carries the upgrading packet in the backup area to the APP area to complete the upgrading of the chip test control program, wherein if the data is carried wrongly in the carrying process, the upgrading packet can be carried once again.
After the upgrade is finished, the main control chip changes the address mark from the upgrade mark to a normal mark, and restarts the test bottom plate, and the main control chip enters a self-checking stage after detecting the normal mark;
the main control chip enters a self-checking stage after reading that the address mark is a default value or a normal mark, and executes self-checking operation of the chip testing device, specifically, the main control chip can acquire information of each module (such as a voltage and current detection module, a network communication module, an SD card, a GPRS module and the like) in the chip testing device and judge whether the information is normal or not, if the information is normal, the self-checking is finished, the chip testing device can enter the chip testing stage, and if the main control chip acquires abnormal information, a chip testing control program stops running and triggers an alarm module to alarm;
in addition, before the chip is tested, the test program and the test case file of the chip are written, the testing of the chip is completed through the matching of the testing program of the chip and the chip testing control program in the main control chip, for example, firstly, the SD card is connected with an upper computer, inputting configuration parameters of each module of the packaged chip to be tested on an upper computer test software interface, automatically generating a test case file by the test software according to the configuration parameters, then the test case file is saved in the SD card, and then the written test program is saved in the SD card, the test program is used for running in the packaged chip to be tested, completing the test by matching with the chip test control program in the main control chip, then installing the SD card on the test base plate, and the testing bottom plate is placed on the testing machine platform, and the testing bottom plate is connected with the communication interface of the testing machine platform, so that the testing of the chip can be started, wherein the testing process is as follows:
s101: the main control chip detects whether the packaged chip to be tested is on the test base or not through the output signal of the infrared sensor;
if the packaged chip to be tested is not detected, the main control chip sends control information to the testing machine table to control the mechanical arm on the testing machine table to load the packaged chip to be tested, wherein the main control chip can control the mechanical arm according to the size of the packaged chip to be tested and place the packaged chip to be tested on a step table top with the corresponding height of the multi-step structure;
if the packaged chip to be tested is detected, monitoring the position of the packaged chip to be tested through three positioning points on the packaged chip by using a camera on a testing machine table, if the position deviation of the chip is monitored, controlling a mechanical arm on the testing machine table to adjust the position of the chip by using a main control chip, if the chip does not deviate, reading a testing program from an SD card by using the main control chip, writing the testing program into the packaged chip to be tested, and resetting the packaged chip to be tested;
s102, after the packaged chip to be tested is reset, the packaged chip to be tested firstly detects whether the reading and writing of the register are normal. If the information is normal, feeding back normal information of the main control chip, and performing the next step S103; if the chip is abnormal, feeding back abnormal information of the main control chip, and controlling a mechanical arm on a test machine platform by the main control chip to place the packaged chip to be tested in an abnormal area;
s103, the main control chip reads the test case file from the SD card and sends the test case file to the packaged chip to be tested;
s104: the packaged chip to be tested configures the register information of the module to be tested according to the configuration information in the test case file, and configuration completion information can be fed back to the main control chip after configuration is completed;
s105, the main control chip sends a corresponding instruction to the to-be-tested packaging chip after receiving the configuration completion information of the to-be-tested packaging chip, and starts testing;
in the testing process, if the main control chip detects abnormal information output by the packaged chip to be tested, the alarm module is triggered to alarm;
and S106, the main control chip collects the chip test result, encrypts the test result and uploads the encrypted test result to the cloud server through the network communication module. If the network communication is abnormal, the test result can be encrypted and then temporarily stored in the local SD card, and after the network is recovered, the test result is uploaded to the cloud server.
S107, the main control chip eliminates the test program in the packaged chip to be tested.
And S108, the main control chip controls the test machine, the test machine takes the tested chip out of the test base through the mechanical arm, a new packaged chip to be tested is replaced, and the process is repeated until the chips are completely tested.
The chip testing device provided by the embodiment of the invention can solve the problem that the packaged chips with different sizes cannot be compatible in the chip FT (final test) testing process in the prior art, the testing base in the chip testing device can be compatible with the packaged chips with different sizes, the FT testing of the packaged chips with different sizes can be realized by only one set of testing system, and the chip FT testing efficiency is greatly improved.
The embodiment of the invention also provides a chip testing system which comprises the cloud server and the chip testing device;
and the cloud server is used for acquiring and storing the test result of the packaged chip to be tested from the chip test device.
The embodiment of the invention also provides a method for testing a chip by using the chip testing device, which comprises the following steps:
step S1: placing the packaged chip to be tested on a step table surface with the corresponding height of the multi-step structure according to the size of the packaged chip to be tested, so that the packaged chip to be tested is fixed and pins of the packaged chip to be tested are in electric contact with a corresponding group of conductive contacts on the multi-step structure;
step S2: the test circuit sends a test input signal to the packaged chip to be tested through a first conductive contact in the corresponding group of conductive contacts, wherein the test input signal comprises a test program and a test case file;
step S3: and the test circuit acquires the test output signal of the packaged chip to be tested through the second conductive contact in the corresponding group of conductive contacts, and judges whether the packaged chip to be tested is abnormal or not according to the test output signal.
In an embodiment, before step S2, the method further includes:
and the test circuit judges whether the test base is provided with the packaged chip to be tested or not, and if not, the test circuit controls the mechanical arm to load the packaged chip to be tested on the test base.
In an embodiment, before step S2, the method further includes:
the test circuit controls the image acquisition equipment to acquire images of the test base;
the test circuit identifies a positioning pattern on the packaged chip to be tested in the image acquired by the image acquisition equipment, and judges whether the placement position of the packaged chip to be tested on the test base deviates or not according to the identified positioning pattern;
and if the placement position of the packaged chip to be tested deviates, the test circuit controls the mechanical arm to adjust the placement position of the packaged chip to be tested.
In one embodiment, the step S3 further includes:
if the packaged chip to be tested is judged to be abnormal, the test circuit controls the sound-light alarm module to execute sound-light alarm operation;
if the response information of the sound-light alarm operation is not received within a first preset time, the test circuit controls the short message alarm module to execute the short message alarm operation;
and if the response information of the short message alarm operation is not received within second preset time, the test circuit controls the call alarm module to execute the call alarm operation.
In one embodiment, the step S3 further includes:
and the test circuit sends the abnormal judgment result of the packaged chip to be tested to the cloud server.
It will be appreciated by those skilled in the art that the above-described preferred embodiments may be freely combined, superimposed, without conflict.
It will be understood that the embodiments described above are illustrative only and not restrictive, and that various obvious and equivalent modifications and substitutions for details described herein may be made by those skilled in the art without departing from the basic principles of the invention.
Claims (16)
1. A chip testing device is characterized by comprising a testing base and a testing circuit;
the test base is provided with a groove for fixing a packaged chip to be tested, the edge of the groove comprises a multi-step structure, the multi-step structure enables the groove to fix packaged chips to be tested with different sizes, a group of conductive contacts are respectively arranged on a plurality of step table tops with different heights of the multi-step structure, and the different groups of conductive contacts are used for being in electric contact with pins of the packaged chips to be tested with different sizes;
each group of conductive contacts comprises a first conductive contact and a second conductive contact, the first conductive contact and the second conductive contact are respectively electrically connected with the test circuit, the test circuit is used for sending a test input signal to a packaged chip to be tested through the first conductive contact, obtaining a test output signal of the packaged chip to be tested through the second conductive contact, and judging whether the packaged chip to be tested is abnormal or not according to the test output signal.
2. The chip testing device according to claim 1, further comprising an image acquisition device and a mechanical arm, wherein the image acquisition device and the mechanical arm are respectively connected with the testing circuit;
the image acquisition equipment is used for acquiring images of the test base;
the test circuit is also used for identifying a positioning pattern on the packaging chip to be tested in the image acquired by the image acquisition equipment, judging whether the placing position of the packaging chip to be tested on the test base deviates or not according to the identified positioning pattern, and controlling the mechanical arm to adjust the placing position of the packaging chip to be tested if the placing position deviation of the packaging chip to be tested is judged.
3. The chip testing device according to claim 1, wherein the testing circuit comprises a main control chip and a memory disposed outside the main control chip;
the memory is used for acquiring and storing the test program and the test case file from the external equipment;
the main control chip is connected with the memory and the first conductive contact and used for reading the test program and the test case file from the memory and sending the test program and the test case file to the packaging chip to be tested through the first conductive contact;
the main control chip is further used for judging whether the packaged chip to be tested is abnormal or not according to the test output signal output by the packaged chip to be tested at the second conductive contact.
4. The chip testing device according to claim 3, wherein an internal memory of the main control chip includes a first partition and a second partition, the first partition is used for storing and running a chip testing control program, the second partition is used for storing an upgrade file of the chip testing control program, and the chip testing control program is used for realizing testing control of a packaged chip to be tested;
the master control chip is configured with: and reading an address mark of the internal memory when the main control chip is powered on, and carrying the upgrade file of the second partition to the first partition if the upgrade mark is read.
5. The chip testing device according to claim 3, further comprising an alarm module connected to the main control chip, wherein the main control chip is further configured to control the alarm module to perform an alarm operation if it is determined that the packaged chip to be tested is abnormal.
6. The chip testing device according to claim 5, wherein the alarm module comprises an acousto-optic alarm module, a short message alarm module and a call alarm module;
the master control chip is configured with: when the packaged chip to be tested is judged to be abnormal, the sound and light alarm module is controlled to execute sound and light alarm operation, if the response information of the sound and light alarm operation is not received within first preset time, the short message alarm module is controlled to execute short message alarm operation, and if the response information of the short message alarm operation is not received within second preset time, the call alarm module is controlled to execute call alarm operation.
7. The chip test apparatus according to claim 3, wherein the memory comprises a pluggable memory.
8. The chip testing device according to claim 3, further comprising a network communication module connected to the main control chip, wherein the main control chip is further configured to send an abnormality determination result of the packaged chip to be tested to a cloud server through the network communication module.
9. The chip testing device according to claim 3, further comprising an infrared sensor connected to the main control chip, wherein the main control chip is further configured to determine whether a packaged chip to be tested is placed on the testing base according to an output signal of the infrared sensor.
10. The chip testing device according to any one of claims 1 to 9, wherein the testing base and the testing circuit are disposed on a testing substrate, and the testing base is provided with an electrical connection structure corresponding to the position of the conductive contact, and the electrical connection structure penetrates through the testing base in a direction perpendicular to the testing substrate, so as to electrically connect the conductive contact and the testing circuit.
11. A chip testing system comprising a cloud server and the chip testing apparatus according to any one of claims 1 to 10;
and the cloud server is used for acquiring and storing the test result of the packaged chip to be tested from the chip test device.
12. A method for chip testing using the chip testing apparatus according to any one of claims 1 to 10, the method comprising:
step S1: placing the packaged chip to be tested on a step table surface with the corresponding height of the multi-step structure according to the size of the packaged chip to be tested, so that the packaged chip to be tested is fixed and pins of the packaged chip to be tested are in electric contact with a corresponding group of conductive contacts on the multi-step structure;
step S2: the test circuit sends a test input signal to the packaged chip to be tested through a first conductive contact in the corresponding group of conductive contacts, wherein the test input signal comprises a test program and a test case file;
step S3: and the test circuit acquires the test output signal of the packaged chip to be tested through the second conductive contact in the corresponding group of conductive contacts, and judges whether the packaged chip to be tested is abnormal or not according to the test output signal.
13. The chip testing method according to claim 12, wherein before step S2, the method further comprises:
and the test circuit judges whether the test base is provided with the packaged chip to be tested or not, and if not, the test circuit controls the mechanical arm to load the packaged chip to be tested on the test base.
14. The chip testing method according to claim 12, wherein before step S2, the method further comprises:
the test circuit controls the image acquisition equipment to acquire images of the test base;
the test circuit identifies a positioning pattern on the packaged chip to be tested in the image acquired by the image acquisition equipment, and judges whether the placement position of the packaged chip to be tested on the test base deviates or not according to the identified positioning pattern;
and if the placement position of the packaged chip to be tested deviates, the test circuit controls the mechanical arm to adjust the placement position of the packaged chip to be tested.
15. The chip testing method according to claim 12, wherein the step S3 further comprises:
if the packaged chip to be tested is judged to be abnormal, the test circuit controls the sound-light alarm module to execute sound-light alarm operation;
if the response information of the sound-light alarm operation is not received within a first preset time, the test circuit controls the short message alarm module to execute the short message alarm operation;
and if the response information of the short message alarm operation is not received within second preset time, the test circuit controls the call alarm module to execute the call alarm operation.
16. The chip testing method according to claim 12, wherein the step S3 further comprises:
and the test circuit sends the abnormal judgment result of the packaged chip to be tested to the cloud server.
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