CN113192896A - Chip packaging structure and manufacturing method thereof - Google Patents

Chip packaging structure and manufacturing method thereof Download PDF

Info

Publication number
CN113192896A
CN113192896A CN202010038806.5A CN202010038806A CN113192896A CN 113192896 A CN113192896 A CN 113192896A CN 202010038806 A CN202010038806 A CN 202010038806A CN 113192896 A CN113192896 A CN 113192896A
Authority
CN
China
Prior art keywords
layer
chip
metal layer
patterned photoresist
patterned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010038806.5A
Other languages
Chinese (zh)
Inventor
何崇文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to CN202010038806.5A priority Critical patent/CN113192896A/en
Publication of CN113192896A publication Critical patent/CN113192896A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

The invention provides a chip packaging structure and a manufacturing method thereof. The manufacturing method of the chip packaging structure comprises the following steps. Providing a carrier plate which is provided with a containing groove and comprises a base material and a stainless steel layer sputtered on the base material. The chip is configured in the accommodating groove of the carrier plate. The chip is provided with an active surface and a back surface which are opposite to each other and a plurality of electrodes arranged on the active surface. And forming a circuit structure layer on the carrier plate, wherein the circuit structure layer comprises a patterned circuit and a plurality of conductive through holes. The patterned circuit is electrically connected with the electrode of the chip through the conductive through hole. And forming a packaging colloid to cover the active surface of the chip and the circuit structure layer, wherein the active surface of the chip and the bottom surface of the packaging colloid are coplanar. The carrier is removed to expose the bottom surface of the encapsulant.

Description

Chip packaging structure and manufacturing method thereof
Technical Field
The present invention relates to a package structure and a method for fabricating the same, and more particularly, to a chip package structure and a method for fabricating the same.
Background
In the conventional coreless process, a local edge of the carrier and a local edge of the circuit board are bonded together by using an adhesive or by using a copper-plated edge seal. Another conventional method is to use a thin substrate (with a thickness of, for example, 100 microns) containing fiberglass cloth, a copper foil attached to each side, and a strippable ultra-thin copper foil (with a thickness of, for example, 3 to 5 microns) attached thereto as a carrier. And after the circuit board is subjected to a plurality of processes, cutting off the part with the adhesive or the copper-plated edge sealing between the carrier plate and the circuit board to obtain the circuit board for the packaging process. However, in the conventional coreless process, a portion of the carrier and a portion of the circuit board need to be cut off, so that the size of the circuit board is reduced and the carrier after cutting off cannot be reused, which results in an increase in manufacturing cost.
In order to solve the above problems, a conventional stainless steel plate is used as a base of a carrier, and in the process of manufacturing a circuit structure, the stainless steel plate can provide good stability, and is not required to be cut when the circuit structure is disassembled, so that the stainless steel plate can be repeatedly used, and the manufacturing cost can be effectively saved. However, the stainless steel plate is very bulky and heavy, and is not easy to be carried in the manufacturing process, and the corners of the stainless steel plate are sharp, which may cause damage to the substrate itself or the machine.
In addition, in the conventional method for manufacturing the chip package structure, a dielectric layer, such as a Prepreg (PP), is laminated or attached on the chip. Then, a Via (Via) is formed in the dielectric layer and connected to the electrode of the chip by laser ablation to complete a Fan-out packaging structure. However, the fan-out package fabricated through the dielectric layer is complicated in structure and manufacturing process, and has high cost.
Disclosure of Invention
The invention aims at a chip packaging structure and a manufacturing method thereof, which are safer and simpler in manufacturing, and can effectively reduce the manufacturing cost and improve the product yield.
According to an embodiment of the invention, a manufacturing method of a chip packaging structure comprises the following steps. A carrier plate is provided. The carrier plate is provided with a containing groove and comprises a base material and a stainless steel layer sputtered on the base material. The chip is configured in the accommodating groove of the carrier plate. The chip is provided with an active surface and a back surface which are opposite to each other and a plurality of electrodes arranged on the active surface. And forming a circuit structure layer on the carrier plate, wherein the circuit structure layer comprises a patterned circuit and a plurality of conductive through holes. The patterned circuit is electrically connected with the electrode of the chip through the conductive through hole. And forming a packaging colloid to cover the active surface of the chip and the circuit structure layer, wherein the active surface of the chip and the bottom surface of the packaging colloid are coplanar. The carrier plate is removed to expose the circuit structure layer.
In the manufacturing method of the chip packaging structure according to the embodiment of the invention, the material of the base material includes a sheet-shaped glass fiber resin base material, a rolled glass fiber resin base material or a rolled stainless steel base material.
In the method for manufacturing a chip package structure according to an embodiment of the present invention, the method further includes: before the chip is configured in the accommodating groove of the carrier plate, a metal layer is formed on the stainless steel layer. When the carrier plate is removed, the metal layer is removed at the same time.
In the method for manufacturing a chip package structure according to an embodiment of the present invention, the step of forming a circuit structure layer on a carrier includes: a first patterned photoresist layer is formed on the metal layer. The first patterned photoresist layer exposes the electrode of the chip and a part of the metal layer. And sputtering the first metal layer and a second metal layer on the first patterned photoresist layer and the electrode and the metal layer of the chip exposed by the first metal layer. And forming a second patterned photoresist layer on the second metal layer, wherein the second patterned photoresist layer is positioned above the first patterned photoresist layer and exposes a part of the second metal layer. And performing an electroplating process to form a conductive material layer on the second patterned photoresist layer and the exposed second metal layer. And removing the first patterned photoresist layer, the second patterned photoresist layer, part of the first metal layer and part of the second metal layer to form a circuit structure layer and expose the metal layer. The patterned circuit of the circuit structure layer comprises a plurality of inner pins and a plurality of outer pins. The inner leads are separated from each other and located above the chip. The outer pin is connected with the inner pin and is arranged on the metal layer in an extending way.
In the method for manufacturing the chip package structure according to the embodiment of the invention, the encapsulant covers a portion of the metal layer and the active surface of the chip, and covers the inner leads and the conductive through holes.
In the method for manufacturing a chip package structure according to an embodiment of the present invention, the method further includes: when the carrier plate is removed, the back surface of the chip and the metal layer thereon are exposed. A surface treatment layer is formed on the metal layer on the back surface of the chip.
In the manufacturing method of the chip package structure according to the embodiment of the invention, the carrier further has a plurality of recesses, wherein the recesses surround the accommodating groove, and the stainless steel layer is disposed conformal with the substrate.
In the method for manufacturing a chip package structure according to an embodiment of the present invention, the method further includes: before the chip is configured in the accommodating groove of the carrier plate, a metal layer is formed on the stainless steel layer. The metal layer fills the recess to define a plurality of conductive bumps. When the carrier is removed, the conductive bumps on the bottom surface of the encapsulant and a portion of the metal layer on the back surface of the chip are exposed.
In the method for manufacturing a chip package structure according to an embodiment of the present invention, the step of forming a circuit structure layer on a carrier includes: a first patterned photoresist layer is formed on the metal layer. The first patterned photoresist layer exposes the electrode of the chip and a part of the metal layer. And sputtering the first metal layer and a second metal layer on the first patterned photoresist layer and the electrode and the metal layer of the chip exposed by the first metal layer. And forming a second patterned photoresist layer on the second metal layer, wherein the second patterned photoresist layer is positioned above the first patterned photoresist layer and exposes a part of the second metal layer. And performing an electroplating process to form a conductive material layer on the second patterned photoresist layer and the exposed second metal layer. And removing the first patterned photoresist layer, the second patterned photoresist layer, part of the first metal layer and part of the second metal layer to form a circuit structure layer and expose the metal layer.
In the method for manufacturing the chip package structure according to the embodiment of the invention, the encapsulant covers the metal layer and the active surface of the chip, and covers the patterned circuit and the conductive through hole.
In the method for manufacturing a chip package structure according to an embodiment of the present invention, the method further includes: after removing the carrier plate, a surface treatment layer is formed on the peripheral surface of the conductive bump and the metal layer on the back surface of the chip.
According to an embodiment of the invention, the chip packaging structure comprises a circuit structure layer, a chip and a packaging colloid. The circuit structure layer comprises a patterned circuit and a plurality of conductive through holes. The chip is provided with an active surface and a back surface which are opposite to each other and a plurality of electrodes arranged on the active surface. The patterned circuit is electrically connected with the electrode of the chip through the conductive through hole. The packaging colloid covers the active surface of the chip and the circuit structure layer, wherein the active surface of the chip and the bottom surface of the packaging colloid are coplanar.
In an embodiment of the invention, the patterned circuit of the chip package structure includes a plurality of inner leads and a plurality of outer leads. The inner leads are separated from each other and located above the chip. The packaging colloid covers the inner pins and the conductive through holes, and the outer pins are connected with the inner pins and extend out of the packaging colloid.
In an embodiment of the invention, the chip package structure further includes a surface treatment layer disposed on the metal layer on the back surface of the chip and the side surface connecting the back surface and the active surface.
In an embodiment of the invention, the chip package structure further includes a plurality of conductive bumps disposed on the bottom surface of the encapsulant and electrically connected to the patterned circuits through the conductive vias.
In an embodiment of the invention, the chip package structure further includes a surface treatment layer disposed on the metal layer on the back surface of the chip and the side surface connecting the back surface and the active surface, and on the peripheral surface of the conductive bump.
In view of the above, in the manufacturing method of the chip package structure of the present invention, the stainless steel layer is formed on the substrate of the carrier by sputtering, so that good stability can be provided during the manufacturing process of the circuit structure layer. Furthermore, the stainless steel layer formed by sputtering has smaller volume and weight compared with the conventional stainless steel plate, and maintains the characteristic of mechanical separation of the stainless steel film and the copper plating film thereon, and is safer and simpler to operate. In addition, the carrier plate is not required to be cut when being separated to expose the circuit structure layer, so that the carrier plate can be repeatedly used, and the manufacturing cost can be effectively saved.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.
Fig. 1A to fig. 1I are schematic cross-sectional views illustrating a method for manufacturing a chip package structure according to an embodiment of the invention;
fig. 1J is a schematic cross-sectional view illustrating a chip package structure according to an embodiment of the invention;
fig. 2A to fig. 2I are schematic cross-sectional views illustrating a method for fabricating a chip package structure according to another embodiment of the invention;
fig. 2J is a schematic cross-sectional view illustrating a chip package structure according to another embodiment of the invention.
Description of the reference numerals
100a1, 100a2, 100b1, 100b 2: a chip package structure;
110a, 110 b: a carrier plate;
112. 112': a substrate;
114. 114': a stainless steel layer;
120. 120', 170: a metal layer;
130: a chip;
131: an active surface;
132: an electrode;
133: a back side;
135: a side surface;
140: a first metal layer;
145: a second metal layer;
150. 150': a circuit structure layer;
150 a: a layer of conductive material;
152. 152': patterning the circuit;
153: an inner pin;
154. 154': a conductive via;
155: an outer pin;
160. 160': packaging the colloid;
162. 162': a bottom surface;
170', 172: a surface treatment layer;
C. c': an accommodating groove;
c1: a recess;
p1, P1': a first patterned photoresist layer;
p2, P2': a second patterned photoresist layer;
s: a peripheral surface;
t: and a conductive bump.
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Fig. 1A to fig. 1I are schematic cross-sectional views illustrating a method for manufacturing a chip package structure according to an embodiment of the invention. Referring to fig. 1A, a carrier 110a is provided, wherein the carrier 110a has a receiving cavity C and includes a substrate 112 and a stainless steel layer 114 sputtered on the substrate 112. Here, the base material 112 may be a hard base material composed of a glass fiber resin substrate and copper foils disposed on opposite sides of the glass fiber resin substrate; or the glass fiber resin substrate can be coiled or the stainless steel substrate can be coiled; alternatively, the glass substrate that has been electroplated with a titanium layer and a copper layer is within the scope of the present invention. The stainless steel layer 114 is made of SUS 304 or other suitable materials, for example, wherein the thickness of the stainless steel layer 114 is between 0.05 micrometers and 0.5 micrometers, for example. In other words, the stainless steel layer 114 can be considered as a stainless steel film.
Next, referring to fig. 1A, a metal layer 120 is formed on the stainless steel layer 114. Here, the metal layer 120 is disposed conformal with the carrier 110a, wherein the material of the metal layer 120 is, for example, copper, but not limited thereto.
Next, referring to fig. 1B, the chip 130 is disposed in the accommodating recess C of the carrier 110a, wherein the chip 130 has an active surface 131 and a back surface 133 opposite to each other and a plurality of electrodes 132 disposed on the active surface 131. Here, the chip 130 is located on the metal layer 120 corresponding to the receiving recess C of the carrier 110a, and the electrode 132 is made of, for example, aluminum, but not limited thereto.
Next, referring to fig. 1C, a first patterned photoresist layer P1 is formed on the metal layer 120, wherein the first patterned photoresist layer P1 exposes the electrode 132 of the chip 130 and a portion of the metal layer 120.
Next, referring to fig. 1D, the first metal layer 140 and the second metal layer 145 on the first metal layer 140 are sputtered on the first patterned photoresist layer P1 and the exposed electrodes 132 of the chip 130 and the metal layer 120. Here, the first metal layer 140 is, for example, a titanium layer, and the second metal layer 145 is, for example, a copper layer; alternatively, the first metal layer 140 is, for example, a chromium layer, and the second metal layer 145 is, for example, a copper layer.
Next, referring to fig. 1E, a second patterned photoresist layer P2 is formed on the second metal layer 145, wherein the second patterned photoresist layer P2 is located above the first patterned photoresist layer P1 and exposes a portion of the second metal layer 145. Here, the pattern of the first patterned photoresist layer P1 is different from the pattern of the second patterned photoresist layer P2.
Next, referring to fig. 1F, an electroplating process is performed to form a conductive material layer 150a on the second patterned photoresist layer P2 and the exposed second metal layer 145 by using the second metal layer 145 as an electroplating seed layer.
Next, referring to fig. 1F and fig. 1G, the first patterned photoresist layer P1, the second patterned photoresist layer P2, a portion of the first metal layer 140 and a portion of the second metal layer 145 are removed, so as to form the circuit structure layer 150 and expose the metal layer 120. At this point, the circuit structure layer 150 is formed on the carrier 110a, wherein the circuit structure layer 150 includes a patterned circuit 152 and a plurality of conductive vias 154, and the patterned circuit 152 is electrically connected to the electrodes 132 of the chip 130 through the conductive vias 154. Here, the patterned circuit 152 of the circuit structure layer 150 includes a plurality of inner leads 153 and a plurality of outer leads 155, wherein the inner leads 153 are separated from each other and located above the chip 130, and the outer leads 155 are connected to the inner leads 153 and extend and disposed on the metal layer 120. In addition, the conductive via 154 is formed by the remaining first metal layer 140, the remaining second metal layer 145 and a portion of the conductive material layer 150 a. As can be seen from the above description, in the embodiment, the line structure layer is not formed by using a dielectric layer, but after the photoresist is removed, a portion of the line is suspended to form an Air bridge (Air bridge) structure, and the line structure layer 150 may be regarded as a lead frame.
Then, referring to fig. 1H, an encapsulant 160 is formed to cover the active surface 131 of the chip 130 and the circuit structure layer 150, wherein the active surface 131 of the chip 130 is coplanar with the bottom surface 162 of the encapsulant 160. Here, the encapsulant 160 covers a portion of the metal layer 120 and the active surface 131 of the chip 130, and covers the inner leads 153 and the conductive vias 154.
Finally, referring to fig. 1H and fig. 1I, the carrier 110a and a portion of the metal layer 120 are removed to expose the bottom surface 162 of the encapsulant 160. Here, the carrier 110a is removed, for example, by placing the encapsulant 160 on a vacuum platform (not shown) downward, and vacuum-absorbing the encapsulant 160. In addition, the molding compound 160 is fixed by a mechanism and separated from the metal layer 120 on the carrier 110a along the interface with the stainless steel layer 114. Compared with the conventional carrier board removing method, the carrier board 110a of the present embodiment does not need to be cut, so the carrier board 110a can be reused, and the manufacturing cost can be effectively saved. In addition, the metal layer 120 is removed by, for example, etching. Thus, the lead frame type chip package structure 100a1 is completed.
In structure, referring to fig. 1I again, the chip package structure 100a1 includes a circuit structure layer 150, a chip 130 and a molding compound 160. The circuit structure layer 150 includes a patterned circuit 152 and a conductive via 154. The chip 130 has an active surface 131 and a back surface 133 opposite to each other, and an electrode 132 disposed on the active surface 131. The patterned circuit 152 includes inner leads 153 and outer leads 155, wherein the inner leads 153 are separated from each other and located above the chip 130, and the inner leads 153 of the patterned circuit 152 are electrically connected to the electrodes 132 of the chip 130 through the conductive vias 154. The encapsulant 160 covers the active surface 131 of the chip 130 and the circuit structure layer 150, wherein the encapsulant 160 covers the inner leads 153 and the conductive vias 154, and the outer leads 155 are connected to the inner leads 153 and extend out of the encapsulant 160. In particular, the active surface 131 of the chip 130 is coplanar with the bottom surface 162 of the encapsulant 160.
In short, in the method for manufacturing the chip package structure 100a1 of the present embodiment, the stainless steel layer 114 is formed on the substrate 112 of the carrier 110a by sputtering, so that good stability can be provided during the manufacturing process of the circuit structure layer 150. Furthermore, the stainless steel layer 114 formed by sputtering can be smaller in volume and weight than conventional stainless steel plates, and is safer and simpler to operate. In addition, the carrier 100a is not required to be cut when being separated, so that the carrier 100a can be reused, and the manufacturing cost can be effectively saved.
Fig. 1J is a schematic cross-sectional view illustrating a chip package structure according to an embodiment of the invention. The present embodiment follows the reference numerals and parts of the foregoing embodiments, wherein the same reference numerals are used to refer to the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the description of the embodiments is not repeated.
Referring to fig. 1J, after the carrier board 110a is removed in fig. 1H, only a portion of the metal layer 120 is removed, but the metal layers on the side surface 135 and the back surface 133 of the chip 130 are remained to form the metal layer 170. Then, a surface treatment layer 172 is formed on the metal layer 170 on the back surface 133 of the chip 130, wherein the surface treatment layer 172 is disposed on the metal layer 170. Here, the material of the surface treatment layer 172 is, for example, tin, but not limited thereto. Thus, the lead frame type chip package structure 100a2 is completed.
Since the chip package structure 100a2 of the present embodiment has the metal layer 170 disposed on the back surface 133 of the chip 130, the metal layer 170 can be directly used as a shielding layer for preventing electromagnetic interference. Compared to the conventional method of additionally providing a shielding plate or a grounding plate, the chip package structure 100a2 of the present embodiment has a thinner package thickness and can reduce the manufacturing cost.
Fig. 2A to fig. 2I are schematic cross-sectional views illustrating a method for manufacturing a chip package structure according to another embodiment of the invention. Referring to fig. 2A, a carrier 110b is provided, wherein the carrier 110b has a receiving cavity C 'and a plurality of notches C1 surrounding the receiving cavity C'. The carrier 110b includes a substrate 112 ' and a stainless steel layer 114 ' sputtered on the substrate 112 '. Here, the stainless steel layer 114 'is disposed conformally with the substrate 112'. Here, the base material 112' may be a hard base material composed of a glass fiber resin substrate and copper foils disposed on opposite sides of the glass fiber resin substrate; or, a rolled glass fiber resin substrate and a rolled stainless steel substrate; alternatively, the glass substrate that has been electroplated with a titanium layer and a copper layer is within the scope of the present invention. The stainless steel layer 114 'is made of, for example, SUS 304 or other suitable materials, and the thickness of the stainless steel layer 114' is, for example, 0.05 to 0.5 μm. In other words, the stainless steel layer 114' can be considered as a stainless steel film.
Next, referring to fig. 2B, a metal layer 120 ' is formed on the stainless steel layer 114 ', wherein the metal layer 120 ' fills the notches C1 to define a plurality of conductive bumps T. Here, the material of the metal layer 120' is, for example, copper, but not limited thereto.
Next, referring to fig. 2B, the chip 130 is disposed in the accommodating recess C' of the carrier 110B, wherein the chip 130 has an active surface 131 and a back surface 133 opposite to each other and a plurality of electrodes 132 disposed on the active surface 131. Here, the chip 130 is located on the metal layer 120 'corresponding to the receiving recess C' of the carrier 110b, and the electrode 132 is made of, for example, aluminum, but not limited thereto.
Next, referring to fig. 2C, a first patterned photoresist layer P1 'is formed on the metal layer 120', wherein the first patterned photoresist layer P1 'exposes the electrode 132 of the chip 130 and a portion of the metal layer 120'.
Next, referring to fig. 2D, the first metal layer 140 and the second metal layer 145 on the first metal layer 140 are sputtered on the first patterned photoresist layer P1 'and the exposed electrodes 132 of the chip 130 and the metal layer 120'. Here, the first metal layer 140 is, for example, a titanium layer, and the second metal layer 145 is, for example, a copper layer; alternatively, the first metal layer 140 is, for example, a chromium layer, and the second metal layer 145 is, for example, a copper layer.
Next, referring to fig. 2E, a second patterned photoresist layer P2 ' is formed on the second metal layer 145, wherein the second patterned photoresist layer P2 ' is located above the first patterned photoresist layer P1 ' and exposes a portion of the second metal layer 145. Here, the pattern of the first patterned photoresist layer P1 'is different from the pattern of the second patterned photoresist layer P2'.
Next, referring to fig. 2F, an electroplating process is performed to form a conductive material layer 150a 'on the second patterned photoresist layer P2' and the exposed second metal layer 145 by using the second metal layer 145 as an electroplating seed layer.
Next, referring to fig. 2F and fig. 2G, the first patterned photoresist layer P1 ', the second patterned photoresist layer P2', a portion of the first metal layer 140 and a portion of the second metal layer 145 are removed to form the circuit structure layer 150 'and expose the metal layer 120'. The circuit structure layer 150 ' includes a patterned circuit 152 ' and a plurality of conductive vias 154 ', wherein the patterned circuit 152 ' is electrically connected to the electrodes 132 of the chip 130 through the conductive vias 154 '. Here, the conductive via 154 'is formed by the remaining first metal layer 140, the remaining second metal layer 145 and a portion of the conductive material layer 150 a'. At this point, the circuit structure layer 150' is formed on the carrier 110 b.
Next, referring to fig. 2H, an encapsulant 160 'is formed to cover the active surface 131 of the chip 130 and the circuit structure layer 150', wherein the active surface 131 of the chip 130 is coplanar with the bottom surface 162 'of the encapsulant 160'.
Finally, referring to fig. 2H and fig. 2I, when the carrier 110b is removed, the conductive bumps T on the bottom surface 162 ' of the encapsulant 160 ' and a portion of the metal layer 120 ' on the back surface 133 of the chip 130 are exposed. Here, the encapsulant 160 'covers the metal layer 120' and the active surface 131 of the chip 130, and covers the patterned circuit 152 'and the conductive via 154'.
Here, the carrier 110b is removed, for example, by placing the encapsulant 160 'on a vacuum platform (not shown) and sucking the encapsulant 160' by vacuum. In addition, the molding compound 160 'is mechanically fixed and separated from the metal layer 120' on the carrier 110b along the interface with the stainless steel layer 114. Compared with the conventional carrier board removing method, the carrier board 110b of the present embodiment does not need to be cut, so the carrier board 110b can be reused, and the manufacturing cost can be effectively saved. In addition, the metal layer 120' is removed by, for example, etching. Thus, the chip package structure 100b1 of quad flat no-lead (QFN) type is completed.
In structure, referring to fig. 2I again, the chip package structure 100b1 includes a circuit structure layer 150 ', a chip 130 and a molding compound 160'. The line structure layer 150 ' includes a patterned line 152 ' and a conductive via 154 '. The chip 130 has an active surface 131 and a back surface 133 opposite to each other, and an electrode 132 disposed on the active surface 131. The patterned circuit 152 'is electrically connected to the electrode 132 of the chip 130 through the conductive via 154'. The encapsulant 160 'covers the active surface 131 of the chip 130 and the circuit structure layer 150'. In particular, the active surface 131 of the chip 130 is coplanar with the bottom surface 162 'of the encapsulant 160'. In addition, the chip package structure 100b1 of the present embodiment further includes a conductive bump T, wherein the conductive bump T is disposed on the bottom surface 162 ' of the encapsulant 160 ' and electrically connected to the patterned circuit 152 ' through the conductive via 154.
Fig. 2J is a schematic cross-sectional view illustrating a chip package structure according to an embodiment of the invention. The present embodiment follows the reference numerals and parts of the foregoing embodiments, wherein the same reference numerals are used to refer to the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the description of the embodiments is not repeated.
Referring to fig. 2J, after the step of fig. 2I, a surface treatment layer 170 'may also be formed on the peripheral surface S of the conductive bump T and the metal layer 120' on the back surface 133 of the chip 130. Here, the material of the surface treatment layer 170' is, for example, tin, but not limited thereto. Thus, the fabrication of the quad flat no-lead (QFN) type chip package structure 100b2 is completed.
Since the chip package structure 100b2 of the present embodiment has the surface finish layer 170 'disposed on the back surface 133 of the chip 130, the side surface 135 connecting the back surface 133 and the active surface 131, and the peripheral surface S of the conductive bump T, the surface finish layer 170' can directly serve as an electromagnetic interference shielding layer. Compared to the conventional method of additionally providing a shielding plate or a grounding plate, the chip package structure 100b2 of the present embodiment has a thinner package thickness and can reduce the manufacturing cost.
In summary, in the manufacturing method of the chip package structure of the present invention, the stainless steel layer is formed on the substrate of the carrier by sputtering, so that good stability can be provided during the manufacturing process of the circuit structure layer. Furthermore, the stainless steel layer formed by sputtering has smaller volume and weight than the conventional stainless steel plate, and is safer and simpler to operate. In addition, the carrier plate is not required to be cut when being separated to expose the circuit structure layer, so that the carrier plate can be repeatedly used, and the manufacturing cost can be effectively saved. In addition, in some embodiments of the chip package structure of the present invention, a surface treatment layer may be added to serve as an electromagnetic interference shielding layer, which may have a thinner package thickness and may reduce the manufacturing cost.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (16)

1. A method for manufacturing a chip packaging structure is characterized by comprising the following steps:
providing a carrier plate, wherein the carrier plate is provided with a containing groove and comprises a base material and a stainless steel layer sputtered on the base material;
configuring a chip in the accommodating groove of the carrier plate, wherein the chip is provided with an active surface and a back surface which are opposite to each other and a plurality of electrodes arranged on the active surface;
forming a circuit structure layer on the carrier plate, wherein the circuit structure layer comprises a patterned circuit and a plurality of conductive through holes, and the patterned circuit is electrically connected with the plurality of electrodes of the chip through the plurality of conductive through holes;
forming a packaging colloid to cover the active surface of the chip and the circuit structure layer, wherein the active surface of the chip and the bottom surface of the packaging colloid are coplanar; and
and removing the carrier plate to expose the circuit structure layer.
2. The method of claim 1, wherein the substrate comprises a glass fiber resin substrate in sheet form, a glass fiber resin substrate in roll form, or a stainless steel substrate in roll form.
3. The method for manufacturing a chip package structure according to claim 1, further comprising:
before the chip is configured in the accommodating groove of the carrier plate, a metal layer is formed on the stainless steel layer; and
and when the carrier plate is removed, the metal layer is removed at the same time.
4. The method of claim 3, wherein the step of forming the circuit structure layer on the carrier includes:
forming a first patterned photoresist layer on the metal layer, the first patterned photoresist layer exposing the plurality of electrodes of the chip and a portion of the metal layer;
sputtering a first metal layer and a second metal layer on the first patterned photoresist layer and the plurality of electrodes of the chip exposed by the first metal layer and the metal layer;
forming a second patterned photoresist layer on the second metal layer, wherein the second patterned photoresist layer is located above the first patterned photoresist layer and exposes a portion of the second metal layer;
performing an electroplating process to form a conductive material layer on the second patterned photoresist layer and the second metal layer exposed by the second patterned photoresist layer; and
and removing the first patterned photoresist layer, the second patterned photoresist layer, part of the first metal layer and part of the second metal layer to form the circuit structure layer and expose the metal layer, wherein the patterned circuit of the circuit structure layer comprises a plurality of inner pins and a plurality of outer pins, the inner pins are separated from each other and are positioned above the chip, and the outer pins are connected with the inner pins and are arranged on the metal layer in an extending manner.
5. The method of claim 4, wherein the encapsulant covers a portion of the metal layer and the active surface of the chip and covers the inner leads and the conductive vias.
6. The method for manufacturing the chip packaging structure according to claim 5, further comprising:
exposing the carrier plate on the metal layer on the back surface of the chip when the carrier plate is removed; and
forming a surface treatment layer on the metal layer on the back surface of the chip.
7. The method of claim 1, wherein the carrier further has a plurality of recesses, wherein the plurality of recesses surround the receiving groove, and the stainless steel layer is disposed conformal with the substrate.
8. The method for manufacturing the chip packaging structure according to claim 7, further comprising:
before the chip is configured in the accommodating groove of the carrier plate, a metal layer is formed on the stainless steel layer, wherein the metal layer fills the plurality of notches to define a plurality of conductive bumps; and
when the carrier plate is removed, the plurality of conductive bumps on the bottom surface of the encapsulant and a part of the metal layer on the back surface of the chip are exposed at the same time.
9. The method of claim 8, wherein the step of forming the circuit structure layer on the carrier includes:
forming a first patterned photoresist layer on the metal layer, the first patterned photoresist layer exposing the plurality of electrodes of the chip and a portion of the metal layer;
sputtering a first metal layer and a second metal layer on the first patterned photoresist layer and the plurality of electrodes of the chip exposed by the first metal layer and the metal layer;
forming a second patterned photoresist layer on the second metal layer, wherein the second patterned photoresist layer is located above the first patterned photoresist layer and exposes a portion of the second metal layer;
performing an electroplating process to form a conductive material layer on the second patterned photoresist layer and the second metal layer exposed by the second patterned photoresist layer; and
and removing the first patterned photoresist layer, the second patterned photoresist layer, part of the first metal layer and part of the second metal layer to form the circuit structure layer and expose the metal layer.
10. The method of claim 9, wherein the encapsulant covers the metal layer and the active surface of the chip and covers the patterned trace and the plurality of conductive vias.
11. The method for manufacturing the chip package structure according to claim 10, further comprising:
after removing the carrier plate, forming a surface treatment layer on the peripheral surfaces of the conductive bumps and the metal layer on the back surface of the chip.
12. A chip package structure, comprising:
the circuit structure layer comprises a patterned circuit and a plurality of conductive through holes;
a chip having an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface, wherein the patterned circuit is electrically connected to the plurality of electrodes of the chip through the plurality of conductive vias; and
and the packaging colloid covers the active surface of the chip and the circuit structure layer, wherein the active surface of the chip and the bottom surface of the packaging colloid are coplanar.
13. The chip package structure according to claim 12, wherein the patterned circuit comprises a plurality of inner leads and a plurality of outer leads, the inner leads are separated from each other and located above the chip, the encapsulant covers the inner leads and the conductive vias, and the outer leads are connected to the inner leads and extend out of the encapsulant.
14. The chip package structure according to claim 13, further comprising:
and the surface treatment layer is configured on the metal layer on the back surface of the chip and the side surface connecting the back surface and the active surface.
15. The chip package structure according to claim 12, further comprising:
the conductive bumps are arranged on the bottom surface of the packaging colloid and are electrically connected with the patterned circuit through the conductive through holes.
16. The chip package structure according to claim 15, further comprising:
and the surface treatment layer is configured on the back surface of the chip, the side surface connecting the back surface and the active surface and the peripheral surfaces of the conductive bumps.
CN202010038806.5A 2020-01-14 2020-01-14 Chip packaging structure and manufacturing method thereof Pending CN113192896A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010038806.5A CN113192896A (en) 2020-01-14 2020-01-14 Chip packaging structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010038806.5A CN113192896A (en) 2020-01-14 2020-01-14 Chip packaging structure and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN113192896A true CN113192896A (en) 2021-07-30

Family

ID=76972444

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010038806.5A Pending CN113192896A (en) 2020-01-14 2020-01-14 Chip packaging structure and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN113192896A (en)

Similar Documents

Publication Publication Date Title
KR20120109427A (en) Wiring board and semiconductor device
US20140054785A1 (en) Chip package structure and method for manufacturing same
CN109788666B (en) Circuit substrate and manufacturing method thereof
KR102069659B1 (en) Method for manufacturing semiconductor package substrate and semiconductor package substrate manufactured using the same
JP2015070263A (en) Package carrier and manufacturing method thereof
US20140353006A1 (en) Multilayer circuit board and method for manufacturing same
US12040272B2 (en) Connector for implementing multi-faceted interconnection
CN116631953A (en) Semiconductor package and method for manufacturing the same
CN103489796B (en) The manufacture method of element built-in type semiconductor package
KR20040040348A (en) Circuit device, circuit module, and manufacturing method of the circuit device
CN109788664B (en) Circuit substrate and manufacturing method thereof
CN106783790A (en) There is one kind low resistance three-dimension packaging structure and its process is lost
CN112420524B (en) Support frame and manufacturing method thereof
TWI762885B (en) Semiconductor packaging substrate, manufacturing method and packaging process thereof
CN112366197A (en) Lead frame for chip packaging, preparation method and chip packaging structure
CN113192896A (en) Chip packaging structure and manufacturing method thereof
TWI758138B (en) Chip package structure and manufacturing method thereof
JP6524526B2 (en) Semiconductor element mounting substrate and semiconductor device, and methods of manufacturing the same
CN213519935U (en) Lead frame for chip packaging and chip packaging structure
CN113286440B (en) Lead frame and manufacturing method thereof
US11037869B2 (en) Package structure and preparation method thereof
US11217551B1 (en) Chip package structure and manufacturing method thereof
KR20220164896A (en) High strength printed circuit board with breakgae, warpage prvention and restoration function and method of manufacturing the same, and semiconductor package thereof
CN107658286B (en) Substrate for mounting semiconductor element, semiconductor device, and method for manufacturing semiconductor device
TWI839601B (en) Chip package structure and manufacturing method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination