TWI758138B - Chip package structure and manufacturing method thereof - Google Patents

Abstract

A method for manufacturing a chip package structure is provided. A carrier board with a containing cavity included a substrate and a stainless steel layer sputtered on the substrate is provided. A chip is disposed inside the containing cavity of the carrier board. The chip has an active surface and a rear surface opposite to each other and several electrodes disposed on the active surface. A circuit structure layer is formed on the carrier board, wherein the circuit structure layer includes a patterning circuit and several conductive via holes. The patterning circuit is electrically connected with the electrodes of the chip through the conductive via holes. A molding compound is formed to cover the active surface of the chip and the circuit structure layer, wherein the active surface of the chip is coplanar with a bottom surface of the molding compound. The carrier board is removed so as to expose the chip disposed inside the containing cavity.

Description

Chip package structure and manufacturing method thereof

The present invention relates to a package structure and a manufacturing method thereof, and more particularly, to a chip package structure and a manufacturing method thereof.

In the well-known coreless process, the edge of the partial carrier board and the edge of the partial circuit board are firstly bonded by adhesive or copper-plated edge sealing. Another conventional method is to use a thin substrate (for example, 100 microns in thickness) containing glass fiber cloth, and then a piece of copper foil on both sides and a strippable ultra-thin copper foil (for example, 3 thickness) attached to it. μm to 5 μm) as the carrier plate. After the circuit board undergoes multiple processes, the part with adhesive or copper-plated edge between the carrier board and the circuit board is cut to obtain a circuit board for the packaging process. However, in the well-known coreless process, part of the carrier board and part of the circuit board need to be cut off. Therefore, the size of the circuit board will be reduced and the cut carrier board cannot be reused, resulting in increased manufacturing cost.

In order to solve the above problems, it is known to use a stainless steel plate as the base of the carrier. In the production process of the circuit structure, in addition to providing good stability, the stainless steel plate does not need to be cut when disassembling the plate, so it can be reused. , which can effectively save manufacturing costs. However, the stainless steel plate is bulky and heavy, and it is often difficult to handle during the production process, and its edges and corners are relatively sharp, which often causes damage to the substrate itself or the machine.

In addition, in the conventional method for fabricating the chip package structure, a dielectric layer, such as a prepreg (PP), is firstly laminated or laminated on the chip. Next, by means of laser ablation, vias are formed in the dielectric layer and connected to the electrodes of the chip, so as to complete the fan out packaging structure. However, the fan-out package fabricated through the dielectric layer is complicated in structure and process, and the cost is high.

The present invention provides a chip package structure and a manufacturing method thereof, which are relatively safe and simple to manufacture, and can effectively reduce manufacturing costs and improve product yield.

The manufacturing method of the chip package structure of the present invention includes the following steps. A carrier board is provided. The carrier plate has accommodating grooves and includes a base material and a stainless steel layer sputtered on the base material. The chip is arranged in the accommodating groove of the carrier. The wafer has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. A circuit structure layer is formed on the carrier board, wherein the circuit structure layer includes patterned circuits and a plurality of conductive through holes. The patterned circuit is electrically connected to the electrode of the chip through the conductive through hole. The encapsulant is formed to cover the active surface of the chip and the circuit structure layer, wherein the active surface of the chip and the bottom surface of the encapsulant are coplanar. The carrier plate is removed to expose the wafers placed in the accommodating recesses.

In an embodiment of the present invention, the material of the substrate includes a sheet-shaped glass fiber resin substrate, a roll-shaped glass fiber resin substrate, or a rolled-shaped stainless steel substrate.

In an embodiment of the present invention, the above-mentioned manufacturing method of the chip package structure further includes forming a metal layer on the stainless steel layer before arranging the chip in the accommodating groove of the carrier. When the carrier is removed, the metal layer is removed at the same time.

In an embodiment of the present invention, the above-mentioned step of forming the circuit structure layer on the carrier includes forming a first patterned photoresist layer on the metal layer. The first patterned photoresist layer exposes the electrodes and part of the metal layer of the wafer. The first metal layer and the second metal layer on the first metal layer are sputtered on the first patterned photoresist layer and on the electrodes and metal layers of the wafer exposed therefrom. forming a second patterned photoresist layer on the second metal layer, wherein the second patterned photoresist layer is located above the first patterned photoresist layer, and part of the second metal is exposed layer. An electroplating process is performed to form a layer of conductive material on the second patterned photoresist layer and on the exposed second metal layer. The first patterned photoresist layer, the second patterned photoresist layer, part of the first metal layer and part of the second metal layer are removed to form a circuit structure layer and expose the metal layer. The patterned circuit of the circuit structure layer includes a plurality of inner pins and a plurality of outer pins. The inner pins are separated from each other and located above the die. The outer pins are connected to the inner pins and are extended on the metal layer.

In an embodiment of the present invention, the above-mentioned encapsulant covers part of the metal layer and the active surface of the chip, and covers the inner leads and the conductive vias.

In an embodiment of the present invention, the above-mentioned manufacturing method of the chip package structure further includes exposing the metal layer on the backside of the chip when the carrier is removed. A surface treatment layer is formed on the metal layer on the backside of the wafer.

In an embodiment of the present invention, the above-mentioned carrier plate further has a plurality of notches, wherein the notches surround the accommodating grooves, and the stainless steel layer is conformally arranged with the substrate.

In an embodiment of the present invention, the above-mentioned manufacturing method of the chip package structure further includes forming a metal layer on the stainless steel layer before arranging the chip in the accommodating groove of the carrier. The metal layer fills the recess to define a plurality of conductive bumps. When the carrier plate is removed, the conductive bumps on the bottom surface of the encapsulant and a part of the metal layer on the back surface of the chip are exposed at the same time.

In an embodiment of the present invention, the above-mentioned step of forming the circuit structure layer on the carrier includes forming a first patterned photoresist layer on the metal layer. The first patterned photoresist layer exposes the electrodes and part of the metal layer of the wafer. The first metal layer and the second metal layer on the first metal layer are sputtered on the first patterned photoresist layer and on the electrodes and metal layers of the wafer exposed therefrom. forming a second patterned photoresist layer on the second metal layer, wherein the second patterned photoresist layer is located above the first patterned photoresist layer, and part of the second metal is exposed layer. An electroplating process is performed to form a layer of conductive material on the second patterned photoresist layer and on the exposed second metal layer. The first patterned photoresist layer, the second patterned photoresist layer, part of the first metal layer and part of the second metal layer are removed to form a circuit structure layer and expose the metal layer.

In an embodiment of the present invention, the above-mentioned encapsulant covers the metal layer and the active surface of the chip, and covers the patterned lines and the conductive vias.

In an embodiment of the present invention, the above-mentioned manufacturing method of the chip package structure further includes forming a surface treatment layer on the peripheral surface of the conductive bump and the metal layer on the backside of the chip after removing the carrier plate.

The chip packaging structure of the present invention includes a circuit structure layer, a chip and a packaging colloid. The line structure layer includes patterned lines and a plurality of conductive vias. The wafer has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The patterned circuit is electrically connected to the electrode of the chip through the conductive through hole. The encapsulating compound covers the active surface of the chip and the circuit structure layer, wherein the active surface of the chip and the bottom surface of the encapsulating compound are coplanar.

In an embodiment of the present invention, the above-mentioned patterned circuit includes a plurality of inner pins and a plurality of outer pins. The inner pins are separated from each other and located above the die. The encapsulation compound covers the inner pins and the conductive through holes, and the outer pins are connected to the inner pins and extend to the outside of the encapsulation compound.

In an embodiment of the present invention, the above-mentioned chip package structure further includes a surface treatment layer disposed on the backside of the chip and the metal layer on the side surface connecting the backside and the active surface.

In an embodiment of the present invention, the above-mentioned chip package structure further includes a plurality of conductive bumps disposed on the bottom surface of the encapsulant and electrically connected to the patterned circuit through conductive vias.

In an embodiment of the present invention, the above-mentioned chip package structure further includes a surface treatment layer disposed on the backside of the chip, the side surfaces connecting the backside and the active surface, and the peripheral surfaces of the conductive bumps.

Based on the above, in the manufacturing method of the chip package structure of the present invention, the stainless steel layer is formed on the base material of the carrier board by sputtering, so good stability can be provided during the manufacturing process of the circuit structure layer. Furthermore, the stainless steel layer formed by sputtering can have a smaller volume and weight than the conventional stainless steel plate, and maintain the characteristics that the stainless steel film and the copper-plated film on it can be mechanically separated. And it is safer and easier to operate. In addition, it is not necessary to cut the carrier board to expose the circuit structure layer, so the carrier board can be reused, thereby effectively saving the manufacturing cost.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and description to refer to the same or like parts.

1A to FIG. 1I are schematic cross-sectional views illustrating a method for fabricating a chip package structure according to an embodiment of the present invention. Regarding the manufacturing method of the chip package structure of this embodiment, first, referring to FIG. 1A , a carrier board 110 a is provided, wherein the carrier board 110 a has an accommodating groove C and includes a base material 112 and a stainless steel layer sputtered on the base material 112 . 114. Here, the base material 112 can be a rigid base material composed of a glass fiber resin substrate and copper foils disposed on opposite sides of the glass fiber resin substrate; alternatively, it can be a rolled glass fiber resin substrate or a rolled stainless steel substrate; Alternatively, the glass substrate that has been electroplated with the titanium layer and the copper layer, all of which belong to the scope of the present invention. The material of the stainless steel layer 114 is, for example, SUS 304 or other suitable types, and the thickness of the stainless steel layer 114 is, for example, between 0.05 μm and 0.5 μm. In other words, the stainless steel layer 114 can be regarded as a stainless steel film.

Next, referring to FIG. 1A again, a metal layer 120 is formed on the stainless steel layer 114 . Here, the metal layer 120 and the carrier board 110a are conformally disposed, wherein the material of the metal layer 120 is copper, for example, but not limited thereto.

Next, referring to FIG. 1B , the chip 130 is disposed in the accommodating groove C of the carrier plate 110 a , wherein the chip 130 has an active surface 131 and a back surface 133 opposite to each other and a plurality of electrodes 132 disposed on the active surface 131 . Here, the wafer 130 is located on the metal layer 120 corresponding to the accommodating groove C of the carrier 110a, and the material of the electrode 132 is, for example, aluminum, but not limited thereto.

Next, referring to FIG. 1C , a first patterned photoresist layer P1 is formed on the metal layer 120 , wherein the first patterned photoresist layer P1 exposes the electrode 132 of the wafer 130 and part of the metal layer 120 .

Next, referring to FIG. 1D , the first metal layer 140 and the second metal layer 145 on the first metal layer 140 are sputtered on the first patterned photoresist layer P1 and the exposed surface of the wafer 130 . on the electrode 132 and the metal layer 120 . Here, the first metal layer 140 is, for example, a titanium layer, and the second metal layer 145 is, for example, a copper layer; or, the first metal layer 140 is, for example, a chromium layer, and the second metal layer 145 is, for example, a copper layer.

Next, referring to FIG. 1E, a second patterned photoresist layer P2 is formed on the second metal layer 145, wherein the second patterned photoresist layer P2 is located on the first patterned photoresist layer Above P1, a part of the second metal layer 145 is exposed. Here, the pattern of the first patterned photoresist layer P1 is different from the pattern of the second patterned photoresist layer P2.

Next, please refer to FIG. 1F , using the second metal layer 145 as a plating seed layer, an electroplating process is performed to form on the second patterned photoresist layer P2 and the exposed second metal layer 145 The conductive material layer 150a.

Next, please refer to FIG. 1F and FIG. 1G at the same time, remove the first patterned photoresist layer P1 , the second patterned photoresist layer P2 , part of the first metal layer 140 and part of the second metal layer 145 , and the circuit structure layer 150 is formed and the metal layer 120 is exposed. So far, the circuit structure layer 150 has been formed on the carrier board 110a, wherein the circuit structure layer 150 includes the patterned circuit 152 and a plurality of conductive vias 154, and the patterned circuit 152 is electrically connected to the electrodes 132 of the chip 130 through the conductive vias 154 connect. Here, the patterned circuit 152 of the circuit structure layer 150 includes a plurality of inner pins 153 and a plurality of outer pins 155, wherein the inner pins 153 are separated from each other and are located above the wafer 130, and the outer pins 155 are connected to the inner pins 153 and extended on the metal layer 120 . In addition, the conductive via 154 is formed by the remaining first metal layer 140 , the remaining second metal layer 145 and part of the conductive material layer 150a. It can be known from the above content that in this embodiment, a dielectric layer is not used to fabricate the circuit structure layer, but after removing the photoresist, part of the circuit will be suspended to form an air bridge structure, In this case, the circuit structure layer 150 can be regarded as a lead frame.

1H , an encapsulant 160 is formed to cover the active surface 131 of the chip 130 and the circuit structure layer 150 , wherein the active surface 131 of the chip 130 and the bottom surface 162 of the encapsulant 160 are coplanar. Here, the encapsulant 160 covers part of the metal layer 120 and the active surface 131 of the chip 130 , and covers the inner leads 153 and the conductive vias 154 .

Finally, referring to FIG. 1H and FIG. 1I at the same time, the carrier 110 a and part of the metal layer 120 are removed to expose the bottom surface 162 of the encapsulant 160 . Here, the way of removing the carrier plate 110a is, for example, placing the encapsulating compound 160 on a vacuum platform (not shown) downward, and sucking the encapsulating compound 160 by vacuum. In addition, the encapsulant 160 is fixed by a mechanism, and is separated from the metal layer 120 located on the carrier board 110 a along the interface with the stainless steel layer 114 . Compared with the conventional method of removing the carrier board, the carrier board 110a of the present embodiment does not need to be cut, so the carrier board 110a can be reused, thereby effectively saving the manufacturing cost. In addition, the method of removing the metal layer 120 is, for example, etching. So far, the fabrication of the lead frame type chip package structure 100a1 has been completed.

Structurally, please refer to FIG. 1I again, the chip package structure 100 a 1 includes a circuit structure layer 150 , a chip 130 and an encapsulant 160 . The circuit structure layer 150 includes patterned circuits 152 and conductive vias 154 . The wafer 130 has an active surface 131 and a back surface 133 opposite to each other, and electrodes 132 disposed on the active surface 131 . The patterned circuit 152 includes inner leads 153 and outer leads 155 , wherein the inner leads 153 are separated from each other and located above the chip 130 , and the inner leads 153 of the patterned circuit 152 pass through the conductive vias 154 and the electrodes 132 of the chip 130 Electrical connection. The encapsulant 160 covers the active surface 131 of the chip 130 and the circuit structure layer 150 , wherein the encapsulant 160 covers the inner leads 153 and the conductive vias 154 , and the outer leads 155 are connected to the inner leads 153 and extend out of the encapsulant 160 . In particular, the active surface 131 of the die 130 is coplanar with the bottom surface 162 of the encapsulant 160 .

In short, in the manufacturing method of the chip package structure 100a1 of the present embodiment, the stainless steel layer 114 is formed on the base material 112 of the carrier board 110a by sputtering. Therefore, in the manufacturing process of the circuit structure layer 150, the Provides good stability. Furthermore, the stainless steel layer 114 formed by sputtering can have a smaller volume and weight than the conventional stainless steel plate, and is safer and easier to operate. In addition, it is not necessary to cut the carrier board 110a when separating, so the carrier board 110a can be reused, thereby effectively saving the manufacturing cost.

FIG. 1J is a schematic cross-sectional view of a chip package structure according to an embodiment of the present invention. In this embodiment, the element numbers and part of the contents of the previous embodiments are used, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and repeated descriptions are not repeated in this embodiment.

Referring to FIG. 1J , after the carrier 110 a is removed in FIG. 1H , only a part of the metal layer 120 is removed, but the metal layers on the side surface 135 and the back surface 133 of the chip 130 remain to become the metal layer 170 . Then, a surface treatment layer 172 is formed on the back surface 133 of the wafer 130 on the metal layer 170 , wherein the surface treatment layer 172 is disposed on the metal layer 170 . Here, the material of the surface treatment layer 172 is, for example, tin, but not limited thereto. So far, the fabrication of the lead frame type chip package structure 100a2 has been completed.

Since the chip package structure 100a2 of this embodiment has the metal layer 170 disposed on the back surface 133 of the chip 130, the metal layer 170 can directly serve as a shielding layer against electromagnetic interference. Compared with the conventional shielding plate or the grounding plate, the chip package structure 100a2 of the present embodiment can have a thinner package thickness and can reduce the process cost.

2A to 2I are schematic cross-sectional views illustrating a method for fabricating a chip package structure according to another embodiment of the present invention. Regarding the manufacturing method of the chip package of the present embodiment, first, referring to FIG. 2A , a carrier board 110b is provided, wherein the carrier board 110b has an accommodating groove C' and a plurality of notches C1 surrounding the accommodating groove C'. The carrier plate 110b includes a substrate 112' and a stainless steel layer 114' sputtered on the substrate 112'. Here, the stainless steel layer 114' is disposed conformally with the substrate 112'. Here, the base material 112' can be a rigid base material composed of a glass fiber resin substrate and copper foils disposed on opposite sides of the glass fiber resin substrate; or, a rolled glass fiber resin substrate and a rolled stainless steel substrate; The glass substrate electroplated with the titanium layer and the copper layer all belong to the scope of the present invention. The material of the stainless steel layer 114' is, for example, SUS 304 or other suitable types, and the thickness of the stainless steel layer 114' is, for example, between 0.05 microns and 0.5 microns. In other words, the stainless steel layer 114' can be regarded as a stainless steel film.

Next, referring to FIG. 2B , a metal layer 120' is formed on the stainless steel layer 114', wherein the metal layer 120' fills the recess C1 to define a plurality of conductive bumps T. Here, the material of the metal layer 120' is copper, for example, but not limited thereto.

Next, referring to FIG. 2B again, the chip 130 is disposed in the accommodating groove C' of the carrier board 110b, wherein the chip 130 has an active surface 131 and a back surface 133 opposite to each other and a plurality of electrodes 132 disposed on the active surface 131 . Here, the wafer 130 is located on the metal layer 120' corresponding to the accommodating groove C' of the carrier 110b, and the material of the electrode 132 is, for example, aluminum, but not limited thereto.

Next, referring to FIG. 2C, a first patterned photoresist layer P1' is formed on the metal layer 120', wherein the first patterned photoresist layer P1' exposes the electrode 132 of the wafer 130 and part of the metal Layer 120'.

2D, the first metal layer 140 and the second metal layer 145 on the first metal layer 140 are sputtered on the first patterned photoresist layer P1', and the exposed wafer 130 on the electrode 132 and the metal layer 120'. Here, the first metal layer 140 is, for example, a titanium layer, and the second metal layer 145 is, for example, a copper layer; or, the first metal layer 140 is, for example, a chromium layer, and the second metal layer 145 is, for example, a copper layer.

Next, referring to FIG. 2E, a second patterned photoresist layer P2' is formed on the second metal layer 145, wherein the second patterned photoresist layer P2' is located on the first patterned photoresist Above the agent layer P1 ′, part of the second metal layer 145 is exposed. Here, the pattern of the first patterned photoresist layer P1' is different from the pattern of the second patterned photoresist layer P2'.

Next, please refer to FIG. 2F , using the second metal layer 145 as a plating seed layer, an electroplating process is performed on the second patterned photoresist layer P2 ′ and on the exposed second metal layer 145 A conductive material layer 150a' is formed.

Next, please refer to FIG. 2F and FIG. 2G at the same time, remove the first patterned photoresist layer P1 ′, the second patterned photoresist layer P2 ′, part of the first metal layer 140 and part of the second metal layer layer 145 to form a circuit structure layer 150' and expose the metal layer 120'. The circuit structure layer 150' includes patterned lines 152' and a plurality of conductive vias 154', wherein the patterned lines 152' are electrically connected to the electrodes 132 of the wafer 130 through the conductive vias 154'. Here, the conductive via 154' is formed by the remaining first metal layer 140, the remaining second metal layer 145 and part of the conductive material layer 150a'. So far, the circuit structure layer 150' has been formed on the carrier board 110b.

Then, referring to FIG. 2H, an encapsulant 160' is formed to cover the active surface 131 of the chip 130 and the circuit structure layer 150', wherein the active surface 131 of the chip 130 and the bottom surface 162' of the encapsulant 160' are coplanar.

Finally, please refer to FIG. 2H and FIG. 2I at the same time, when the carrier 110b is removed, the conductive bumps T on the bottom surface 162' of the encapsulant 160' and a part of the metal layer 120' on the back surface 133 of the chip 130 are exposed at the same time. Here, the encapsulant 160' covers the metal layer 120' and the active surface 131 of the chip 130, and covers the patterned lines 152' and the conductive vias 154'.

Here, the way of removing the carrier plate 110b is, for example, placing the encapsulating compound 160' downward on a vacuum platform (not shown), and sucking the encapsulating compound 160' by vacuum. In addition, the encapsulant 160' is fixed by a mechanism, and is separated from the metal layer 120' located on the carrier board 110b along the interface with the stainless steel layer 114. Compared with the conventional method of removing the carrier board, the carrier board 110b of this embodiment does not need to be cut, so the carrier board 110b can be reused, thereby effectively saving the manufacturing cost. In addition, the manner of removing the metal layer 120' is, for example, etching. So far, the fabrication of the chip package structure 100b1 of the quad flat no-lead (QFN) type has been completed.

Structurally, please refer to FIG. 2I again, the chip package structure 100b1 includes a circuit structure layer 150', a chip 130 and an encapsulant 160'. The line structure layer 150' includes patterned lines 152' and conductive vias 154'. The wafer 130 has an active surface 131 and a back surface 133 opposite to each other, and electrodes 132 disposed on the active surface 131 . The patterned circuit 152' is electrically connected to the electrode 132 of the wafer 130 through the conductive via 154'. The encapsulant 160' covers the active surface 131 of the chip 130 and the circuit structure layer 150'. In particular, the active surface 131 of the die 130 is coplanar with the bottom surface 162' of the encapsulant 160'. In addition, the chip package structure 100b1 of the present embodiment further includes conductive bumps T, wherein the conductive bumps T are disposed on the bottom surface 162' of the encapsulant 160', and are electrically connected to the patterned lines 152' through the conductive vias 154.

2J is a schematic cross-sectional view of a chip package structure according to an embodiment of the present invention. In this embodiment, the element numbers and part of the contents of the previous embodiments are used, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and repeated descriptions are not repeated in this embodiment.

Referring to FIG. 2J, after the step of FIG. 2I, a surface treatment layer 170' can also be formed on the peripheral surface S of the conductive bump T and the metal layer 120' on the back surface 133 of the wafer 130. Here, the material of the surface treatment layer 170' is, for example, tin, but not limited thereto. So far, the fabrication of the chip package structure 100b2 of the Quad Flat No Outer Lead (QFN) type has been completed.

Since the chip package structure 100b2 of the present embodiment has the surface treatment layer 170' disposed on the backside 133 of the chip 130, the side surface 135 connecting the backside 133 and the active surface 131, and the surrounding surface S of the conductive bump T, the surface treatment Layer 170' can directly act as a shield against electromagnetic interference. Compared with the conventional shielding plate or the grounding plate, the chip package structure 100b2 of the present embodiment can have a thinner package thickness and can reduce the process cost.

To sum up, in the manufacturing method of the chip package structure of the present invention, the stainless steel layer is formed on the base material of the carrier board by sputtering, so it can provide good stability during the manufacturing process of the circuit structure layer . Furthermore, the stainless steel layer formed by sputtering can have smaller volume and weight than conventional stainless steel plates, and is safer and easier to operate. In addition, it is not necessary to cut the carrier board to expose the circuit structure layer, so the carrier board can be reused, thereby effectively saving the manufacturing cost. In addition, in some embodiments of the chip package structure of the present invention, a surface treatment layer can also be added to serve as a shielding layer for preventing electromagnetic interference, which can have a thinner package thickness and reduce process costs.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features thereof can be equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the embodiments of the present invention. scope.

100a1, 100a2, 100b1, 100b2: Chip package structure 110a, 110b: carrier board 112, 112': base material 114, 114': stainless steel layer 120, 120', 170: metal layer 130: Wafer 131: Active Surface 132: Electrodes 133: Back 135: Side Surface 140: first metal layer 145: Second metal layer 150, 150': circuit structure layer 150a: Conductive material layer 152, 152': patterned circuit 153: Inner pin 154, 154': conductive vias 155: Outer pin 160, 160': encapsulating colloid 162, 162': bottom surface 170', 172: Surface treatment layer C, C': accommodating groove C1: Notch P1, P1': first patterned photoresist layer P2, P2': second patterned photoresist layer S: Surrounding surface T: conductive bump

The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. 1A to FIG. 1I are schematic cross-sectional views illustrating a method for fabricating a chip package structure according to an embodiment of the present invention. FIG. 1J is a schematic cross-sectional view of a chip package structure according to an embodiment of the present invention. 2A to 2I are schematic cross-sectional views illustrating a method for fabricating a chip package structure according to another embodiment of the present invention. 2J is a schematic cross-sectional view of a chip package structure according to another embodiment of the present invention.

100a1: Chip Package Structure

130: Wafer

131: Active Surface

132: Electrodes

133: Back

150: Line structure layer

152: Patterned Circuits

153: Inner pin

154: Conductive Vias

155: Outer pin

160: encapsulating colloid

162: Underside

170: Metal Layer

Claims (14)

A method for fabricating a chip package structure, comprising: providing a carrier having an accommodating groove and comprising a base material and a stainless steel layer sputtered on the base material; disposing a chip on the carrier board In the accommodating groove, the chip has an active surface and a back surface opposite to each other and a plurality of electrodes arranged on the active surface; a circuit structure layer is formed on the carrier board, wherein the circuit structure layer includes a pattern a patterned circuit and a plurality of conductive vias, the patterned circuit is electrically connected to the electrodes of the chip through the conductive vias; an encapsulant is formed to cover the active surface of the chip and the circuit structure layer, wherein the The active surface of the chip is coplanar with a bottom surface of the encapsulant; and the carrier plate is removed to expose the chip placed in the accommodating groove. The method for manufacturing a chip package structure according to claim 1, wherein the material of the base material includes a sheet-shaped glass fiber resin base material, a roll-shaped glass fiber resin base material or a roll-shaped stainless steel base material. The method for manufacturing a chip package structure according to claim 1, further comprising: forming a metal layer on the stainless steel layer before disposing the chip in the accommodating groove of the carrier; and removing the carrier , while removing the metal layer. The method for fabricating a chip package structure as claimed in claim 3, wherein the step of forming the circuit structure layer on the carrier comprises: forming a first patterned photoresist layer on the metal layer, the first The patterned photoresist layer exposes the electrodes of the wafer and part of the metal layer; a first metal layer and a second metal layer on the first metal layer are sputtered on the first patterned photoresist on the resist layer, and on the electrodes of the wafer and the metal layer exposed by it; forming a second patterned photoresist layer on the second metal layer, wherein the second patterned A photoresist layer is located above the first patterned photoresist layer, and part of the second metal layer is exposed; an electroplating process is performed on the second patterned photoresist layer , and a conductive material layer is formed on the exposed second metal layer; and the first patterned photoresist layer, the second patterned photoresist layer, and part of the first patterned photoresist layer are removed. A metal layer and a part of the second metal layer are formed to form the circuit structure layer and expose the metal layer, wherein the patterned circuit of the circuit structure layer includes a plurality of inner pins and a plurality of outer pins, the inner leads The pins are separated from each other and located above the chip, and the outer pins are connected to the inner pins and are extended on the metal layer. The manufacturing method of the chip package structure as claimed in claim 4, wherein the encapsulant covers part of the metal layer and the active surface of the chip, and covers the inner pins and the conductive vias. The manufacturing method of the chip package structure according to claim 5, further comprising: When the carrier is removed, it is exposed on the metal layer on the backside of the chip; and a surface treatment layer is formed on the metal layer on the backside of the chip. The manufacturing method of the chip package structure according to claim 1, wherein the carrier plate further has a plurality of notches, wherein the notches surround the accommodating groove, and the stainless steel layer is conformally disposed with the substrate. The method for manufacturing a chip package structure as claimed in claim 7, further comprising: forming a metal layer on the stainless steel layer before arranging the chip in the accommodating groove of the carrier, wherein the metal layer fills the The notches define a plurality of conductive bumps; and when the carrier is removed, the conductive bumps on the bottom surface of the encapsulant and a portion of the metal layer on the back surface of the chip are exposed simultaneously. The method for fabricating a chip package structure as claimed in claim 8, wherein the step of forming the circuit structure layer on the carrier comprises: forming a first patterned photoresist layer on the metal layer, the first The patterned photoresist layer exposes the electrodes of the wafer and part of the metal layer; a first metal layer and a second metal layer on the first metal layer are sputtered on the first patterned photoresist on the resist layer, and on the electrodes of the wafer and the metal layer exposed by it; forming a second patterned photoresist layer on the second metal layer, wherein the second patterned a photoresist layer is located above the first patterned photoresist layer, and a part of the second metal layer is exposed; performing an electroplating process to form a conductive material layer on the second patterned photoresist layer and the exposed second metal layer; and removing the first patterned photoresist A chemical layer, the second patterned photoresist layer, a part of the first metal layer and a part of the second metal layer are formed to form the circuit structure layer and expose the metal layer. The manufacturing method of the chip package structure as claimed in claim 9, wherein the encapsulant covers the metal layer and the active surface of the chip, and covers the patterned circuit and the conductive vias. The method for manufacturing a chip package structure according to claim 10, further comprising: after removing the carrier board, forming a surface treatment layer on a surrounding surface of the conductive bumps and the metal on the backside of the chip layer. A chip package structure includes: a circuit structure layer including a patterned circuit and a plurality of conductive vias; a chip having an active surface and a back surface opposite to each other and a plurality of electrodes arranged on the active surface, wherein The patterned circuit is electrically connected to the electrodes of the chip through the conductive vias; and an encapsulant covers the active surface of the chip and the circuit structure layer, wherein the active surface of the chip and the encapsulant A bottom surface is coplanar, wherein the patterned circuit includes a plurality of inner pins and a plurality of outer pins, the inner pins are separated from each other and are located above the chip, and the encapsulating compound covers the inner pins and the The conductive vias, and the outer pins are connected to the inner pins and extend out of the packaging compound. The chip package structure according to claim 12, further comprising a surface treatment layer disposed on the backside of the chip and a metal layer on a side surface connecting the backside and the active surface. A chip package structure includes: a circuit structure layer including a patterned circuit and a plurality of conductive vias; a chip having an active surface and a back surface opposite to each other and a plurality of electrodes arranged on the active surface, wherein The patterned circuit is electrically connected to the electrodes of the chip through the conductive vias; an encapsulant covers the active surface of the chip and the circuit structure layer, wherein the active surface of the chip and the encapsulant a coplanar bottom surface; a plurality of conductive bumps disposed on the bottom surface of the encapsulant and electrically connected to the patterned circuit through the conductive vias; and a surface treatment layer disposed on the back surface of the chip and a side surface connecting the back surface and the active surface and a peripheral surface of the conductive bumps.

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