CN113192888B - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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CN113192888B
CN113192888B CN202110120471.6A CN202110120471A CN113192888B CN 113192888 B CN113192888 B CN 113192888B CN 202110120471 A CN202110120471 A CN 202110120471A CN 113192888 B CN113192888 B CN 113192888B
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layer
semiconductor structure
air gap
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CN113192888A (zh
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姚茜甯
杨柏峰
杨世海
程冠伦
王志豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体结构包括：半导体层的堆叠件，设置在衬底上方；金属栅极堆叠件，具有设置在半导体层的堆叠件上方的顶部部分和与半导体层的堆叠件交错的底部部分；内部间隔件，设置在金属栅极堆叠件的底部部分的侧壁上；气隙，被包围在内部间隔件层中；以及外延源极/漏极(S/D)部件，设置在内部间隔件层上方并与金属栅极堆叠件相邻。本申请的实施例还提供了半导体结构的形成方法。

Description

半导体结构及其形成方法
技术领域
本申请的实施例涉及半导体结构及其形成方法。
背景技术
半导体工业经历了快速增长。半导体材料和设计的技术进步产生了多代半导体器件，其中，每一代都具有比先前一代更小且更复杂的电路。在集成电路(IC)演化的过程中，功能密度(即，每芯片面积的互连器件的数量)已经普遍增大，而几何尺寸(即，使用制造工艺可以产生的最小组件(或线))已经减小。该按比例缩小工艺通常因提高生产效率和降低相关成本而提供益处。但是这些进步也增加了处理和制造半导体器件的复杂程度。
诸如全环栅(GAA)晶体管的多栅极晶体管已被结合到各种存储器和核心器件中，以减少IC芯片的占用面积，同时保持合理的处理裕度。与其他半导体器件一样，按比例缩小确实增加了制造GAA晶体管的复杂程度。在一个这样的示例中，当器件尺寸继续减小时，提供能够减小寄生电容的内部间隔件变得更具挑战性。至少由于这个原因，需要改进制造GAA晶体管中的内部间隔件的方法。
发明内容
在一些实施例中，一种方法，包括：在从半导体衬底突出的鳍上方形成伪栅极堆叠件，其中，所述鳍包括交替的沟道层和非沟道层的多层堆叠件(ML)；在所述ML中形成S/D凹槽；对每个非沟道层的一部分进行开槽以形成沟槽；在所述沟槽中沉积内部间隔件层，其中，该沉积在所述内部间隔件层中形成气隙；在所述S/D凹槽中和所述内部间隔件层上方形成外延源极/漏极(S/D)部件；从所述ML去除所述非沟道层以形成置于所述内部间隔件层之间的开口；以及在所述开口中并代替所述伪栅极堆叠件形成金属栅极堆叠件。
在一些实施例中，一种半导体结构，包括：半导体层的堆叠件，设置在衬底上方；金属栅极堆叠件，具有设置在所述半导体层的堆叠件上方的顶部部分和与所述半导体层的堆叠件交错的底部部分；内部间隔件，设置在所述金属栅极堆叠件的底部部分的侧壁上；气隙，被包围在所述内部间隔件中；以及外延源极/漏极(S/D)部件，设置在所述内部间隔件上方并与所述金属栅极堆叠件相邻。
在一些实施例中，一种半导体结构，包括：半导体层，设置在衬底上方；高k金属栅极堆叠件(HKMG)，设置在所述半导体层之间；源极/漏极(S/D)部件，设置为与所述HKMG相邻；以及内部间隔件，配置为将所述S/D部件与所述HKMG分离，其中，所述内部间隔件包括设置在所述HKMG的侧壁上的第一介电层、设置在所述第一介电层中的气隙和设置在所述第一介电层上方的第二介电层。
本申请的实施例提供了场效应晶体管中的内部间隔件中的气隙及其制造方法。
附图说明
当结合附图进行阅读时，从以下详细描述可更好地理解本发明。需要强调的是，根据行业的标准实践，各个部件未按比例绘制，并且仅用于说明目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1A和图1B示出根据本公开的各种实施例的用于制造半导体器件的示例性方法的流程图。
图2A是根据本公开的各种实施例的示例性半导体器件的三维立体图。
图2B是根据本公开的各种实施例的图2A所示的半导体器件的平面俯视图。
图3、图4、图5、图6、图7、图8、图9A、图9B、图9C、图10A、图10B、图11A、图11B、图12A、图12B、图13A和图13B是根据本公开的各种实施例的在图1A和/或图1B所示的方法的中间阶段中沿图2A和/或图2B所示的线A-A'截取的半导体器件的部分或全部的截面图。
具体实施方式
以下公开内容提供了许多不同的实施例或实例以实现本发明的不同特征。以下将描述组件和布置的具体实例以简化本发明。当然，这些仅是实例并且不意欲限制本发明。例如，以下本发明中一个部件形成在另一个部件上、连接和/或联接至另一部件可以包括部件以直接接触的方式形成的实施例，并且也可以包括形成插入在部件之间的额外的部件，从而使得部件可以不直接接触的实施例。另外，为了便于理解，使用例如“下部”、“上部”、“水平”、“垂直”、“在...之上”、“在...上方”、“在...下”、“在...下方”、“上”、“下”、“顶部”、“底部”等以及它们的派生词(例如，“水平地”、“向下地”、“向上地”等)空间相对术语以描述本发明的部件与另一部件的关系。空间相对术语旨在覆盖包括部件的器件的不同定位。
此外，当用“约”、“近似”等描述数值或数值的范围时，该词语旨在涵盖在包括所描述的数值的合理范围内的数值，诸如本领域技术人员所理解的所描述的数值的+/-10％或其他值。例如，词语“约5nm”涵盖从4.5nm至5.5nm的尺寸范围。另外，本发明可以在各个实例中重复附图标号和/或字母。这种重复仅是为了简明和清楚，其自身并不表示所论述的各个实施例和/或配置之间的关系。
本公开总体上涉及半导体器件，并且更具体地涉及场效应晶体管(FET)，诸如三维全环栅(GAA)FET、鳍式FET(FinFET)和/或其他FET。通常，GAA FET在FET的沟道区域中包括多个竖直堆叠的片(例如，纳米片)、线(例如，纳米线)或棒(例如，纳米棒)，从而针对各种IC应用实现更好的栅极控制、降低的漏电流以及改善的缩放能力。尽管用于制造GAA FET的现有技术通常已足以满足其预期的应用，但它们并不是在所有方面都完全令人满意。本公开包括多个实施例。不同的实施例可以具有不同的优点，并且没有必要要求任一实施例具有特别的优点。
现在参考图1A和图1B，示出根据本公开的各个方面的形成半导体器件200(以下简称为器件200)的方法100和方法300的流程图。方法100和300仅是示例，并且不旨在限制本公开超出权利要求中明确记载的内容。可以在方法100和300之前、期间和之后提供额外的操作，并且对于方法的额外的实施例，可将描述的一些操作替换、消除或转移。方法100和300在下面结合图3至图13B进行描述，其为在方法100的中间步骤中沿图2A和图2B所示的虚线AA'截取的器件200的截面图。器件200可以是在IC的加工期间制造的中间器件或其一部分，该中间器件可以包括静态随机存取存储器(SRAM)和/或其他逻辑电路、诸如电阻器、电容器和感应器的无源组件、以及有源组件，诸如GAA FET、FinFET、金属氧化物半导体场效应晶体管(MOSFET)、互补金属氧化物半导体(CMOS)晶体管、双极晶体管、高压晶体管、高频晶体管和/或其他晶体管。本公开不限于任何特定数量的器件或器件区域或任何特定器件配置。例如，尽管所示的器件200是三维器件，但是本公开还可以提供用于制造平面器件的实施例。在器件200的其他实施例中，可以在器件200中添加附加部件，并且可以替换、修改或消除下文描述的一些部件。
在操作102中，参考图1A和图2A-图4，方法100形成器件200，该器件包括从衬底202突出并由隔离结构208分离的一个或多个鳍(或有源区域)204、设置在鳍204上方的伪栅极堆叠件210以及设置在伪栅极堆叠件210的侧壁上的顶部间隔件212。尽管未示出，但是器件200可以包括设置在伪栅极堆叠件210上方的其他组件，诸如硬掩模层、阻挡层、其他合适的层或其组合。
衬底202可以包括：单质(单元素)半导体，诸如硅、锗和/或其他合适的材料；化合物半导体，诸如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、锑化铟和/或其他合适的材料；合金半导体，诸如SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP和/或其他合适的材料。衬底202可以是具有均匀组成的单层材料。替代地，衬底202可以包括具有适合于IC器件制造的相似或不同组成的多个材料层。在一个示例中，衬底202可以是绝缘体上硅(SOI)衬底，其具有形成在氧化硅层上的硅层。在另一示例中，衬底202可以包括导电层、半导体层、介电层、其他层或其组合。
在衬底202包括FET的一些实施例中，在衬底202中或上设置各种掺杂区域。掺杂区域可以掺杂有诸如磷或砷的n型掺杂剂和/或诸如硼或BF2的p型掺杂剂，这取决于设计要求。可以在衬底202上以p阱结构、n阱结构、双阱结构或凸起结构的形式直接形成掺杂区域。可以通过注入掺杂剂原子、原位掺杂外延生长和/或其他适当的技术形成掺杂区域。每个鳍204可以适合于提供n型FET或p型FET。在一些实施例中，如本文所示的鳍204可以适合于提供相似类型的FET，即，均为n型或均为p型。替代地，它们可以适合于提供不同类型的FET，即n型和p型。该配置仅用于说明目的，并不旨在进行限制。
在本实施例中，参考图2A和图3，每个鳍204包括交替的半导体层204b和半导体层204a的多层堆叠件(ML)，其竖直堆叠在衬底202的突出部分上。在本实施例中，每个半导体层204b均是牺牲层，被配置为在随后的处理步骤中去除，从而在半导体层204a(和衬底202)之间提供开口，以在其中形成金属栅极堆叠件。每个半导体层204a可以包括半导体材料，例如Si、Ge、SiC、SiGe、GeSn、SiGeSn、SiGeCSn、其他合适的半导体材料或它们的组合，而每个半导体层204b具有与半导体层204a不同的组成。在一个这样的示例中，半导体层204a可以包括元素Si，但是不含或基本上不含Ge，并且半导体层204b可以包括SiGe。在另一示例中，半导体层204a可以包括元素Si，但是不含或基本上不含Ge，并且半导体层204b可以包括Ge。在一些示例中，每个鳍204可以包括总共三到十对交替的半导体层204a和204b；当然，取决于特定的设计要求，其他配置也可以适用。
在本实施例中，形成ML包括以一系列外延工艺交替生长半导体层204a和204b。可以通过化学气相沉积(CVD)技术(例如，气相外延(VPE)、超高真空CVD(UHV-CVD)、低压(LP-CVD)和/或等离子体增强CVD(PE-CVD))、分子束外延、其他合适的选择性外延生长(SEG)工艺或其组合来实施外延工艺。外延工艺可以使用包含合适材料(例如，用于半导体层204b的Ge)的气体和/或液体前体，其与下面的衬底(例如，衬底202)的成分相互作用。在一些示例中，半导体层204a和204b可以形成为纳米片、纳米线或纳米棒。然后可以实施片(或线)形成工艺以去除半导体层204b，以在半导体层204a之间形成开口，并且随后在开口中形成金属栅极堆叠件，从而提供GAA FET。换句话说，剩余的半导体层204a与金属栅极堆叠件(例如，高k金属栅极堆叠件或HKMG)接合，其中“高k”是指介电常数大于氧化硅的介电常数(约为3.9)的介电材料，以提供GAA FET的沟道区域。因此，以下将半导体层204a称为沟道层204a，并且以下将半导体层204b称为非沟道层204b。
在本实施例中，在一系列的光刻和蚀刻工艺中，从ML和衬底202制造鳍204。例如，光刻工艺可以包括：形成覆盖在ML上的光刻胶层；将光刻胶层曝光为图案；执行曝光后烘烤工艺；以及对曝光的光刻胶层进行显影以形成图案化的掩模元件(未示出)。然后，使用图案化的掩模元件作为蚀刻掩模来蚀刻ML，从而使三维鳍204从衬底202突出。蚀刻工艺可以包括干蚀刻、湿蚀刻、反应离子蚀刻(RIE)、其他合适的工艺或其组合。随后使用任何合适的工艺(诸如灰化和/或抗蚀剂剥离)，将图案化的掩模元件从ML去除。
附加地或替代地，用于形成鳍204的方法的其他实施例也可以是合适的。例如，可以使用双图案化或多图案化工艺来图案化ML(和衬底202)。通常，双图案化或多图案化工艺将光刻和自对准工艺组合，从而允许创建具有例如间距小于使用单一、直接光刻工艺可获得的间距的图案。例如，在一个实施例中，在衬底上方形成牺牲层，并使用光刻工艺对其进行图案化。使用自对准工艺在图案化的牺牲层旁边形成间隔件。然后去除牺牲层，然后可以使用剩余的间隔件或心轴来图案化ML以形成鳍204。
已经引入了诸如GAA FET的多栅极器件，以通过增加栅极-沟道耦合来改善栅极控制，减小截止状态电流并减小短沟道效应(SCE)。GAA FET通常包括包围在多个水平半导体层周围的栅极结构，从而提供对所有侧的沟道区域的访问。GAA FET通常与CMOS工艺兼容，因此可以在保持栅极控制和减轻SCE的同时缩小其尺寸。当然，本公开不限于仅形成GAAFET，并且可以提供诸如FinFET的其他三维FET。这样，一个或多个鳍204可以包括半导体材料的单层，使得提供统一的鳍以形成FinFET。
因为HKMG插入在GAA FET中的沟道层之间，所以在HKMG的侧壁和与HKMG相邻设置的外延源极/漏极(S/D)部件的部分之间提供内部栅极间隔件，以减小器件的寄生电容，其通常随着内部间隔件的厚度的增加而减小。然而，尽管内部间隔件通常具有减小GAA FET中电容的优点，但它们并不是在所有方面都令人满意。例如，为了减小HKMG与相邻的S/D部件之间的寄生电容的目的而增加内部间隔件的厚度可以减小器件的有效沟道长度，从而在器件中引起不利的短沟道效应(SCE)。本公开提供了形成内部间隔件以减小GAA FET中的寄生电容而基本不缩短由更厚的内部间隔件引起的器件的有效沟道长度的方法。在一些实施例中，本公开提供内部间隔件，其具有嵌入一种或多种介电材料中的气隙。
再次参考图2A，隔离结构208可以包括氧化硅(SiO和/或SiO2)、低k介电材料、原硅酸四乙酯(TEOS)、掺杂的氧化硅(例如，硼磷硅酸盐玻璃(BPSG)、掺杂氟的硅酸盐玻璃(FSG))、其他合适的材料或其组合。隔离结构208可以包括浅沟槽隔离(STI)部件。诸如场氧化物、硅的局部氧化(LOCOS)和/或其他合适的结构的其他隔离结构也可以实施为隔离结构208。替代地，隔离结构208可以包括多层结构，例如，具有一个或多个热氧化物衬层。在一个实施例中，通过在鳍204的形成期间在衬底202中蚀刻沟槽来形成隔离结构208。然后可以通过沉积工艺用上述隔离材料填充沟槽，然后进行化学机械平坦化(CMP)工艺。在另一实施例中，通过在鳍204上方沉积作为间隔件层的介电层并随后对介电层开槽来形成隔离结构208，使得隔离结构208的顶面在鳍204的顶面下方。可以通过任何合适的方法来沉积隔离结构208，诸如CVD、可流动CVD(FCVD)、旋涂玻璃(SOG)、其他合适的方法或其组合。
还参考图2A、图2B和图4，伪栅极堆叠件(或占位栅极堆叠件)210设置在鳍204(以及因此在ML)上方，并且可以包括多晶硅。在本实施例中，在形成器件200的其他组件之后，用HKMG替换伪栅极堆叠件210的部分。可以通过一系列沉积和图案化工艺来形成伪栅极堆叠件210。例如，可以通过在鳍204上方沉积多晶硅层并执行各向异性蚀刻工艺(例如，干蚀刻工艺)以去除多晶硅的一部分来形成伪栅极堆叠件210。在一些实施例中，如图4所示，去除多晶硅层的部分还可以去除ML的顶部，从而获得如虚线所示的弯曲的上表面。在本实施例中，器件200还包括界面层211，其在通过诸如热氧化、化学氧化、其他适合的方法或其组合的适合方法沉积多晶硅层之前形成在鳍204上。
此后，仍然参考图4，顶部间隔件212可以形成在伪栅极堆叠件210的侧壁上。顶部间隔件212可以是单层结构或多层结构，并且可以包括氮化硅(SiN)、氧化硅(SiO和/或SiO2)、碳化硅(SiC)、含碳氮化硅(SiCN)、含碳氧化硅(SiOC)、含氧氮化硅(SiON)、硅(Si)、碳和氧掺杂的氮化硅(SiOCN)、低k介电材料、其他合适的材料或其组合。在本实施例中，顶部间隔件212包括形成在伪栅极堆叠件210的侧壁上的间隔件层212a和形成在间隔件层212a上的间隔件层212b。顶部间隔件212的每个间隔件层可以通过以下步骤形成：首先在伪栅极堆叠件210上方沉积介电层，随后在各向异性蚀刻工艺(例如，干蚀刻工艺)中去除介电层的部分，从而留下伪栅极堆叠件210的侧壁上的介电层的部分作为顶部间隔件212。
随后，方法100在操作104中形成用于器件200的内部间隔件(例如，内部间隔件222或223)，其被提供在随后形成的外延S/D部件(例如，外延S/D部件230)与非沟道层204b的侧壁之间。在本实施例中，操作104实现图1B所示的方法300的实施例，以形成内部间隔件222或223。在以下公开中，参考图5至图13B详细讨论方法300。
参考图5，方法300在操作302中去除ML的一部分以形成S/D凹槽206。在本实施例中，S/D凹槽206延伸至鳍204的顶面下方并进入衬底202。在本实施例中，方法300实施蚀刻工艺402以去除沟道层204a和非沟道层204b两者的部分。蚀刻工艺402可以通过干蚀刻工艺、湿蚀刻工艺、RIE工艺或其组合来实施。在一些实施例中，方法300使用合适的蚀刻剂或蚀刻剂的组合来实施干蚀刻工艺和/或RIE工艺。在一些实施例中，可以通过调节持续时间、温度、压力、源功率、偏置电压、偏置功率、蚀刻剂流速和/或其他合适的参数来调整操作302中的蚀刻工艺402。在一些实施例中，非沟道层204b的蚀刻比沟道层204a的蚀刻更多，并且蚀刻工艺402可以在非沟道层204b的侧壁上引起弯曲的表面，如图5所示。随后可以执行清洁工艺以用氢氟酸(HF)溶液或其他合适的溶液清洁S/D凹槽206。
参考图6，方法300在操作304中进一步去除非沟道层204b在S/D凹槽206中暴露的部分以形成沟槽214。在本实施例中，方法300选择性地去除非沟道层204b的部分而不去除或基本不去除沟道层204a的暴露在S/D凹槽206中的部分。方法300通过执行蚀刻工艺404来形成沟槽214，该蚀刻工艺包括例如干蚀刻工艺、湿蚀刻工艺、RIE工艺或其组合。在一些实施例中，蚀刻工艺404是使用基于氟的蚀刻剂(诸如HF、CF4、SF6、CH2F2、CHF3、C2F6、其他含氟蚀刻剂或其组合)的干蚀刻工艺和/或RIE工艺。在一些实施例中，方法300使用包括硝酸(HNO3)、氢氧化铵(NH3OH)、氟化铵(NH4F)、过氧化氢(H2O2)、其他合适的蚀刻剂或其组合的蚀刻剂来实施湿蚀刻工艺。在一些实施例中，操作304中的蚀刻工艺404由诸如持续时间、温度、压力、源功率、偏置电压、偏置功率、蚀刻剂流速和/或其他合适的参数的因素控制，以去除期望量的非沟道层204b。在本实施例中，操作304中去除的非沟道层204b的量由蚀刻工艺404的持续时间控制，以确保保持足够的沟道长度L以在随后的处理步骤中形成金属栅极堆叠件。
随后，参考图7，方法300在沟槽214中形成内部间隔件222。在本实施例中，如将在下面详细讨论的，内部间隔件222包括嵌入或部分地嵌入间隔件层216中的气隙218。在操作306中，参考图9A-图9C，方法300在沉积工艺406中，在沟槽214中和在S/D凹槽206的侧壁206SW上，即在沟道层204a的暴露部分上方，形成间隔件层216。在本实施例中，形成间隔件层216产生了嵌入或部分嵌入其中的气隙218，下面将详细讨论该工艺。
间隔件层216可以包括任何合适的介电材料，包括硅、碳、氧、氮、其他元素或其组合。例如，间隔件层216可以包括氮化硅(SiN)、氧化硅(SiO和/或SiO2)、碳化硅(SiC)、含碳氮化硅(SiCN)、含碳氧化硅(SiOC)、含氧氮化硅(SiON)、硅(Si)、碳和氧掺杂的氮化硅(SiOCN)、低k介电材料、原硅酸四乙酯(TEOS)、掺杂的氧化硅(例如，硼磷硅酸盐玻璃(BPSG)、掺氟硅酸盐玻璃(FSG)、磷硅酸盐玻璃(PSG)、掺硼硅酸盐玻璃(BSG)等)、其他合适的介电材料或其组合。在一些实施例中，选择间隔件层216的组成以在随后的栅极替换工艺期间具有合适的抗蚀刻性，而不会显著增加金属栅极堆叠件(例如，HKMG 260)和外延S/D部件230之间的寄生电容。
沉积工艺406可以包括任何合适的方法，诸如ALD、CVD、PVD、其他合适的方法或其组合。在一些实施例中，沉积工艺406包括当一种或多种ALD前体材料沉积在沟槽214中时以高脉冲模式实施的ALD工艺。高脉冲模式可以通过调节ALD工艺的一个或多个参数来实现，包括但不限于增加脉冲时间(即，前体材料的持续时间和/或流速)、在输送用于形成间隔件层216的前体材料时的脉冲压力、脉冲能量和/或脉冲频率。在本实施例中，以高脉冲模式实施的ALD工艺增加了间隔件层216的整体沉积速率。换句话说，本文提供的ALD工艺被配置为增加每单位时间沉积在沟槽214中的前体材料的量。在一些实施例中，沉积工艺406包括以高沉积速率实施CVD工艺以获得与上述ALD工艺相似的效果。
在本实施例中，参考图9A至图9C，无论在ALD工艺还是CVD工艺期间，增加间隔件层216的沉积速率，都会使间隔件层216横向生长于沟槽214的开口上的速率高于竖直生长于沟槽214的主体部分中的速率，从而形成气隙218。在本实施例中，以这种方式生长的间隔件层216表现出以间隔件层216的顶部厚度(ttop)和底部厚度(tbottom)之间的差异表征的突出结构。例如，突出结构的程度可以由(ttop-tbottom)/tbottom来限定。换句话说，在气隙218和沟槽214的侧壁之间测得的间隔件层216的厚度朝着沟槽214的开口增加。
除了和/或替代上述调节沉积参数(例如，脉冲压力、脉冲时间等)，为了促进突出结构的形成(即，气隙218的形成)，可以将由沟槽214的高度H与宽度W之比限定的沟槽214的纵横比增加到至少约4。如果该纵横比小于约4，则沟槽214的开口上的间隔件层216的横向生长速率可以接近沟槽214的主体中的竖直生长速率，从而可以在不形成气隙218的情况下完全填充沟槽214。在本实施例中，高度H也对应于间隔件层216的总厚度，可以为约5nm至约7nm。在一些实施例中，操作306中的沉积工艺406在高脉冲压力和/或脉冲时间下实施，以使得间隔件层216的顶部完全合并，如图9C所示。在一些实施例中，如图9A和图9B中所描绘的，间隔件层216的顶部包括小开口，即，间隔件层216没有完全密封沟槽214的开口。如下面将详细讨论的，随后通过另一间隔件层(例如，间隔件层220)或通过外延S/D部件(例如，外延S/D部件230)密封小开口。
仍参考图9A-图9C，形成间隔件层216可以使得气隙218具有各种配置，这取决于操作306中的沉积工艺406的条件。在本实施例中，增加沉积工艺(例如，ALD)的脉冲时间、沉积工艺的脉冲压力和/或沟槽214的纵横比促进气隙218的形成。在一些实施例中，比较图9B和图9C描绘的实施例，增加脉冲压力和脉冲时间两者增加了气隙218的体积。在一些实施例中，比较图9A与图9B和图9C中描绘的实施例，增加脉冲压力使气隙218的底面向上弯曲。在一些实施例中，增加间隔件层216中包括的材料的介电常数减小气隙218的体积，因为具有较高介电常数的材料通常比具有较低介电常数的材料流动性差，并且通常在沉积工艺406期间会较慢地融合。在一些示例中，气隙218可以由小于约0.5nm的直径(或高度)限定。尽管气隙218的配置不受图9A-图9C中所描绘的实施例的限制，但是仅出于讨论目的，以下公开内容采用图9A所描绘的配置作为示例。
在操作308中，方法300对间隔件层216实施可选的退火工艺。可以在适合于间隔件层216的组成的任何温度下通过任何合适的工艺对间隔件层216进行退火，诸如炉内退火工艺、快速热退火(RTA)工艺、尖峰退火工艺、激光退火工艺、其他合适的退火工艺或其组合。在一些实施例中，在退火工艺期间将一种或多种元素引入间隔件层216中。为了改变间隔件层216中包括的介电材料的介电常数，可以将诸如碳和/或氮的元素以一种或多种气态物质的形式提供给间隔件层216。在一个示例中，如果期望较低的介电常数以减小器件200中的寄生电容，则可以将碳引入间隔件层216。在另一示例中，如果期望较高的介电常数以改善间隔件层216的抗蚀刻性，可以将氮引入间隔件层216。应当理解，可以根据特定的设计要求省略或执行操作308。
在操作310中，仍参考图7和图9A-图9C，方法300实施蚀刻工艺以去除(或回蚀刻)形成在沟道层204a上方的间隔件层216的部分，例如，形成在沟道层204a上方的间隔件层216的最顶部部分，如图9A-图9C所示，以形成内部间隔件222。在一些实施例中，回蚀刻之后的间隔件层216的侧壁与沟道层204a的侧壁基本上共面。在一些实施例中，如图7中的内部间隔件222的放大图所示，获得的间隔件层216的侧壁向内弯曲并远离沟道层204a的侧壁。操作308中的蚀刻工艺可以是任何合适的工艺，诸如干蚀刻、湿蚀刻、RIE或其组合。在本实施例中，蚀刻剂(或蚀刻剂的组合)的选择不受限制，并且可以取决于间隔件层216的特定组成。在一些实施例中，当暴露沟道层204a的侧壁时，蚀刻工艺停止。对于其中间隔件层216合并在气隙218的开口上的实施例，如图9C所示，回蚀刻间隔件层216的部分可以产生通向气隙218的小开口。替代地，在回蚀刻工艺之后，气隙218可以被间隔件层216密封。
随后，参考图8，方法300在操作312和314中在间隔件层216上方形成间隔件层220。间隔件层220可以包括任何合适的介电材料，包括硅、碳、氧、氮、其他元素或其组合。例如，间隔件层220可以包括氮化硅(SiN)、氧化硅(SiO和/或SiO2)、碳化硅(SiC)、含碳氮化硅(SiCN)、含碳氧化硅(SiOC)、含氧氮化硅(SiON)、硅(Si)、碳和氧掺杂的氮化硅(SiOCN)、低k介电材料、原硅酸四乙酯(TEOS)、掺杂的氧化硅(例如，硼磷硅酸盐玻璃(BPSG)、掺氟硅酸盐玻璃(FSG)、磷硅酸盐玻璃(PSG)、掺硼硅酸盐玻璃(BSG)等)、其他合适的介电材料或其组合。
在一些实施例中，间隔件层220和间隔件层216具有基本相同的组成。在一些实施例中，间隔件层216包括比间隔件层220更多的碳。在一个这样的示例中，间隔件层216可以包括SiOCN，并且间隔件层220可以包括SiON。在另一示例中，间隔件层216可以包括SiCN，并且间隔件层220可以包括SiN。在一些实施例中，间隔件层220和间隔件层216的介电常数不同。在一个这样的示例中，间隔件层216可以具有比间隔件层220低的介电常数。在一些实施例中，间隔件层220包括比间隔件层216更致密的材料，即，间隔件层216比间隔件层216更多孔。应当注意，本实施例不限于这些示例。在本实施例中，可以根据例如改进的抗蚀刻性、减小的寄生电容和更大的设计自由度来选择间隔件层216和220的组成以增强器件性能。
方法300可以通过沉积工艺408在间隔件层216上形成间隔件层220，该沉积工艺通过任何合适的方法来实现，诸如ALD、CVD、其他合适的方法或其组合。在本实施例中，不需要以类似于沉积工艺406的高脉冲模式来实施沉积工艺408。在一些示例中，可以通过不同的工艺来实施沉积工艺406和408。例如，沉积工艺406可以通过ALD工艺实施，并且沉积工艺408可以通过CVD工艺实施。在另一示例中，沉积工艺406和408可以通过具有不同沉积参数(例如，不同的脉冲和/或沉积速率)的相同工艺(诸如CVD工艺或ALD工艺)来实施。在本实施例中，间隔件层220被沉积为小于约1nm的厚度。在一些实施例中，间隔件层220的厚度与间隔件层216的厚度的比率小于约1：5。
对于其中气隙218被部分暴露的实施例(参见图9A和图9B)，间隔件层220提供了更统一的衬底，用于随后形成外延S/D部件230。对于其中间隔件层216和间隔件层220具有不同组成的实施例，对于间隔件层220使用具有较高介电常数的材料可防止外延S/D材料意外地生长到间隔件层216和间隔件层220之间的气隙218和/或层间空间中。在一些实施例中，方法300省略了形成间隔件层220，使得操作106中将外延S/D部件230直接形成在间隔件层216上(参见图1A和图1B)，从而进行密封或以其他方式覆盖气隙218。
此后，仍然参考图8，方法300在操作314中去除形成在沟道层204a的侧壁上的间隔件层220的部分，从而产生内部间隔件223。因此，除了间隔件层216和设置在其中的气隙218，内部间隔件223包括第二间隔件层，即，间隔件层220。在一些实施例中，所得的间隔件层220的侧壁与沟道层204a的侧壁基本上共面。换句话说，间隔件层220的侧壁与沟道层204a的侧壁是连续的。在一些实施例中，如内部间隔件232的放大图所示，所得间隔件层220的侧壁向内弯曲并远离沟道层204a的侧壁。
操作314中的蚀刻工艺可以包括干蚀刻工艺、湿蚀刻工艺、RIE或其组合，其利用用于选择性去除间隔件层220的蚀刻剂。在本实施例中，蚀刻剂(或蚀刻剂的组合)的选择不受限制，并且可以取决于间隔件层220的特定组成。在一些实施例中，当暴露沟道层204a的侧壁时，蚀刻工艺停止。对于其中间隔件层216和间隔件层220具有基本相同的组成的实施例，操作310和314中的蚀刻工艺可以获得更统一的表面以更好地适应后续的处理步骤。在一些实施例中，特别是当间隔件层220足够薄时，可以从方法300中省略操作314。将参考具有内部间隔件222(如图10A、图11A、图12A和图13A所示)或内部间隔件223(如图10B、图11B、图12B和图13B所示)的器件200来讨论方法300的后续操作。
现在参考图10A和图10B，方法300从操作314进行到方法100的操作106中在S/D凹槽206中形成外延S/D部件230。在所描绘的实施例中，因为间隔件层216和/或间隔件层220的表面向内弯曲，如参考图7和图8所示和所讨论的，所以外延S/D部件230的部分延伸超过沟道层204a的侧壁以接触间隔件层216和/或间隔件层220。换句话说，外延S/D部件230的部分在沟道层204a之间交错。在一些示例中，使用内部间隔件222作为示例，这种突起的距离P可以为约0.5nm至约2nm。与内部间隔件223接触的突起的距离也可以为约0.5至约2nm。在一些实施例中，本文提供的内部间隔件的配置在外延S/D部件230和沟道层204a之间提供更大的接触面积，从而改善了器件200的整体性能。对于其中气隙218被完全嵌入间隔件层216(参见图9C)的实施例，外延S/D部件230通过间隔件层216的至少一部分与气隙218分离。
每个外延S/D部件230可以适合于形成p型FET器件(例如，包括p型外延材料)或替代的n型FET器件(例如，包括n型外延材料)。p型外延材料可以包括一个或多个硅锗外延层(epi SiGe)，其中硅锗掺杂有诸如硼、锗、铟的p型掺杂剂和/或其他p型掺杂剂。n型外延材料可以包括一个或多个硅外延层(epi Si)或硅碳外延层(epi SiC)，其中硅或硅碳掺杂有诸如砷、磷的n型掺杂剂和/或其他n型掺杂剂。在一些实施例中，执行一个或多个外延生长工艺以在S/D凹槽206中生长外延材料。例如，方法100可以实施如上关于形成ML所讨论的外延生长工艺。在一些实施例中，通过在外延生长工艺期间将掺杂剂添加到源极材料中来原位掺杂外延材料。在一些实施例中，在执行沉积工艺之后，通过离子注入工艺来掺杂外延材料。在一些实施例中，随后执行退火工艺以激活外延S/D部件230中的掺杂剂。在一些示例中，方法100在操作106中可以首先形成适合于n型FET的外延S/D部件230，随后形成适合于p型FET的外延S/D部件230。
参考图11A和图11B，方法100在操作108中随后去除伪栅极堆叠件210以在顶部间隔件212之间形成栅极沟槽250。在去除伪栅极堆叠件210之前，方法100通过CVD、可流动CVD(FVCD)、旋涂玻璃(SOG)、其他合适方法或其组合，在外延S/D部件230上方形成层间介电(ILD)层242。ILD层242可以包括氧化硅、低k介电材料、TEOS、掺杂的氧化硅(例如，BPSG、FSG、PSG、BSG等)、其他合适的介电材料或其组合。方法100可以可选地首先在形成ILD层242之前在外延S/D部件230上方形成蚀刻停止层(ESL；未示出)。ESL可以包括氮化硅(SiN)、氧掺杂或碳掺杂的氮化硅(SiON或SiCN)、其他合适的材料或其组合，并且可以通过CVD、PVD、ALD、其他合适的方法或其组合形成。此后，方法100可以在一个或多个CMP工艺中平坦化ILD层242以暴露伪栅极堆叠件210的顶面。此后，通过任何合适的蚀刻工艺(诸如干蚀刻工艺)，将伪栅极堆叠件210的至少一部分从器件200去除以形成栅极沟槽250。在本实施例中，在去除伪栅极堆叠件210之后，界面层211保留在ML上方。
参考图12A和图12B，然后方法100在操作110中在片(或线)形成工艺中从ML去除非沟道层204b，从而在沟道层204a之间形成开口252。在本实施例中，方法100选择性地去除非沟道层204b，而不去除或基本上不去除沟道层204a。这可以通过确保非沟道层204b、沟道层204a和间隔件层216(作为内部间隔件222或223的一部分)之间存在足够的蚀刻选择性来实现。非沟道层204b可以通过由例如干蚀刻工艺、湿蚀刻工艺、RIE工艺或其组合实施的蚀刻工艺410选择性地去除。在一些实施例中，蚀刻工艺410包括使用基于氟的蚀刻剂(诸如HF、CF4、SF6、CH2F2、CHF3、C2F6、其他含氟蚀刻剂或其组合)的干蚀刻工艺和/或RIE工艺。在一些实施例中，蚀刻工艺410包括湿蚀刻工艺，其使用包括硝酸(HNO3)、氢氧化铵(NH3OH)、氟化铵(NH4F)、过氧化氢(H2O2)、其他合适的蚀刻剂或其组合的蚀刻剂。在一些实施例中，蚀刻工艺410实施与蚀刻工艺404相同的蚀刻剂。
现在参考图13A和图13B，方法100在操作112中栅极沟槽250和开口252中形成HKMG260。换句话说，HKMG 260形成在顶部间隔件212之间以及内部间隔件222或223之间。HKMG260至少包括设置在栅极沟槽250中和开口252中的高k介电层262以及设置在高k介电层262上方的金属栅电极264。在本实施例中，对于栅极沟槽250中形成的HKMG 260的顶部部分，高k介电层262的侧壁部分形成在顶部间隔件212上，而高k介电层262的底部部分形成在最顶部沟道层204a(和/或界面层211(如果存在的话))上方，使得高k介电层262被配置为U形。对于开口252中形成的HKMG 260的部分，高k介电层262的侧壁部分形成在内部间隔件222或223(例如，间隔件层216)上，而高k介电层262的顶部和底部部分形成在沟道层204a上，使得高k介电层262被沟道层204a和内部间隔件222或223包围。
高k介电层262可以包括任何合适的高k介电材料，诸如氧化铪、氧化镧、其他合适的材料或其组合。在一些实施例中，高k介电层262包括介电常数比间隔件层216和/或间隔件层220中包括的材料的介电常数高的介电材料。金属栅电极264可以包括至少一个功函数金属层(未单独示出)和块状导电层(未单独示出)并设置在其上方。功函数金属层可以是p型或n型功函数金属层。示例性功函数材料包括TiN、TaN、Ru、Mo、Al、WN、ZrSi2、MoSi2、TaSi2、NiSi2、Ti、Ag、TaAl、TaAlC、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、其他合适的功函数材料或其组合。块状导电层可以包括Cu、W、Al、Co、Ru、其他合适的材料或其组合。HKMG 260可以进一步包括许多其他层(未示出)，诸如盖层、阻挡层、其他合适的层或其组合。在一些实施例中，每个HKMG 260中包括的材料层的数量由设置在沟道层204a之间的开口252的尺寸确定。HKMG260的各个层可以通过任何合适的方法来沉积，诸如化学氧化、热氧化、ALD、CVD、PVD、镀敷、其他合适的方法或其组合。
此后，方法100在操作114中可以执行对器件200的附加处理步骤。例如，方法100可以在外延S/D部件230上方形成S/D接触件(未示出)。每个S/D接触件可以包括任何合适的导电材料，诸如Co、W、Ru、Cu、Al、Ti、Ni、Au、Pt、Pd、其他合适的导电材料或其组合。方法100可以经由一系列图案化和蚀刻工艺在ILD层242中以及在外延S/D部件230上方形成S/D接触件开口(或沟槽)，并且随后使用任何合适的方法(诸如CVD、PVD、镀敷、其他合适的工艺或其组合)在S/D接触件开口中沉积导电材料。在一些实施例中，可以在沉积导电材料之前在接触件开口中形成包括Ti、Ta、TiN、TaN、其他合适的材料或其组合的阻挡层。
在一些实施例中，在外延S/D部件230和S/D接触件之间形成硅化物层(未示出)。硅化物层可以包括硅化镍、硅化钴、硅化钨、硅化钽、硅化钛、硅化铂、硅化铒、硅化钯、其他合适的硅化物或其组合。可以通过诸如CVD、ALD、PVD或其组合的沉积工艺在器件200上方形成硅化物层。例如，可以在外延S/D部件230上方沉积金属层(例如，钛)，并且使器件200退火以允许金属层和外延S/D部件230的半导体材料反应。此后，去除未反应的金属层，在外延S/D部件230上方留下硅化物层。
随后，方法100可以在器件200上方形成附加部件，包括例如HKMG260上方的栅极接触件、S/D接触件上方的竖直互连结构(例如，通孔)、水平互连结构(例如，导线)、介电层(例如，金属间介电层)、其他合适的部件或其组合。
尽管不旨在限制，但本发明的一个或多个实施例提供了半导体器件及其形成的许多益处。例如，本公开在GAA FET中提供内部间隔件(例如，内部间隔件222和223)，其具有被一个或多个介电层包围的气隙。在一些实施例中，气隙至少部分地嵌入第一介电层(例如，间隔件层216)中。内部间隔件的一些实施例包括第二介电层(例如，间隔件层220)，其设置在第一介电层上方，并且气隙被第一介电层和第二介电层两者包围。第一介电层和第二介电层可以具有基本相同的组成。替代地，第二介电层可以包括具有比第一介电层更高的介电常数的材料。在一些实施例中，S/D部件的一部分延伸以接触两个沟道层之间的内部间隔件。通过包括气隙，本实施例提供了被配置为降低GAA FET的寄生电容的内部间隔件。此外，本实施例还提供了包括不同介电材料的内部间隔件，从而允许更大的灵活性以满足各种设计要求。所公开的方法的实施例可以容易地集成到用于制造三维FET(诸如GAA FET)的现有工艺和技术中。
在一个方面中，本实施例提供了一种方法，包括：在从半导体衬底突出的鳍上方形成伪栅极堆叠件，其中鳍包括交替的沟道层和非沟道层的多层堆叠件(ML)；在ML中形成S/D凹槽；在S/D凹槽中形成内部间隔件层；在S/D凹槽中和内部间隔件层上方形成外延源极/漏极(S/D)部件；从ML层去除非沟道层以形成置于内部间隔件层之间的开口；以及在开口中形成金属栅极堆叠件并代替伪栅极堆叠件。在本实施例中，形成内部间隔件层包括对每个非沟道层的一部分进行开槽以形成沟槽，并且在沟槽中沉积内部间隔件层，从而在内部间隔件层中形成气隙。
在另一方面中，本实施例提供了一种半导体结构，包括：半导体层的堆叠件，设置在衬底上方；金属栅极堆叠件，具有设置在半导体层的堆叠件上方的顶部部分和与半导体层的堆叠件交错的底部部分；内部间隔件，设置在金属栅极堆叠件的底部部分的侧壁上；气隙，被包围在内部间隔件层中；以及外延源极/漏极(S/D)部件，设置在内部间隔件层上方并与金属栅极堆叠件相邻。
在又一方面中，本实施例提供一种半导体衬底，包括：半导体层，设置在衬底上方；高k金属栅极堆叠件(HKMG)，设置在半导体层之间；源极/漏极(S/D)部件，设置为与HKMG相邻；内部间隔件，配置为将S/D部件与HKMG分离，其中，内部间隔件包括设置在HKMG的侧壁上的第一介电层、设置在第一介电层中的气隙和设置在第一介电层上方的第二介电层。
在一些实施例中，一种方法，包括：在从半导体衬底突出的鳍上方形成伪栅极堆叠件，其中，所述鳍包括交替的沟道层和非沟道层的多层堆叠件(ML)；在所述ML中形成S/D凹槽；对每个非沟道层的一部分进行开槽以形成沟槽；在所述沟槽中沉积内部间隔件层，其中，该沉积在所述内部间隔件层中形成气隙；在所述S/D凹槽中和所述内部间隔件层上方形成外延源极/漏极(S/D)部件；从所述ML去除所述非沟道层以形成置于所述内部间隔件层之间的开口；以及在所述开口中并代替所述伪栅极堆叠件形成金属栅极堆叠件。在一些实施例中，还包括：在形成所述外延S/D部件之前，去除所述内部间隔件层的形成在所述沟道层的侧壁上的部分。在一些实施例中，沉积所述内部间隔件层包括以高脉冲模式实施原子层沉积(ALD)工艺。在一些实施例中，还包括：在从所述沟道层的侧壁去除所述内部间隔件层的部分之前，对所述内部间隔件层进行退火。在一些实施例中，沉积所述内部间隔件层使得所述内部间隔件层的形成在所述气隙与所述沟槽的侧壁之间的部分的厚度朝着所述沟槽的开口增加。在一些实施例中，沉积所述内部间隔件层使得所述气隙被所述内部间隔件层部分地包围，使得形成所述外延S/D部件密封所述气隙。在一些实施例中，沉积所述内部间隔件层使得所述气隙完全嵌入所述内部间隔件层中，使得所述内部间隔件层的一部分设置在所述气隙和所述外延S/D部件之间。在一些实施例中，内部间隔件层是第一内部间隔件层，所述方法还包括在形成所述外延S/D部件之前，在所述第一内部间隔件层上方形成第二内部间隔件层。
在一些实施例中，一种半导体结构，包括：半导体层的堆叠件，设置在衬底上方；金属栅极堆叠件，具有设置在所述半导体层的堆叠件上方的顶部部分和与所述半导体层的堆叠件交错的底部部分；内部间隔件，设置在所述金属栅极堆叠件的底部部分的侧壁上；气隙，被包围在所述内部间隔件中；以及外延源极/漏极(S/D)部件，设置在所述内部间隔件上方并与所述金属栅极堆叠件相邻。在一些实施例中，内部间隔件是第一内部间隔件，所述半导体结构还包括设置在所述第一内部间隔件和所述外延S/D部件之间的第二内部间隔件。在一些实施例中，第二内部隔离件密封所述气隙。在一些实施例中，第二内部间隔件呈现出比所述第一内部间隔件更高的介电常数。在一些实施例中，与所述内部间隔件接触的外延S/D部件的部分设置在两个半导体层之间。在一些实施例中，气隙完全嵌入所述内部间隔件中，使得所述外延S/D部件通过所述内部间隔件的一部分与所述气隙分离。在一些实施例中，外延S/D部件密封所述气隙。在一些实施例中，内部间隔件的与所述气隙相邻的部分的厚度在朝向所述外延S/D部件的方向上增加。
在一些实施例中，一种半导体结构，包括：半导体层，设置在衬底上方；高k金属栅极堆叠件(HKMG)，设置在所述半导体层之间；源极/漏极(S/D)部件，设置为与所述HKMG相邻；以及内部间隔件，配置为将所述S/D部件与所述HKMG分离，其中，所述内部间隔件包括设置在所述HKMG的侧壁上的第一介电层、设置在所述第一介电层中的气隙和设置在所述第一介电层上方的第二介电层。在一些实施例中，气隙嵌入所述第一介电层中，使得所述第二介电层通过所述第一介电层的一部分与所述气隙分离。在一些实施例中，S/D部件的一部分设置在两个半导体层之间以接触所述第二介电层。在一些实施例中，第一介电层具有第一介电常数，并且所述第二介电层具有第二介电常数，并且其中，所述第二介电常数大于所述第一介电常数。
上面论述了若干实施例的部件，使得本领域技术人员可以更好地理解本发明的各个实施例。本领域技术人员应该理解，他们可以很容易地使用本发明作为基础来设计或更改其他用于达到与本文所介绍实施例相同的目的和/或实现相同优点的工艺和结构。本领域普通技术人员也应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (20)

1.一种形成半导体结构的方法，包括：
在从半导体衬底突出的鳍上方形成伪栅极堆叠件，其中，所述鳍包括交替的沟道层和非沟道层的多层堆叠件；
在所述多层堆叠件中形成源极/漏极凹槽；
对每个非沟道层的一部分进行开槽以形成沟槽；
在所述沟槽中沉积内部间隔件层，其中，该沉积在所述内部间隔件层中形成气隙，并且其中，所述内部间隔件层的形成在所述气隙与所述沟槽的侧壁之间的部分的厚度朝着所述沟槽的开口增加；
在所述源极/漏极凹槽中和所述内部间隔件层上方形成外延源极/漏极部件；
从所述多层堆叠件去除所述非沟道层以形成置于所述内部间隔件层之间的另一开口；以及
在所述另一开口中并代替所述伪栅极堆叠件形成金属栅极堆叠件。
2.根据权利要求1所述的形成半导体结构的方法，还包括：在形成所述外延源极/漏极部件之前，去除所述内部间隔件层的形成在所述沟道层的侧壁上的部分。
3.根据权利要求1所述的形成半导体结构的方法，其中，沉积所述内部间隔件层包括以高脉冲模式实施原子层沉积工艺。
4.根据权利要求2所述的形成半导体结构的方法，还包括：在从所述沟道层的侧壁去除所述内部间隔件层的部分之前，对所述内部间隔件层进行退火。
5.根据权利要求1所述的形成半导体结构的方法，其中，所述外延源极/漏极部件的部分延伸超过所述沟道层的侧壁以使所述外延源极/漏极部件接触所述沟道层的侧面和上下表面。
6.根据权利要求1所述的形成半导体结构的方法，其中，沉积所述内部间隔件层使得所述气隙被所述内部间隔件层部分地包围，使得形成所述外延源极/漏极部件密封所述气隙。
7.根据权利要求1所述的形成半导体结构的方法，其中，沉积所述内部间隔件层使得所述气隙完全嵌入所述内部间隔件层中，使得所述内部间隔件层的一部分设置在所述气隙和所述外延源极/漏极部件之间。
8.根据权利要求1所述的形成半导体结构的方法，其中，所述内部间隔件层是第一内部间隔件层，所述方法还包括在形成所述外延源极/漏极部件之前，在所述第一内部间隔件层上方形成第二内部间隔件层。
9.一种半导体结构，包括：
半导体层的堆叠件，设置在衬底上方；
金属栅极堆叠件，具有设置在所述半导体层的堆叠件上方的顶部部分和与所述半导体层的堆叠件交错的底部部分；
内部间隔件，设置在所述金属栅极堆叠件的底部部分的侧壁上；
气隙，被包围在所述内部间隔件中；以及
外延源极/漏极部件，设置在所述内部间隔件上方并与所述金属栅极堆叠件相邻，
其中，所述内部间隔件的与所述气隙相邻的部分的厚度在朝向所述外延源极/漏极部件的方向上增加。
10.根据权利要求9所述的半导体结构，其中，所述内部间隔件是第一内部间隔件，所述半导体结构还包括设置在所述第一内部间隔件和所述外延源极/漏极部件之间的第二内部间隔件。
11.根据权利要求10所述的半导体结构，其中，所述第二内部间隔件密封所述气隙。
12.根据权利要求10所述的半导体结构，其中，所述第二内部间隔件呈现出比所述第一内部间隔件更高的介电常数。
13.根据权利要求9所述的半导体结构，其中，与所述内部间隔件接触的外延源极/漏极部件的部分设置在两个半导体层之间。
14.根据权利要求9所述的半导体结构，其中，所述气隙完全嵌入所述内部间隔件中，使得所述外延源极/漏极部件通过所述内部间隔件的一部分与所述气隙分离。
15.根据权利要求9所述的半导体结构，其中，所述外延源极/漏极部件密封所述气隙。
16.根据权利要求10所述的半导体结构，其中，所述第一内部间隔件包括SiOCN，并且所述第二内部间隔件包括SiON。
17.一种半导体结构，包括：
半导体层，设置在衬底上方；
高k金属栅极堆叠件，设置在所述半导体层之间；
源极/漏极部件，设置为与所述高k金属栅极堆叠件相邻；以及
内部间隔件，配置为将所述源极/漏极部件与所述高k金属栅极堆叠件分离，其中，所述内部间隔件包括设置在所述高k金属栅极堆叠件的侧壁上的第一介电层、设置在所述第一介电层中的气隙和设置在所述第一介电层上方的第二介电层，
其中，所述半导体层突出进入所述源极/漏极部件中，以使所述源极/漏极部件接触所述半导体层的侧面和上下表面。
18.根据权利要求17所述的半导体结构，其中，所述气隙嵌入所述第一介电层中，使得所述第二介电层通过所述第一介电层的一部分与所述气隙分离。
19.根据权利要求17所述的半导体结构，其中，所述源极/漏极部件的一部分设置在两个半导体层之间以接触所述第二介电层。
20.根据权利要求17所述的半导体结构，其中，所述第一介电层具有第一介电常数，并且所述第二介电层具有第二介电常数，并且
其中，所述第二介电常数大于所述第一介电常数。
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