CN113190174A - Control method and device of SRAM with zero waiting period - Google Patents

Control method and device of SRAM with zero waiting period Download PDF

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Publication number
CN113190174A
CN113190174A CN202110450783.3A CN202110450783A CN113190174A CN 113190174 A CN113190174 A CN 113190174A CN 202110450783 A CN202110450783 A CN 202110450783A CN 113190174 A CN113190174 A CN 113190174A
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write
state
condition
met
sram
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CN113190174B (en
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王锐
陆思茗
李建军
王亚波
莫军
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Unicmicro Guangzhou Co ltd
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Unicmicro Guangzhou Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/781—On-chip cache; Off-chip memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device

Abstract

The invention provides a control method and a device of a zero-waiting period SRAM (static random access memory). three states are added besides basic read, write and idle states, and on the premise of keeping the same instruction execution effect as the prior art, the problem that the read-after-write operation needs to wait for at least one more period is avoided by controlling the SRAM controller to read and then write and latch the write operation. Therefore, by implementing the invention, the execution efficiency of the instruction can be greatly improved, and the capability of the SOC system for running the program is effectively improved.

Description

Control method and device of SRAM with zero waiting period
Technical Field
The invention relates to the technical field of storage control, in particular to a control method and a control device of a zero-waiting-period SRAM (static random access memory).
Background
Static Random-Access Memory (SRAM) is a Memory commonly used in SOC systems. The static state in the SRAM mainly means that data in the memory can be kept all the time as long as power is not lost, and the data in the memory can be lost after the power is lost. The SRAM has high access speed and is generally used for storing some temporary data of the CPU, so that the CPU has higher speed and convenience in executing operation; the SRAM can also be used for data or instruction caching between a high-speed CPU and a low-speed memory, and the efficiency of reading data in the low-speed memory by the CPU can be improved. Therefore, the access speed of the SRAM determines the performance of the SOC system and the execution efficiency of the CPU, and the function of the SRAM controller determines the access speed of the SRAM memory.
In the AHB protocol, data is always delayed by one clock from its corresponding address and control signals. When the host writes and then reads the SRAM memory, the SRAM controller needs to latch an address of the write operation and some control signals first, and then actually write the data into the SRAM memory after the data written on the bus is ready. According to the pipeline operation on the AHB bus, a read operation following a write operation needs to wait for one more clock cycle, and can be executed after the SRAM controller actually writes the write data into the SRAM memory. The read data is read by the bus in the next cycle.
The read-after-write operation takes at least one more cycle in the process of waiting for data writing, thereby influencing the read-write speed of the SRAM and greatly reducing the instruction execution efficiency of the CPU.
Disclosure of Invention
The invention aims to provide a control method and a control device of a zero-waiting-period SRAM (static random access memory), which aim to solve the problem that at least one clock period needs to be waited when the SRAM is read after being written, thereby greatly improving the execution efficiency of instructions and improving the capability of running programs of an SOC (system on chip).
In order to solve the above technical problem, an embodiment of the present invention provides a method for controlling a zero-latency SRAM, including:
when the SRAM controller is in an idle state, if a first condition is met, controlling the SRAM controller to enter a reading state; if the second condition is met, controlling the SRAM controller to enter a writing state; when the AHB selects an SRAM address area, the bus is idle and the AHB write enable signal is invalid; the second condition is that when the AHB bus selects an SRAM address area, the bus is idle and an AHB bus write enable signal is valid;
when the SRAM controller is in a read state, if the second condition is met, the SRAM controller is controlled to enter a write state; if the first condition is met, controlling the SRAM controller to be maintained in a read state; if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter an idle state;
when the SRAM controller is in a writing state, if the first condition is met, the SRAM controller is controlled to enter a read-after-write state; if the second condition is met, controlling the SRAM controller to be maintained in a writing state; if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter an idle state; in a read-after-write state, the SRAM controller preferentially executes a current read operation and latches data of a previous write operation;
when the SRAM controller is in a read-after-write state, if the second condition is met, controlling the SRAM controller to enter a write-after-write state; if the first condition is met, controlling the SRAM controller to maintain a read-after-write state; if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter a post-write idle state; in a write-after-write state, the SRAM controller writes previously latched write operation data into an SRAM memory; in an idle state after writing, the SRAM controller writes the data of the write operation latched before into an SRAM memory;
when the SRAM controller is in a write-after-write state, if the second condition is met, controlling the SRAM controller to enter the write state; if the first condition is met, controlling the SRAM controller to enter a read-after-write state; if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter an idle state;
when the SRAM controller is in a post-write idle state, if the second condition is met, controlling the SRAM controller to enter a write state; if the first condition is met, controlling the SRAM controller to enter a reading state; and if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter an idle state.
Further, when the AHB bus does not select the SRAM address area, the SRAM controller is in an idle state by default.
Further, the data of the write operation comprises a write operation address, write data and a data transmission width.
In order to solve the same technical problem, the present invention further provides a control device of a zero-latency SRAM, comprising:
the SRAM controller is used for controlling the SRAM controller to enter a read state if a first condition is met when the SRAM controller is in an idle state; if the second condition is met, controlling the SRAM controller to enter a writing state; when the AHB selects an SRAM address area, the bus is idle and the AHB write enable signal is invalid; the second condition is that when the AHB bus selects an SRAM address area, the bus is idle and an AHB bus write enable signal is valid;
the read state control module is used for controlling the SRAM controller to enter a write state if the second condition is met when the SRAM controller is in a read state; if the first condition is met, controlling the SRAM controller to be maintained in a read state; if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter an idle state;
the write state control module is used for controlling the SRAM controller to enter a read-after-write state if the first condition is met when the SRAM controller is in the write state; if the second condition is met, controlling the SRAM controller to be maintained in a writing state; if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter an idle state; in a read-after-write state, the SRAM controller preferentially executes a current read operation and latches data of a previous write operation;
the read-after-write state control module is used for controlling the SRAM controller to enter a write-after-write state if the second condition is met when the SRAM controller is in the read-after-write state; if the first condition is met, controlling the SRAM controller to maintain a read-after-write state; if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter a post-write idle state; in a write-after-write state, the SRAM controller writes previously latched write operation data into an SRAM memory; in an idle state after writing, the SRAM controller writes the data of the write operation latched before into an SRAM memory;
the write-after-write state control module is used for controlling the SRAM controller to enter a write state if the second condition is met when the SRAM controller is in the write-after-write state; if the first condition is met, controlling the SRAM controller to enter a read-after-write state; if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter an idle state;
the after-write idle state control module is used for controlling the SRAM controller to enter a write state if the second condition is met when the SRAM controller is in the after-write idle state; if the first condition is met, controlling the SRAM controller to enter a reading state; and if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter an idle state.
Further, when the AHB bus does not select the SRAM address area, the SRAM controller is in an idle state by default.
Further, the data of the write operation comprises a write operation address, write data and a data transmission width.
Compared with the prior art, the invention has the following beneficial effects:
the embodiment of the invention provides a control method and a control device of a zero-waiting period SRAM (static random access memory), which are characterized in that three states are added besides basic read, write and idle states, and on the premise of keeping the same instruction execution effect as the prior art, the SRAM controller is controlled by reading and writing firstly and latching the write operation, so that the problem that the read operation needs to wait for at least one period after the write operation is avoided. Therefore, by implementing the invention, the execution efficiency of the instruction can be greatly improved, and the capability of the SOC system for running the program is effectively improved.
Drawings
FIG. 1 is a flow chart illustrating a method for controlling a zero-latency SRAM according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a software implementation flow of a control method for a zero-latency SRAM according to an embodiment of the present invention;
FIG. 3 is a timing diagram illustrating a read/write operation according to the prior art according to an embodiment of the present invention;
FIG. 4 is a timing diagram illustrating read/write operations of a method for controlling a zero latency SRAM according to an embodiment of the present invention;
FIG. 5 is a timing diagram illustrating another read/write operation of the control method of the SRAM with zero wait period according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a control device of a zero-latency SRAM according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-2, an embodiment of the present invention provides a method for controlling a zero-latency SRAM, including:
s1, when the SRAM controller is in an Idle state (represented as "Idle" in FIG. 2), if a first condition is met, controlling the SRAM controller to enter a reading state; if the second condition is met, controlling the SRAM controller to enter a writing state; wherein the first condition is that when the AHB bus selects the SRAM address area, the bus is idle and the AHB bus write enable signal is inactive (as shown in fig. 2, the first condition is satisfied and is denoted as "Valid ═ 1& Hwrite ═ 0"); the second condition is that when the AHB bus selects the SRAM address area, the bus is free and the AHB bus write enable signal is active (as shown in fig. 2, the first condition is satisfied and is denoted as "Valid-1 & Hwrite-1"). In the embodiment of the present invention, further, when the AHB bus does not select the SRAM address area, the SRAM controller is in an idle state by default.
S2, when the SRAM controller is in a Read state (indicated as "Read" in fig. 2), if the second condition is satisfied, controlling the SRAM controller to enter a write state; if the first condition is met, controlling the SRAM controller to be maintained in a read state; if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter an idle state;
s3, when the SRAM controller is in a writing state (indicated as 'Write' in FIG. 2), if the first condition is met, controlling the SRAM controller to enter a read-after-Write state; if the second condition is met, controlling the SRAM controller to be maintained in a writing state; if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter an idle state; and in the read-after-write state, the SRAM controller preferentially executes the current read operation and latches the data of the previous write operation. In the embodiment of the present invention, further, the data of the write operation includes a write operation address, write data, and a data transfer width.
S4, when the SRAM controller is in a Read-after-Write state (indicated as "Read _ Stall _ Write" in fig. 2), if the second condition is satisfied, controlling the SRAM controller to enter a Write-after-Write state; if the first condition is met, controlling the SRAM controller to maintain a read-after-write state; if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter a post-write idle state; in a write-after-write state, the SRAM controller writes previously latched write operation data into an SRAM memory; in an idle state after writing, the SRAM controller writes the data of the write operation latched before into an SRAM memory;
s5, when the SRAM controller is in a Write-after-Write state (denoted as "Write _ And _ Write _ stacked" in fig. 2), controlling the SRAM controller to enter a Write state if the second condition is satisfied; if the first condition is met, controlling the SRAM controller to enter a read-after-write state; if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter an idle state;
s6, when the SRAM controller is in an Idle state after writing (denoted as "Idle _ And _ Write _ Stall" in fig. 2), if the second condition is satisfied, controlling the SRAM controller to enter a Write state; if the first condition is met, controlling the SRAM controller to enter a reading state; and if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter an idle state.
Referring to fig. 2-5, based on the above solutions, in order to better understand the control method of the zero-latency SRAM provided in the embodiments of the present invention, the following detailed descriptions are provided:
the design of the embodiment of the invention is suitable for the SOC system using the AHB protocol.
The basic principle of the scheme is as follows: and under different read-write states of the SRAM controller, data transmission is carried out on the SRAM memory interface and the AHB interface according to an AHB protocol, so that the system can normally run.
The working process of the state machine of the controller under the scheme is as follows (the software implementation flow chart is shown in figure 2):
1. when the AHB bus does not select the SRAM address area, the SRAM controller is in an Idle state (Idle) by default; when the AHB bus selects the SRAM address area, the bus is idle (the HreadyIn signal is high, identified as "Valid ═ 1" in the drawing), and the AHB bus write enable signal is inactive, the Read state is entered (Read).
2. In a reading state, if the AHB selects an SRAM address area, the bus is idle (the HreadyIn signal is high), and the AHB Write enable signal is effective, and enters a writing state (Write); if the AHB bus keeps selecting the SRAM address area, the bus is idle (HreadyIn signal is high), and the AHB bus write enable signal is invalid, the controller will continue to stay in the Read state (Read); if the above two conditions are not met, the controller will return to the Idle state (Idle).
3. In the Write state (Write), if the AHB bus selects the SRAM address area, the bus is idle (the HreadyIn signal is high), and the AHB bus Write enable signal is inactive, and then the Read-after-Write state (Read _ Stall _ Write) is entered; if the AHB bus keeps selecting the SRAM address area, the bus is idle (the HreadyIn signal is high), and the AHB bus Write enable signal is effective, the controller will continue to stay in the Write state (Write); if the above two conditions are not met, the controller will return to the Idle state (Idle).
4. If the Write command is followed by the Read command, the Read _ Stall _ Write state is entered, and in this state, the controller will perform the Read operation first and save the previous Write operation contents, including the address of the Write operation, the Write data and the data transmission width.
In the Read-after-Write state (Read _ Stall _ Write), if the AHB bus selects the SRAM address area, the bus is idle (the HreadyIn signal is high), And the AHB bus Write enable signal is active, entering the Write _ And _ Write _ staged state; if the AHB bus keeps selecting the SRAM address area, the bus is idle (HreadyIn signal is high), and the AHB bus Write enable signal is invalid, the controller will continue to stay in the Read-after-Write state (Read _ Stall _ Write); if the above two conditions are not met, the controller will enter the Idle _ And _ Write _ Stall state.
5. If the read operation is completed after the Write operation is latched, And a Write operation is immediately performed, the state of Write _ add _ Write _ stacked is entered, And in this state, the controller actually writes the previously latched Write data into the SRAM memory.
In the Write _ add _ Write _ stacked state, if the AHB bus selects the SRAM address area, the bus is idle (the HreadyIn signal is high), And the AHB bus Write enable signal is active, entering the Write state (Write); if the AHB bus remains in the selected SRAM address region, the bus is idle (HreadyIn signal is high), and the AHB bus Write enable signal is inactive, entering a Read-after-Write state (Read _ Stall _ Write).
6. If the read operation is completed after the Write operation is latched, And the Write operation is immediately Idle, the Idle _ And _ Write _ Stall state is entered, And in this state, the controller actually writes the previously latched Write data into the SRAM memory.
In Idle _ And _ Write _ Stall state, if the AHB bus selects the SRAM address area, the bus is Idle (HreadyIn signal is high), And the AHB bus Write enable signal is effective, entering into Write state (Write); if the AHB bus selects the SRAM address area, the bus is idle (HreadyIn signal is high), and the AHB bus write enable signal is invalid, entering a Read state (Read). If the above two conditions are not met, the controller will enter an Idle (Idle) state.
The above principle describes a flow chart on software implementation as shown in fig. 2.
Referring to fig. 3 (timing diagram for read/write operations), it should be noted that, to complete a simple transmission according to the AHB transmission protocol, the host first needs to drive the address bus and the control bus for data transmission after the rising edge of the first HCLK, including signals such as the write enable signal and the transmission data width. This address data and control data are then sampled from the opportunity on the rising edge of the second HCLK. After the slave samples the corresponding address and control, the slave can start to drive a response signal which is fed back to the master to tell the master whether the master is busy or not, and the master needs to wait in the next period. The master will sample the slave's response signal on the rising edge of the third HCLK. If host wait is not needed, after the 2 nd HCLK rising edge, the host writes the data to be written to the bus or writes the data read by the host to the bus from the opportunity. The data is always delayed by one clock from its corresponding address and control signals, etc.
For the SRAM controller, the read and write timing of the SRAM memory is different from that of the AHB bus. When reading SRAM memory data, after the address signal is changed, SRAM samples the address signal at the next HCLK rising edge, and returns the data corresponding to the corresponding address, the host will sample the data to be read at the next HCLK rising edge, the reading time sequence is consistent with AHB protocol; when data is written into the SRAM, an address signal, a data signal and a write enable signal are required to be written simultaneously, the write timing is different from the AHB write timing, so that the SRAM controller needs to latch the address signal and the write enable signal after the rising edge of the first HCLK of the AHB bus, and then the latched write address, write enable signal and the like can be written into the SRAM along with the write data written by the bus after the rising edge of the second HCLK.
As described above, because of the characteristics of the AHB protocol, the SRAM controller can only write DATA into the SRAM memory in the DATA phase of a write operation, and if the host initiates a read operation (B) immediately after initiating a write operation (a), the SRAM controller needs to wait until the previously initiated write operation is actually written into the SRAM (the a address and DATA a are both ready to be written into the SRAM), and then the SRAM controller can address with the subsequent read address (SADDR into the B address), and then read the corresponding DATA (DATA B) from the next HCLK. It can be seen that the read-after-write operation will take at least one more cycle waiting for the data write, thereby affecting the SRAM read-write rate and the CPU instruction execution efficiency.
To solve the latency problem, the present invention provides a zero latency SRAM controller design, which can achieve the same instruction execution effect in the above scenario, but does not require a one-cycle latency, and thus achieves a zero latency. The method of the present design will utilize the state machine workflow described above. In addition to the basic read, write, idle states, 3 states are added. In the above scenario, a method of reading first and then writing is adopted, and a writing address, data and the like are latched in advance, so as to realize a function of zero waiting period. The timing diagram of the read/write operation of the design is as follows. The design read/write operation timing sequence of the scheme of the invention is shown in figure 4.
As shown in fig. 4, the host initiates three operations a, B, and C on the AHB bus in sequence. The a operation is a write operation followed by the B, C operation as a read operation.
1. After the first HCLK rising edge, the SRAM controller detects the selection of the SRAM address and the Write enable signal, and determines that the next state is a Write state (Write);
2. after the rising edge of the second HCLK, the SRAM controller latches the address A, receives the B operation Read operation on the bus, judges that the next state is Read after Write (Read _ Stall _ Write), and at the moment, the controller executes the B operation first and sends the address B to the SRAM memory;
the presence of the rising edge of the third HCLK sample into the SRAM to the B address and strobe will return data (B). After the rising edge, the controller receives the C operation Read operation on the bus, and judges that the next state is Read-after-Write (Read _ Stall _ Write), at the moment, the controller firstly executes the C operation and sends the C address into the SRAM. On this HCLK rising edge, the controller detects that the present state is Write and the next state is Read _ Stall _ Write, i.e., the previously latched values of APhase _ HADDR and HWDATA are latched into Stalled _ HADDR and Stalled _ HWDATA.
4. After the fourth HCLK rising edge, the SRAM memory samples the C address and strobe signal, which will return data (C). After the rising edge, the host no longer gates the SRAM memory address, And the controller determines that the next state is Idle _ And _ Write _ Stall, which indicates that the next state is not a read state And a Write operation can be performed, And at this time, the controller fetches the data latched in the stacked _ HADDR And stacked _ HWDATA And actually writes the a data into the a address.
In the above scenario, the design can implement read-after-write operation, and it can be seen that the written and read addresses are different. One more scenario is described below:
referring to fig. 5, the host initiates three operations a, B, and a on the AHB bus in sequence. The A operation is a write operation followed by the B, A operation is a read operation.
1. After the first HCLK rising edge, the SRAM controller detects the selection of the SRAM address and the Write enable signal, and determines that the next state is a Write state (Write);
2. after the rising edge of the second HCLK, the SRAM controller latches the address A, receives the B operation Read operation on the bus, judges that the next state is Read after Write (Read _ Stall _ Write), and at the moment, the controller executes the B operation first and sends the address B to the SRAM memory;
the presence of the rising edge of the third HCLK sample into the SRAM to the B address and strobe will return data (B). After the rising edge, the controller receives the A operation Read operation on the bus, and determines that the next state is Read-after-Write (Read _ Stall _ Write), at this time, the controller will execute the A operation first and send the A address into the SRAM memory. Meanwhile, the controller detects that the current state is Write and the next state is Read _ Stall _ Write, namely, the previously latched APhase _ HADDR value and HWDATA value are latched into the staged _ HADDR and the staged _ HWDATA.
4. After the fourth HCLK rising edge, the controller latches the read address of operation a, and determines that the read address is consistent with the write address latched in the stacked _ HADDR, which indicates that the data read by this operation should be the data to be written into the address a. At this time, the controller pulls up the Read _ match _ reserved signal, ignores the data Read in the previous cycle, and directly writes the data stored in the reserved _ HWDATA to the bus. In this period, the host no longer gates the SRAM memory address, the controller determines that the next state is Idle _ And _ Write _ Stall, which indicates that the next state is not a read state, And a Write operation can be performed, And at this time, the controller fetches the data latched in the staged _ HADDR And the staged _ HWDATA, And actually writes the a data into the a address.
Therefore, the design scheme of the invention solves the problem that the read-write operation of the SRAM does not need waiting period after writing under the condition of consistent and inconsistent read-write addresses, and realizes the design of the SRAM controller with zero waiting period. The execution efficiency of the instruction is greatly improved, and the capability of running the program of the SOC system is improved.
It should be noted that the above method or flow embodiment is described as a series of acts or combinations for simplicity, but those skilled in the art should understand that the present invention is not limited by the described acts or sequences, as some steps may be performed in other sequences or simultaneously according to the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are exemplary embodiments and that no single embodiment is necessarily required by the inventive embodiments.
Referring to fig. 6, to solve the same technical problem, the present invention further provides a control device of a zero-latency SRAM, including:
the SRAM controller comprises an idle state control module 1, a read state control module and a data processing module, wherein the idle state control module is used for controlling the SRAM controller to enter the read state if a first condition is met when the SRAM controller is in an idle state; if the second condition is met, controlling the SRAM controller to enter a writing state; when the AHB selects an SRAM address area, the bus is idle and the AHB write enable signal is invalid; the second condition is that when the AHB bus selects an SRAM address area, the bus is idle and an AHB bus write enable signal is valid;
the read state control module 2 is configured to, when the SRAM controller is in a read state, control the SRAM controller to enter a write state if the second condition is met; if the first condition is met, controlling the SRAM controller to be maintained in a read state; if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter an idle state;
the write state control module 3 is configured to, when the SRAM controller is in a write state, control the SRAM controller to enter a read-after-write state if the first condition is met; if the second condition is met, controlling the SRAM controller to be maintained in a writing state; if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter an idle state; in a read-after-write state, the SRAM controller preferentially executes a current read operation and latches data of a previous write operation;
a read-after-write state control module 4, configured to, when the SRAM controller is in a read-after-write state, control the SRAM controller to enter a write-after-write state if the second condition is met; if the first condition is met, controlling the SRAM controller to maintain a read-after-write state; if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter a post-write idle state; in a write-after-write state, the SRAM controller writes previously latched write operation data into an SRAM memory; in an idle state after writing, the SRAM controller writes the data of the write operation latched before into an SRAM memory;
a write-after-write state control module 5, configured to, when the SRAM controller is in a write-after-write state, control the SRAM controller to enter a write state if the second condition is met; if the first condition is met, controlling the SRAM controller to enter a read-after-write state; if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter an idle state;
a post-write idle state control module 6, configured to, when the SRAM controller is in a post-write idle state, control the SRAM controller to enter a write state if the second condition is met; if the first condition is met, controlling the SRAM controller to enter a reading state; and if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter an idle state.
Further, when the AHB bus does not select the SRAM address area, the SRAM controller is in an idle state by default.
Further, the data of the write operation comprises a write operation address, write data and a data transmission width.
It can be understood that the foregoing device embodiment corresponds to the method embodiment of the present invention, and the control device of the zero wait period SRAM provided in the embodiment of the present invention can implement the control method of the zero wait period SRAM provided in any method embodiment of the present invention.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.

Claims (6)

1. A control method of a zero-waiting period SRAM is characterized by comprising the following steps:
when the SRAM controller is in an idle state, if a first condition is met, controlling the SRAM controller to enter a reading state; if the second condition is met, controlling the SRAM controller to enter a writing state; when the AHB selects an SRAM address area, the bus is idle and the AHB write enable signal is invalid; the second condition is that when the AHB bus selects an SRAM address area, the bus is idle and an AHB bus write enable signal is valid;
when the SRAM controller is in a read state, if the second condition is met, the SRAM controller is controlled to enter a write state; if the first condition is met, controlling the SRAM controller to be maintained in a read state; if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter an idle state;
when the SRAM controller is in a writing state, if the first condition is met, the SRAM controller is controlled to enter a read-after-write state; if the second condition is met, controlling the SRAM controller to be maintained in a writing state; if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter an idle state; in a read-after-write state, the SRAM controller preferentially executes a current read operation and latches data of a previous write operation;
when the SRAM controller is in a read-after-write state, if the second condition is met, controlling the SRAM controller to enter a write-after-write state; if the first condition is met, controlling the SRAM controller to maintain a read-after-write state; if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter a post-write idle state; in a write-after-write state, the SRAM controller writes previously latched write operation data into an SRAM memory; in an idle state after writing, the SRAM controller writes the data of the write operation latched before into an SRAM memory;
when the SRAM controller is in a write-after-write state, if the second condition is met, controlling the SRAM controller to enter the write state; if the first condition is met, controlling the SRAM controller to enter a read-after-write state; if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter an idle state;
when the SRAM controller is in a post-write idle state, if the second condition is met, controlling the SRAM controller to enter a write state; if the first condition is met, controlling the SRAM controller to enter a reading state; and if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter an idle state.
2. The method of claim 1, wherein when the AHB bus does not select the SRAM address region, the SRAM controller is in an idle state by default.
3. The method of claim 1, wherein the data of the write operation comprises a write operation address, write data, and a data transfer width.
4. A control apparatus for a zero latency SRAM, comprising:
the SRAM controller is used for controlling the SRAM controller to enter a read state if a first condition is met when the SRAM controller is in an idle state; if the second condition is met, controlling the SRAM controller to enter a writing state; when the AHB selects an SRAM address area, the bus is idle and the AHB write enable signal is invalid; the second condition is that when the AHB bus selects an SRAM address area, the bus is idle and an AHB bus write enable signal is valid;
the read state control module is used for controlling the SRAM controller to enter a write state if the second condition is met when the SRAM controller is in a read state; if the first condition is met, controlling the SRAM controller to be maintained in a read state; if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter an idle state;
the write state control module is used for controlling the SRAM controller to enter a read-after-write state if the first condition is met when the SRAM controller is in the write state; if the second condition is met, controlling the SRAM controller to be maintained in a writing state; if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter an idle state; in a read-after-write state, the SRAM controller preferentially executes a current read operation and latches data of a previous write operation;
the read-after-write state control module is used for controlling the SRAM controller to enter a write-after-write state if the second condition is met when the SRAM controller is in the read-after-write state; if the first condition is met, controlling the SRAM controller to maintain a read-after-write state; if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter a post-write idle state; in a write-after-write state, the SRAM controller writes previously latched write operation data into an SRAM memory; in an idle state after writing, the SRAM controller writes the data of the write operation latched before into an SRAM memory;
the write-after-write state control module is used for controlling the SRAM controller to enter a write state if the second condition is met when the SRAM controller is in the write-after-write state; if the first condition is met, controlling the SRAM controller to enter a read-after-write state; if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter an idle state;
the after-write idle state control module is used for controlling the SRAM controller to enter a write state if the second condition is met when the SRAM controller is in the after-write idle state; if the first condition is met, controlling the SRAM controller to enter a reading state; and if the first condition is not met and the second condition is not met, controlling the SRAM controller to enter an idle state.
5. The apparatus of claim 4, wherein the SRAM controller is in an idle state by default when the AHB bus does not select the SRAM address region.
6. The control device of the zero-latency SRAM as claimed in claim 4, wherein the data of the write operation comprises a write operation address, write data and a data transfer width.
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