CN113178428B - Interconnection structure, three-dimensional memory device and manufacturing method of interconnection structure - Google Patents
Interconnection structure, three-dimensional memory device and manufacturing method of interconnection structure Download PDFInfo
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- CN113178428B CN113178428B CN202110416366.7A CN202110416366A CN113178428B CN 113178428 B CN113178428 B CN 113178428B CN 202110416366 A CN202110416366 A CN 202110416366A CN 113178428 B CN113178428 B CN 113178428B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
Abstract
The invention provides an interconnection structure, a three-dimensional memory device and a manufacturing method of the interconnection structure. The invention moves the position of the contact part from the center of the high-voltage wire/low-voltage wire to the center of the bonding pad, thereby eliminating the breakdown point between the contact part and the virtual wire.
Description
The application is a divisional application provided for a patent application with an application date of 09 and 05 in 2019 and an application number of 201910836140.5, and is named as an interconnection structure, a three-dimensional memory device and a manufacturing method of the interconnection structure.
Technical Field
The invention belongs to the field of semiconductor integrated circuits, and relates to an interconnection structure, a three-dimensional memory device and a manufacturing method of the interconnection structure.
Background
In a three-dimensional logic NAND flash memory (3D NAND) technology, as metal traces on an upper layer of a high voltage metal oxide semiconductor (HV MOS) in a complementary metal oxide semiconductor Page Buffer circuit (CMOS Page Buffer circuit) become denser, only the width of the metal traces and the distance between the metal traces are continuously reduced, but the size of a contact portion (contact) cannot be correspondingly reduced, and when the width of the contact portion is greater than the width of the metal traces, the problem of early breakdown between the contact portion and a dummy (dummy) trace is easily caused. The virtual wiring does not play a role in actual circuit connection, and the purpose of the virtual wiring is to increase the density of the metal layer and prevent insufficient etching or excessive etching during etching.
The current solution is mainly to increase the distance between the metal wirings, thereby reducing the voltage difference between the two metal wirings, but as the number of layers of the 3D NAND technology is more and more, the number of the wirings at the back section of the device is greatly increased, and the distance between the wirings is not possible any more.
Therefore, how to design a new interconnect structure, three-dimensional memory device and method for fabricating the same to improve the above-mentioned problems is an important technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, it is an object of the present invention to provide an interconnect structure comprising:
the first wire, the second wire and the third wire are arranged in parallel, and the second wire is positioned between the first wire and the third wire in the arrangement direction of the first wire, the second wire and the third wire;
the first connecting pad is positioned between the first wire and the second wire and is electrically connected with the first wire and the second wire;
the first contact part is positioned below the first connecting pad and electrically connected with the first connecting pad, and the second wire protrudes out of the first contact part in the arrangement direction of the first wire pointing to the second wire.
Optionally, the first wire is a high-voltage wire or a low-voltage wire.
Optionally, the third trace is a virtual trace.
Optionally, the first trace protrudes from the first contact portion along the arrangement direction away from the second trace.
Optionally, the first contact portion is aligned with a center of the first connection pad.
Optionally, the first trace is a high voltage trace, and the interconnect structure further includes:
the fourth wire and the first wire are positioned on the same straight line, and the fifth wire is positioned on any side of the fourth wire and is adjacent to the fourth wire;
the second connecting pad is positioned between the fourth wire and the fifth wire and is electrically connected with the fourth wire and the fifth wire;
and the second contact part is positioned below the second connecting bonding pad and is electrically connected with the second connecting bonding pad, and the fifth wire protrudes out of the second contact part in the direction in which the fourth wire vertically points to the fifth wire.
Optionally, the fourth trace protrudes from the second contact portion in a direction in which the fifth trace points perpendicularly to the fourth trace.
Optionally, the interconnect structure further includes a plurality of sixth traces parallel to the first trace, where the sixth traces are virtual traces, and the plurality of sixth traces are distributed on two sides of the first trace in the arrangement direction.
Optionally, the interconnect structure further includes a seventh trace parallel to the first trace, where the seventh trace is a low-voltage trace, and the seventh trace is located on one side of the first trace in the arrangement direction.
The invention also provides a three-dimensional memory device comprising an interconnect structure as described in any of the above.
The invention also provides a manufacturing method of the interconnection structure, which comprises the following steps:
providing a substrate, and forming a contact layer on the substrate, wherein the contact layer comprises a first contact part;
forming a wiring layer on the contact layer, wherein the wiring layer comprises a first connection bonding pad, and a first wiring, a second wiring and a third wiring which are arranged in parallel;
the second trace is located between the first trace and the third trace in the arrangement direction of the first trace, the second trace and the third trace, the first connection pad is located between the first trace and the second trace and electrically connected with the first trace and the second trace, the first contact portion is located below the first connection pad and electrically connected with the first connection pad, and the second trace protrudes out of the first contact portion in the arrangement direction of the first trace pointing to the second trace.
Optionally, the first wire is a high-voltage wire or a low-voltage wire.
Optionally, the third trace is a virtual trace.
Optionally, the first trace protrudes from the first contact portion along the arrangement direction away from the second trace.
Optionally, the first contact portion is aligned with a center of the first connection pad.
Optionally, the first trace is a high-voltage trace, the trace layer further includes a second connection pad, a fourth trace and a fifth trace that are arranged in parallel, and the contact layer further includes a second contact portion, where the fourth trace is a low-voltage trace, the fourth trace and the first trace are located on the same straight line, the fifth trace is located on any side of the fourth trace and adjacent to the fourth trace, the second connection pad is located between the fourth trace and the fifth trace and electrically connected to the fourth trace and the fifth trace, the second contact portion is located below the second connection pad and electrically connected to the second connection pad, and the fifth trace protrudes from the second contact portion in a direction in which the fourth trace points perpendicularly to the fifth trace.
Optionally, the fourth trace protrudes from the second contact portion in a direction in which the fifth trace points perpendicularly to the fourth trace.
Optionally, the interconnect structure further includes a plurality of sixth traces parallel to the first trace, where the sixth traces are virtual traces, and the plurality of sixth traces are distributed on two sides of the first trace in the arrangement direction.
Optionally, the interconnect structure further includes a seventh trace parallel to the first trace, where the seventh trace is a low-voltage trace, and the seventh trace is located on one side of the first trace in the arrangement direction.
As described above, the interconnection structure, the three-dimensional memory device and the manufacturing method of the interconnection structure of the present invention connect the high voltage trace/low voltage trace and the nearby dummy trace with the connection pad, and move the position of the contact portion from the center of the high voltage trace/low voltage trace to the center of the pad, thereby eliminating the breakdown point between the contact portion and the dummy trace.
Drawings
Fig. 1 shows a layout of a trace plane of an exemplary interconnect structure.
Fig. 2 is an enlarged view of a portion indicated by a dotted frame in fig. 1.
Fig. 3 is a cross-sectional view taken along line a-a' of fig. 2.
Fig. 4 is a layout diagram of a trace plane in an interconnect structure according to a first embodiment of the invention.
Fig. 5 is an enlarged view of a portion shown by a dotted line frame in fig. 4.
Fig. 6 is a cross-sectional view taken along line B-B' of fig. 5.
Fig. 7 is a schematic diagram illustrating the connection between the first contact and the second contact and the connection between the first contact and the drain and the source of the transistor, respectively, in the interconnect structure of the present invention.
Description of the element reference numerals
101 high voltage wiring
102 low voltage routing
103 virtual routing
104 first contact part
105 second contact part
106 low voltage routing
W1Width of wiring
D1Routing pitch
d1Spacing between contact and adjacent trace
201 first trace
202 fourth trace
203 second trace
204 fifth trace
205 first connection pad
206 second connection pad
207 first contact part
208 second contact portion
209 third routing
210 seventh trace
211 drain electrode
212 source electrode
213 polysilicon gate
214 sixth trace
W2Width of wiring
D2Routing pitch
d2Spacing between contact and adjacent trace
Direction of X arrangement
Direction of Y extension
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 7. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 1, a layout plan of traces of an exemplary interconnect structure is shown, where the three-dimensional memory device includes a high voltage trace 101 and a low voltage trace 102 located on a same straight line, and the high voltage trace 101 and the low voltage trace 102 respectively provide a high voltage and a low voltage for a semiconductor device therebelow through a first contact 104 and a second contact 105 therebelow.
As an example, the three-dimensional memory device further includes a plurality of dummy traces 103 distributed on two opposite sides of the high voltage trace 101 and the low voltage trace 102, and lengths of the plurality of dummy traces 103 may be adjusted as needed, which should not unduly limit the protection scope of the present invention.
As an example, the three-dimensional memory device further includes a low voltage trace 106 distributed on the right side of the high voltage trace 101 and the low voltage trace 102, the low voltage trace 106 is used as another low voltage trace, and another trace is spaced between the low voltage trace 106 and the high voltage trace 101 or between the low voltage trace 102.
As shown in fig. 2, an enlarged view of a portion shown by a dotted line frame in fig. 1 is shown. By way of example, trace width W is shown in FIG. 11And a wiring distance D1And the distance d between the contact part and the adjacent routing wire1Wherein, because the width of the top end of the contact part is larger than the width of the trace, the distance d between the contact part and the adjacent trace is ensured1Less than the routing distance D1Therefore, the contact part and the virtual routing are easy to break down in advance. As shown in FIG. 3, is shown as a graph2, wherein a breakdown path between the first contact 104 and the virtual trace 103 is shown with a lightning sign.
Therefore, the present invention improves the above problems by a new design. The technical solution of the present invention will be described below by way of more specific examples.
Example one
In the present embodiment, an interconnect structure is provided, please refer to fig. 4, which shows a layout of a trace plane of the interconnect structure, the interconnect structure includes a first connection pad 205, a first contact 207, and a first trace 201, a second trace 203 and a third trace 209 arranged in parallel, wherein, in the arrangement direction X of the first trace 201, the second trace 203 and the third trace 209, the second trace 203 is located between the first trace 201 and the third trace 209, the first connection pad 205 is located between the first trace 201 and the second trace 203, and electrically connected with the first trace 201 and the second trace 203, the first contact 207 is located below the first connection pad 205, and electrically connected to the first connection pad 205, the second trace 203 protrudes from the first contact portion 207 in the arrangement direction X of the first trace 201 pointing to the second trace 203. The extending direction Y of the first trace 201, the second trace 203 and the third trace 209 is also shown in fig. 4.
It should be noted that, in fig. 4, the first trace 201, the second trace 203 and the third trace 209 are sequentially arranged along the positive X direction, however, in other embodiments, the first trace 201, the second trace 203 and the third trace 209 may also be sequentially arranged along the negative X direction, and the protection scope of the present invention should not be limited too much.
As an example, the first trace 201 is a high voltage trace or a low voltage trace, and is used for providing high voltage and low voltage for the semiconductor device below the first trace through the first contact 207. It should be noted that, here, the high voltage and the low voltage are relative, the voltage of the high voltage wire is greater than the voltage of the low voltage wire, and the voltage value of the high voltage wire and the voltage value of the low voltage wire can be adjusted according to the needs of the actual circuit, which should not unduly limit the protection scope of the present invention.
In this embodiment, the first trace 201 is used as a high voltage trace, the third trace 209 is a virtual trace, and the second trace 203 is also a virtual trace originally, but due to the existence of the first connection pad 205, the second trace 203 is equipotential to the first trace 201, so the second trace 203 can also be regarded as a high voltage trace.
Referring to fig. 5 and 6, fig. 5 is an enlarged view of a portion shown by a dotted frame in fig. 4, and fig. 6 is a cross-sectional view taken along line B-B' of fig. 5.
By way of example, the trace width W is shown in FIG. 52And a wiring distance D2And the distance d between the contact part and the adjacent wire2The trace pitch D is shown in FIG. 62And the distance d between the contact part and the adjacent wire2. Therefore, after the design of the invention is adopted, even if the width of the top end of the contact part is larger than the width of the routing wire, the distance d between the contact part and the adjacent routing wire2Can still be larger than the wiring distance D2Therefore, the problem of breakdown in advance between the contact part and the virtual wiring is avoided.
As an example, the first trace 201 also protrudes out of the first contact portion 207 in the arrangement direction away from the second trace 203.
Referring back to fig. 4, in the present embodiment, the interconnect structure further includes a second connection pad 206, a second contact 208, and a fourth trace 202 and a fifth trace 204 arranged in parallel, wherein the fourth trace 202 is a low voltage trace, and the fourth trace 202 and the first trace 201 are located on the same straight line, the fifth trace 204 is located on either side of the fourth trace 202 and adjacent to the fourth trace 202, the second connection pad 206 is located between the fourth trace 202 and the fifth trace 204, and electrically connected to the fourth trace 202 and the fifth trace 204, the second contact 208 is located under the second connection pad 206, and electrically connected to the second connection pad 206, the fifth trace 204 protrudes from the second contact portion 208 in a direction in which the fourth trace 202 perpendicularly points to the fifth trace 204.
It should be noted that, in fig. 4, the fifth trace 204 is located at the right side of the fourth trace 202, however, in other embodiments, the fifth trace 204 may also be located at the left side of the fourth trace 202, and the scope of the present invention should not be limited too.
For example, the fourth trace 204 protrudes out of the second contact portion 208 in a direction in which the fifth trace 204 points perpendicularly to the fourth trace 202.
As an example, the first contact portion 207 is preferably aligned with the center of the first connection pad 205, and the second contact portion 208 is preferably aligned with the center of the second connection pad 206, so that the distance between the contact portion and the left and right traces is equal, and the distance between the contact portion and the left and right traces is prevented from being relatively small.
As an example, the interconnect structure further includes a plurality of sixth traces 216 parallel to the first trace 201, where the sixth traces 216 are virtual traces, and the plurality of sixth traces 216 are distributed on two sides of the first trace 201 in the arrangement direction, where the length and the layout of the plurality of sixth traces 216 may be adjusted as needed, and the protection scope of the present invention should not be limited too here.
As an example, the interconnect structure further includes a seventh trace 210 parallel to the first trace 201, the seventh trace 210 is a low voltage trace, and the seventh trace 210 is located on one side of the first trace in the arrangement direction. The seventh trace 210 serves as another low voltage trace, and a low voltage can be provided to another element through another contact (not shown).
The interconnection structure of the embodiment connects the high-voltage wire/low-voltage wire and the nearby virtual wire by using the connection pad, and moves the position of the contact part from the center of the high-voltage wire/low-voltage wire to the center of the pad, so that the breakdown point between the contact part and the virtual wire is eliminated.
Example two
In this embodiment, a three-dimensional memory device is provided, which includes any one of the interconnect structures described in the first embodiment.
As an example, a page buffer high voltage NMOS transistor is arranged in the three-dimensional memory device. As shown in fig. 7, a schematic view of the transistor is shown, wherein the transistor includes a polysilicon gate 213, and a drain 211 and a source 212 located at two opposite sides of the polysilicon gate 213, the drain 211 is connected to the lower portion of the first trace 201 (high voltage trace) through the first contact 207, and the source 212 of the transistor is connected to the lower portion of the second trace 202 (low voltage trace) through the second contact 208.
As an example, the voltage of the high voltage wire is greater than or equal to 20V, and the voltage of the low voltage wire is less than or equal to 10V.
EXAMPLE III
The embodiment provides a method for manufacturing a three-dimensional memory device, which comprises the following steps:
s1: providing a substrate, and forming a contact layer on the substrate, wherein the contact layer comprises a first contact part;
s2: forming a wiring layer on the contact layer, wherein the wiring layer comprises a first connection pad and a first wiring, a second wiring and a third wiring arranged in parallel
Specifically, in the arrangement direction of the first trace, the second trace and the third trace, the second trace is located between the first trace and the third trace, the first connection pad is located between the first trace and the second trace and electrically connected to the first trace and the second trace, the first contact portion is located below the first connection pad and electrically connected to the first connection pad, and the second trace protrudes from the first contact portion in the arrangement direction in which the first trace points to the second trace.
As an example, the routing layer may be obtained by forming a conductive layer over the contact layer and patterning the conductive layer.
As an example, the routing layer may also be obtained by forming a mask layer having an opening pattern over the contact layer and forming a conductive material in the opening pattern.
As an example, the first trace is a high voltage trace or a low voltage trace, and the third trace is a dummy trace.
As an example, the first trace protrudes from the first contact portion in the arrangement direction away from the second trace.
As an example, the first contact portion is aligned with a center of the first connection pad.
As an example, the first trace is a high-voltage trace, the trace layer further includes a second connection pad, a fourth trace and a fifth trace that are arranged in parallel, and the contact layer further includes a second contact portion, where the fourth trace is a low-voltage trace, the fourth trace and the first trace are located on the same straight line, the fifth trace is located on any one side of the fourth trace and adjacent to the fourth trace, the second connection pad is located between the fourth trace and the fifth trace and electrically connected to the fourth trace and the fifth trace, the second contact portion is located below the second connection pad and electrically connected to the second connection pad, and the fifth trace protrudes from the second contact portion in a direction in which the fourth trace perpendicularly points to the fifth trace.
As an example, the fourth trace protrudes from the second contact portion in a direction in which the fifth trace points perpendicularly to the fourth trace.
As an example, the interconnect structure further includes a plurality of sixth traces parallel to the first trace, where the sixth traces are virtual traces, and the plurality of sixth traces are distributed on two sides of the first trace in the arrangement direction.
As an example, the interconnect structure further includes a seventh trace parallel to the first trace, the seventh trace is a low voltage trace, and the seventh trace is located on one side of the first trace in the arrangement direction.
The manufacturing method in this embodiment can be used to manufacture the interconnect structure described in the first embodiment or the three-dimensional memory device in the second embodiment, different routing layer designs can be realized by simply changing the lithography pattern, and the manufacturing method has the advantages of simple process and no increase in manufacturing cost.
In summary, the three-dimensional memory device and the manufacturing method thereof according to the present invention connect the high voltage trace/low voltage trace and the nearby dummy trace with the connection pad, and move the position of the contact portion from the center of the high voltage trace/low voltage trace to the center of the pad, so as to eliminate the breakdown point between the contact portion and the dummy trace. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.
Claims (17)
1. An interconnect structure, comprising:
the first routing and the second routing are arranged at intervals;
the first routing, the first connection pad and the second routing are positioned on the same routing layer, and the first routing and the second routing are connected through the first connection pad;
a first contact portion positioned below the first connection pad and electrically connected to the first connection pad;
wherein, the voltage of the first wire is greater than or equal to 20V, the interconnect structure further includes:
the voltage of the fourth wire is less than or equal to 10V, the fourth wire and the first wire are positioned on the same straight line, and the fifth wire is positioned on any side of the fourth wire and is adjacent to the fourth wire;
the second connecting pad is positioned between the fourth wire and the fifth wire and is electrically connected with the fourth wire and the fifth wire;
and a second contact part located below the second connection pad and electrically connected to the second connection pad.
2. The interconnect structure of claim 1, wherein: the second trace protrudes from the first contact portion in a direction pointing to the second trace along the first trace.
3. The interconnect structure of claim 1, wherein: the first wire protrudes from the first contact part along a direction far away from the second wire.
4. The interconnect structure of claim 1, wherein: the first contact portion is aligned with a center of the first connection pad.
5. The interconnect structure of claim 1, wherein: the fifth wire protrudes from the second contact portion in a direction in which the fourth wire points perpendicularly to the fifth wire.
6. The interconnect structure of claim 1, wherein: the fourth wire protrudes from the second contact portion in a direction in which the fifth wire vertically points to the fourth wire.
7. The interconnect structure of claim 1, wherein: the interconnection structure further comprises a plurality of sixth wires arranged at intervals with the first wires, the sixth wires are virtual wires, and the plurality of sixth wires are distributed on two sides of the first wires.
8. The interconnect structure of claim 1, wherein: the interconnection structure further comprises a seventh wire arranged at an interval with the first wire, wherein the voltage of the seventh wire is less than or equal to 10V, and the seventh wire is positioned on one side of the first wire.
9. A three-dimensional memory device, characterized by: the three-dimensional memory device includes the interconnect structure of any one of claims 1 to 8.
10. A manufacturing method of an interconnection structure is characterized by comprising the following steps:
providing a substrate, and forming a contact layer on the substrate, wherein the contact layer comprises a first contact part;
forming a wiring layer on the contact layer, wherein the wiring layer comprises a first connecting bonding pad, and a first wiring and a second wiring which are arranged at intervals;
the first connection pad is located between the first wire and the second wire, the first wire and the second wire are connected through the first connection pad, and the first contact portion is located below the first connection pad and electrically connected with the first connection pad;
wherein, the voltage of the first wire is greater than or equal to 20V, the interconnect structure further includes:
the voltage of the fourth wire is less than or equal to 10V, the fourth wire and the first wire are positioned on the same straight line, and the fifth wire is positioned on any side of the fourth wire and is adjacent to the fourth wire;
the second connecting pad is positioned between the fourth wire and the fifth wire and is electrically connected with the fourth wire and the fifth wire;
and a second contact part located below the second connection pad and electrically connected to the second connection pad.
11. The method of claim 10, further comprising: the second wire protrudes from the first contact portion in a direction in which the first wire points to the second wire.
12. The method of claim 10, wherein: the first wire protrudes from the first contact part along a direction far away from the second wire.
13. The method of claim 10, wherein: the first contact portion is aligned with a center of the first connection pad.
14. The method of claim 10, wherein: the fifth wire protrudes from the second contact portion in a direction in which the fourth wire vertically points to the fifth wire.
15. The method of claim 10, wherein: the fourth wire protrudes from the second contact portion in a direction in which the fifth wire vertically points to the fourth wire.
16. The method of claim 10, wherein: the interconnection structure further comprises a plurality of sixth wires arranged at intervals with the first wires, the sixth wires are virtual wires, and the plurality of sixth wires are distributed on two sides of the first wires.
17. The method of claim 10, wherein: the interconnection structure further comprises a seventh wire arranged at an interval with the first wire, wherein the voltage of the seventh wire is less than or equal to 10V, and the seventh wire is positioned on one side of the first wire.
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| CN202110416366.7A CN113178428B (en) | 2019-09-05 | 2019-09-05 | Interconnection structure, three-dimensional memory device and manufacturing method of interconnection structure |
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| CN201910836140.5A CN110707070B (en) | 2019-09-05 | 2019-09-05 | Interconnection structure, three-dimensional memory device and manufacturing method of interconnection structure |
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| CN206098394U (en) * | 2016-10-14 | 2017-04-12 | 京东方科技集团股份有限公司 | Display substrate, display panel and display device |
| CN109698158A (en) * | 2017-10-20 | 2019-04-30 | 三星电子株式会社 | Integrated circuit and its manufacturing method including through-hole array |
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| US20160233159A1 (en) * | 2015-02-10 | 2016-08-11 | Qualcomm Incorporated | Integrated circuit device including multiple via connectors and a metal structure having a ladder shape |
| US9721663B1 (en) * | 2016-02-18 | 2017-08-01 | Sandisk Technologies Llc | Word line decoder circuitry under a three-dimensional memory array |
| CN206432262U (en) * | 2017-01-25 | 2017-08-22 | 中芯国际集成电路制造（天津）有限公司 | A kind of test structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN206098394U (en) * | 2016-10-14 | 2017-04-12 | 京东方科技集团股份有限公司 | Display substrate, display panel and display device |
| CN109698158A (en) * | 2017-10-20 | 2019-04-30 | 三星电子株式会社 | Integrated circuit and its manufacturing method including through-hole array |
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| CN110707070A (en) | 2020-01-17 |
| CN110707070B (en) | 2021-05-28 |
| CN113178428A (en) | 2021-07-27 |
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