CN117712088A

CN117712088A - IO circuit and chip

Info

Publication number: CN117712088A
Application number: CN202211104807.0A
Authority: CN
Inventors: 廖锦强; 梁洁; 罗庆峰
Original assignee: Nationz Technologies Inc
Current assignee: Nationz Technologies Inc
Priority date: 2022-09-09
Filing date: 2022-09-09
Publication date: 2024-03-15

Abstract

The invention discloses an IO circuit and a chip. The IO circuit comprises an ESD protection device, a first metal layer, a second metal layer, a first wiring layer and a PAD body which are sequentially arranged; the second metal layer comprises a second comb-shaped structure, and the second comb-shaped structure comprises a second base and a plurality of second comb strips; the first wiring layer comprises a first comb-shaped structure, the first comb-shaped structure comprises a first base part and a plurality of first comb strips, the first base part and the second base part are oppositely arranged, and the first comb strips and the second comb strips are oppositely arranged; the first base is electrically connected with the second base through a third through hole, the first comb strip is electrically connected with the corresponding second comb strip through a second through hole, and the second comb strip is electrically connected with the first metal layer through the first through hole; the vertical projection of the second hole area for disposing the second through hole overlaps with the vertical projection of the first hole area for disposing the first through hole; the PAD body is electrically connected with the first base. The technical scheme of the embodiment of the invention improves the ESD protection capability.

Description

IO circuit and chip

Technical Field

The invention relates to the technical field of integrated circuits, in particular to an IO circuit and a chip.

Background

The digital-analog hybrid chip generally includes an input/output (IO) port. The IO port includes a PAD body and an ESD (Electro Static Discharge ) device. The PAD body is connected with the ESD protection device, and the ESD device forms a discharge path to discharge ESD current, so that irreversible damage of the ESD current to the chip is avoided. In the related art, the connection path from the PAD body to the ESD protection device is easy to burn, resulting in reduced ESD protection capability.

Disclosure of Invention

The invention provides an IO circuit and a chip, which are used for improving the layout design defect of a wiring path from a PAD body to an ESD protection device, thereby reducing the possibility of faults on the wiring path from the PAD body to the ESD protection device and improving the ESD protection capability.

According to an aspect of the present invention, there is provided an IO circuit including:

a first metal layer over the ESD protection device; connection terminals of the ESD protection device lead into the first metal layer;

a second metal layer located on a side of the first metal layer away from the ESD protection device; the second metal layer comprises a second comb-like structure comprising a second base and a plurality of second bars;

the first wiring layer is positioned at one side of the second metal layer far away from the first metal layer; the first wiring layer comprises a first comb-shaped structure, the first comb-shaped structure comprises a first base part and a plurality of first comb strips, the first base part and the second base part are oppositely arranged, and the first comb strips and the second comb strips are oppositely arranged;

the first base is electrically connected with the second base through a third through hole, the first comb strip is electrically connected with the corresponding second comb strip through the second through hole, and the second comb strip is electrically connected with the first metal layer through the first through hole; a vertical projection of a second hole area for disposing the second through hole overlaps with a vertical projection of a first hole area for disposing the first through hole;

the PAD body is positioned at one side of the first wiring layer far away from the second metal layer; one end of the PAD body is electrically connected with the first base.

Optionally, the first wiring layer includes a first electrostatic discharge wire and a plurality of first power supply wires, and the extending direction of the first electrostatic discharge wire and the extending direction of the first power supply wires are the same;

the first static electricity discharge wire forms the first base, and a first part structure of the first power supply wire adjacent to the first static electricity discharge wire forms the plurality of first comb strips.

Optionally, a second part of the first power supply trace adjacent to the first electrostatic discharge trace forms a third comb structure, and the third comb structure and the first comb structure form a first interdigital structure;

the third comb structure includes a third base and a plurality of third bars, the third bars having a width less than a width of the first bars.

Optionally, the first power supply wire adjacent to the first electrostatic discharge wire is a first power supply wire, and the first power supply wire adjacent to the first power supply wire is a second first power supply wire;

the third part structure of the first power supply wire and the part structure of the second power supply wire form a fourth comb structure, and the fourth comb structure and the first comb structure form a second interdigital structure;

the fourth comb structure includes a fourth base and a plurality of fourth bars having a width less than a width of the first bars.

the first base is formed by the first static electricity discharge wire and a fourth part structure of the first power supply wire adjacent to the first static electricity discharge wire;

the plurality of first comb bars are formed by a fifth partial structure of the first power supply trace adjacent to the first static electricity discharge trace.

the IO circuit further comprises a second wiring layer, a second wiring layer and an nth wiring layer which are sequentially arranged between the first wiring layer and the PAD body, wherein n is a positive integer greater than or equal to 3;

the mth wiring layer comprises an mth electrostatic discharge wiring and a plurality of mth power supply wirings; m is a positive integer greater than or equal to 2 and less than or equal to n;

the mth electrostatic discharge wire is arranged opposite to the first electrostatic discharge wire, and the mth power supply wire is arranged opposite to the first power supply wire;

one end of the PAD body is electrically connected with the first base part through an nth static electricity discharge wire to a second static electricity discharge wire in sequence.

Optionally, the second sliver is electrically connected with a metal wire in the first metal layer through the first through hole, and the metal wire is opposite to the second sliver.

Optionally, the perpendicular projection of the first base does not overlap with the perpendicular projection of the metal wire; the length of the first sliver is smaller than that of the metal wire, and the length of the metal wire is smaller than that of the second sliver.

Optionally, the metal line is electrically connected to a connection terminal of the ESD protection device through a fourth via; a perpendicular projection of a fourth hole area for providing the fourth through hole overlaps with a perpendicular projection of the first hole area.

Optionally, the first sliver corresponds to the second sliver one by one; the second carding strips are in one-to-one correspondence with the metal wires.

According to another aspect of the present invention, there is provided a chip comprising the IO circuit as described in the above aspect.

According to the technical scheme, the IO circuit comprises a PAD body, an ESD protection device, a first metal layer, a second metal layer and a first wiring layer; the first metal layer is positioned above the ESD protection device; the connection terminal of the ESD protection device is led into the first metal layer; the second metal layer is positioned on one side of the first metal layer away from the ESD protection device; the second metal layer comprises a second comb-shaped structure, and the second comb-shaped structure comprises a second base and a plurality of second comb strips; the first wiring layer is positioned on one side of the second metal layer far away from the first metal layer; the PAD body is positioned on one side of the first wiring layer far away from the second metal layer.

On the basis, the first wiring layer comprises a first comb-shaped structure, the first comb-shaped structure comprises a first base part and a plurality of first comb strips, the first base part and the second base part are oppositely arranged, and the first comb strips and the second comb strips are oppositely arranged; the first base is electrically connected with the second base through a third through hole, the first comb strip is electrically connected with the corresponding second comb strip through a second through hole, and the second comb strip is electrically connected with the first metal layer through the first through hole; a vertical projection of a second hole area for disposing the second through hole overlaps with a vertical projection of a first hole area for disposing the first through hole; one end of the PAD body is electrically connected with the first base. Therefore, on the wiring path from the PAD body to the ESD protection device, the local wiring is not only a single-layer metal wiring, but is always provided with at least two layers of metal wirings, so that the situation that the bottleneck appears in the total width of the local wiring on the wiring path is improved, namely, the layout design defect of the wiring path from the PAD body to the ESD protection device is improved, the possibility of burning caused by electromigration effect on the wiring path is reduced, the possibility of failure on the wiring path from the PAD body to the ESD protection device is reduced, and the ESD protection capability is improved.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram showing a cross-sectional structure of an IO circuit in the related art;

fig. 2 is a schematic top view of an IO circuit according to an embodiment of the present invention;

FIG. 3 is a schematic cross-sectional view of the IO circuit of FIG. 2 along section line CC';

FIG. 4 is a schematic top view of a second metal layer according to an embodiment of the present invention;

fig. 5 is a schematic top view of a first wiring layer according to an embodiment of the present invention;

fig. 6 is a schematic top view of another first trace layer according to an embodiment of the present invention;

fig. 7 is a schematic top view of another first routing layer according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

As mentioned in the background art, the burning condition occurs on the connection path between the PAD body and the ESD protection device, which results in the weakening of the ESD protection capability, and the inventors have long studied to find that the reasons include: fig. 1 is a schematic cross-sectional structure of an IO circuit in the related art, referring to fig. 1, the IO circuit includes an ESD protection device, a first metal film layer M1, a second metal film layer M2, a third metal film layer M3, a fourth metal film layer M4, a fifth metal film layer M5, and a PAD body. The connection terminals (connection terminals, for example, source, drain, gate or Bulk) of the ESD protection device are led into the first metal film layer M1, and the third to fifth metal film layers M3 to M5 are used to provide power supply wirings (power supply wirings are, for example, VSS wirings or VDD wirings). The PAD body is electrically connected to the second metal film M2 through the film patterns in the fifth metal film M5 to the third metal film M3 in sequence, and the film pattern of the second metal film M2 is electrically connected with the film pattern of the first metal film M1, so that the connection path from the PAD body to the ESD protection device is seen as a path H. Since there is only a single metal wire at the position F on the path H, in the case where the ESD current is large, the electromigration effect (Electro Migration effect) easily occurs at the position F, resulting in burning.

In view of this, the embodiment of the invention provides an IO circuit and a chip, so as to improve the layout design defect of the connection path from the PAD body to the ESD protection device, thereby reducing the possibility of failure on the connection path from the PAD body to the ESD protection device, and improving the ESD protection capability. Fig. 2 is a schematic top view structure of an IO circuit according to an embodiment of the present invention, fig. 3 is a schematic cross-sectional structure of the IO circuit shown in fig. 2 along a cross-sectional line CC', fig. 4 is a schematic top view structure of a second metal layer according to an embodiment of the present invention, fig. 5 is a schematic top view structure of a first routing layer according to an embodiment of the present invention, and in combination with fig. 2 to 5, the IO circuit according to an embodiment of the present invention includes: the ESD protection device, the first metal layer m1, the second metal layer m2, the first wiring layer m3 and the PAD body;

the first metal layer m1 is positioned above the ESD protection device, and a connection terminal of the ESD protection device is led into the first metal layer m 1; a second metal layer m2 is located on a side of the first metal layer m1 away from the ESD protection device, the second metal layer m2 comprising a second comb structure 200, the second comb structure 200 comprising a second base 210 and a plurality of second bars 220; the first routing layer m3 is located at one side of the second metal layer m2 away from the first metal layer m1, the first routing layer m3 comprises a first comb structure 100, the first comb structure 100 comprises a first base 110 and a plurality of first comb strips 120, the first base 110 is opposite to the second base 210, and the first comb strips 120 are opposite to the second comb strips 220;

the first base 110 is electrically connected with the second base 210 through a third through hole, the first sliver 120 is electrically connected with the corresponding second sliver 220 through a second through hole, and the second sliver 220 is electrically connected with the first metal layer m1 through a first through hole; a vertical projection of the second hole region 320 for disposing the second through hole overlaps with a vertical projection of the first hole region 310 for disposing the first through hole; the PAD body is positioned at one side of the first wiring layer m3 far away from the second metal layer m 2; one end of the PAD body is electrically connected with the first base 110.

Specifically, the practical application range of the IO circuit provided in this embodiment is not limited to GPIO (general purpose IO), but may be applicable to other purely analog signal IOs or power ground IOs. The number of ESD protection devices may be plural, and the present embodiment does not particularly limit the number of ESD protection devices. The ESD protection device may include a Diode (Diode), a metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor), such as an NMOS or PMOS, and a connection terminal of the ESD protection device is Source, drain, gate or Bulk, for example. At least one metal layer is required for the four-terminal extraction of the ESD protection device, and the connecting terminal of the ESD protection device is led into the first metal layer m1 in the embodiment.

The PAD body is of a flat plate structure. The PAD body may be composed of multiple metal film layers, an exemplary illustration of which is shown in fig. 3. The second metal layer m2 in this embodiment is used not only for the electrical connection between the PAD body and the ESD protection device, but also for the electrical connection between other parts in the chip. Based on the layout design actually required by the chip, fig. 4 schematically illustrates a partial pattern of the second metal layer m2, which includes the second comb-like structure 200 and some on-chip traces 230; the second comb structure 200 includes a second base 210 and a plurality of second comb bars 220, and the extension directions of the second base 210 and the second comb bars 220 are along the y-direction and the x-direction, respectively.

The first wiring layer m3 may be used to provide power ground wiring, such as VSS wiring or VDD wiring. In the first comb structure 100, the extending directions of the first base 110 and the first sliver 120 are along the y direction and the x direction, respectively. In the z direction, the vertical projections of the central lines of the first base 110 and the second base 210 along the y direction may be coincident (where the first base 110 and the second base 210 are disposed opposite to each other) or may be parallel to each other; and in the z direction, the vertical projection of the central lines of the first comb strip 120 and the second comb strip 220 along the x direction may be coincident (where the first comb strip 120 and the second comb strip 220 are disposed opposite to each other) or may be parallel.

An interlayer insulating layer is generally disposed between each metal layer and each wiring layer, so that the metal layers and the wiring layers can be electrically connected through holes. One end of the PAD body is electrically connected with the first base 110, the first base 110 is electrically connected with the second base 210 through a plurality of third through holes, the first sliver 120 is electrically connected with the corresponding second sliver 220 through a plurality of second through holes, and the second sliver 220 is electrically connected with the first metal layer m1 through a plurality of first through holes. The region of the interlayer insulating layer for disposing all the third through holes is referred to as a third hole region 330, the region of the interlayer insulating layer for disposing all the second through holes is referred to as a second hole region 320, and the region of the interlayer insulating layer for disposing all the first through holes is referred to as a first hole region 310. Referring to fig. 3, in the z-direction, there is overlap of the second aperture region 320 with the perpendicular projection of the first aperture region 310.

Compared with fig. 1 and fig. 3, in the technical solution of the embodiment of the present invention, by providing the first routing layer m3 including the first comb structure 100, where the first comb structure 100 includes the first base 110 and the plurality of first comb strips 120, the first base 110 is electrically connected to one end of the PAD body, the first base 110 is opposite to the second base 210, and the first base 110 is electrically connected to the second base 210 through the third through hole, the first comb strip 120 is opposite to the second comb strip 220, and the first comb strip 120 is electrically connected to the second comb strip 220 through the second through hole, the second comb strip 220 is electrically connected to the first metal layer m1 through the first through hole, and the second hole area 320 overlaps with the vertical projection of the first hole area 310, so that only a single-layer metal wire is no longer used at the position F ' on the connection path H ' of the PAD body to the ESD protection device, but at least two layers of metal wires are always used, thereby improving the situation that the total width of the local routing (position F ' on the connection path H ', that is, the layout fault of the PAD body to the ESD protection device can be reduced, and the possible fault of the ESD protection device can be migrated to the connection path H ' is reduced, and the fault of the ESD protection device can occur. Wherein the ESD current is also schematically illustrated in fig. 3 as I by a "dot-line".

In an embodiment of the present invention, optionally, each first comb strip 120 in the first comb structure 100 corresponds to one second comb strip 220 in the second comb structure 200, and the number of first comb strips 120 in the first comb structure 100 and the number of second comb strips 220 in the second comb structure 200 are not specifically limited in this embodiment, and generally the number of first comb strips 120 in the first comb structure 100 may be set to be smaller than or equal to the number of second comb strips 220 in the second comb structure 200.

Referring to fig. 3 and fig. 5, in addition to the above embodiment, optionally, the first routing layer m3 includes a first electrostatic discharge wire 410 and a plurality of first power supply wires 510, where the first electrostatic discharge wire 410 and the first power supply wires 510 extend in the same direction, and all directions are along the y direction; the IO circuit further comprises a second wiring layer m4 to an nth wiring layer which are sequentially arranged between the first wiring layer m3 and the PAD body, n is a positive integer which is more than or equal to 3, and the IO circuit is exemplarily shown in fig. 3 to further comprise a second wiring layer m4 to a third wiring layer m5 which are sequentially arranged between the first wiring layer m3 and the PAD body; the mth wiring layer includes an mth electrostatic discharge wire and a plurality of mth power supply wires, m is a positive integer greater than or equal to 2 and less than or equal to n, the second wiring layer m4 is exemplarily illustrated in fig. 3 as including a second electrostatic discharge wire 420 and a plurality of second power supply wires 520, and the third wiring layer m5 includes a third electrostatic discharge wire 430 and a plurality of third power supply wires 530; the mth electrostatic discharge wire is disposed opposite (e.g., opposite) the first electrostatic discharge wire 410, and the mth power wire is disposed opposite (e.g., opposite) the first power wire 510; one end of the PAD body is electrically connected to the first base 110 through the nth electrostatic discharge wire to the second electrostatic discharge wire 420 in sequence. The widths of the first electrostatic discharge wire 410 and the mth electrostatic discharge wire along the x direction may be the same or different; the widths of the first power trace 510 and the mth power trace along the x direction may be the same; the first power trace 510 and the mth power trace may both be connected to VSS or VDD.

With continued reference to fig. 3, in an optional manner, the second sliver 220 is electrically connected to the metal wire 800 in the first metal layer m1 through the first via hole, and the metal wire 800 is disposed opposite (e.g., opposite) the second sliver 220. For example, in the first metal layer m1, the metal wire 800 may have a strip shape, the extending direction of the metal wire 800 may be along the x direction, the width of the metal wire 800 along the y direction may be smaller than the width of the second comb strip 220 along the y direction, and the metal wire 800 may be in a one-to-one correspondence with the second comb strip 220.

With continued reference to fig. 3, optionally, the length of the metal wire 800 along the x-direction is smaller than the length of the second sliver 220 along the x-direction, the length of the metal wire 800 along the x-direction is greater than the length of the first sliver 120 along the x-direction, and the perpendicular projection of the metal wire 800 does not overlap with the perpendicular projection of the first base 110 in the z-direction. In the technical solution of this embodiment, the specific length of the first sliver 120 along x may be set according to actual needs, which is not specifically limited.

With continued reference to fig. 3, in addition to the above embodiment, optionally, the metal line 800 is electrically connected to the connection terminal of the ESD protection device through a plurality of fourth through holes; the region of the interlayer insulating layer for disposing all the fourth via holes is regarded as a fourth hole region 340, and the vertical projection of the fourth hole region 340 overlaps with the vertical projection of the first hole region 310. In this way, according to the technical scheme of the embodiment, on the basis of reducing the possibility of failure on the connection path between the first routing layer m3 and the second metal layer m2, the possibility of failure on the connection path between the second metal layer m2 and the first metal layer m1 caused by the defect of the layout design of the connection path between the second metal layer m2 and the first metal layer m1 is further avoided, so that the possibility of failure on the connection path H' between the PAD body and the ESD protection device is further reduced, and the ESD protection capability is improved.

In the embodiment of the present invention, there are various ways to form the first comb-like structure 100 in the first routing layer m3, and several of them are described below for illustration, but the present invention is not limited thereto.

In one embodiment of the present invention, with continued reference to fig. 5, the first electrostatic discharge wire 410 may optionally form the first base 110, and the first portion structure of the first power supply wire 510_1 adjacent to the first electrostatic discharge wire 410 may form the plurality of first strips 120. With continued reference to fig. 6, optionally, a second portion of the first power supply trace 510_1 adjacent to the first electrostatic discharge trace 410 forms a third comb structure 600, the third comb structure 600 and the first comb structure 100 form a first interdigital structure, the third comb structure 600 includes a third base 610 and a plurality of third strips 620, and the width of the third strips 620 is smaller than the width of the first strips 120.

Specifically, only a few first power traces 510 are exemplarily illustrated in the drawings, and the actual first trace layer m3 includes a large number of first power traces 510. In the technical solution of this embodiment, in order to design the position F 'without only a single-layer metal wire but at least two layers of metal wires all the time, so as to improve the layout design defect of the connection path H' from the PAD body to the ESD protection device, a small part of the structure of the first power supply trace 510_1 adjacent to the first electrostatic discharge trace 410 is separated and used on the connection path H 'from the PAD body to the ESD protection device, i.e. the metal resources of the first trace layer m3 are redistributed, so that the position F' is not only a single-layer metal wire but at least two layers of metal wires all the time, and in this design, the technical solution of this embodiment also does not affect and destroy the layout design of other trace layers, so that it does not affect and destroy the original architecture of the IO circuit, and does not need to add additional structures in the IO circuit.

In addition, after a small portion of the structure of the first power supply trace 510_1 adjacent to the first electrostatic discharge trace 410 is removed to make the first comb strip 120 of the first comb structure 100, a small portion of the structure of the first power supply trace 510_1 may be continuously removed to make the third comb structure 600, and the third comb structure 600 and the remaining structure of the first power supply trace 510_1 may be continuously used as power supply lines; the third comb 620 in the third comb structure 600 may facilitate the electrical connection between the first power trace 510_1 and the underlying ESD protection device, for example, the third comb 620 may be connected to a connection terminal of the ESD protection device through a via.

In another embodiment of the present invention, fig. 6 is a schematic top view of another first routing layer m3 provided in the embodiment of the present invention, and referring to fig. 6, optionally, a first electrostatic discharge wire 410 forms a first base 110, and a first portion structure of a first power supply wire 510_1 adjacent to the first electrostatic discharge wire 410 forms a plurality of first strips 120. With continued reference to fig. 5, optionally, the first power trace 510 adjacent to the first electrostatic discharge trace 410 is a first power trace 510_1, and the first power trace 510 adjacent to the first power trace 510_1 is a second first power trace 510_2; the third partial structure of the first power supply trace 510_1 and the partial structure of the second first power supply trace 510_2 form a fourth comb structure, and the fourth comb structure and the first comb structure 100 form a second interdigital structure; the fourth comb structure includes a fourth base 710 and a plurality of fourth bars 720, the fourth bars 720 having a width smaller than the width of the first bars 120.

Specifically, in the case where the length of the first comb bar 120 in the x direction is set to be long, the structure of the first power supply trace 510_1 adjacent to the first electrostatic discharge trace 410 in the y direction is also sufficient to be moved to make the third comb bar 620, but the structure of the first power supply trace 510_1 in the x direction is insufficient to set the third base 610, so that a partial structure of the second first power supply trace 510_2 is adopted as the third base 610, and the third comb bar 620 and the third base 610 at this time constitute a fourth comb structure.

In another embodiment of the present invention, fig. 7 is a schematic top view of another first routing layer m3 provided in the embodiment of the present invention, and referring to fig. 7, optionally, a first base 110 is formed by a first electrostatic discharge wire 410 and a fourth portion structure of a first power supply wire 510_1 adjacent to the first electrostatic discharge wire 410; the plurality of first slivers 120 are configured by a fifth partial structure of the first power supply trace 510_1 adjacent to the first electrostatic discharge trace 410.

Specifically, when the width of the first esd protection wire 410 along the x direction is smaller such that only the first esd protection wire 410 is insufficient as the first base 110, the structure of the first power supply wire 510_1 adjacent to the first esd protection wire 410 may be removed by a small portion to manufacture the first base 110, that is, the partial structure of the first power supply wire 510_1 and the first esd protection wire 410 together form the first base 110.

In summary, the above specific way of moving the metal resources of the first power supply trace 510 in the first trace layer m3 in the embodiment of the present invention is merely an example, and it is guaranteed that the first comb structure 100 and the third comb structure 600 meeting the actual needs can be formed, or the first comb structure 100 and the fourth comb structure meeting the actual needs can be formed, so that the present invention is not limited in particular.

According to the technical scheme, under the condition that the original architecture of an IO circuit is not affected and destroyed, and meanwhile, the structure additionally arranged in the IO circuit is not needed, metal resources of a first wiring layer m3 in the IO circuit are redistributed, specifically, the structure of a first power supply wiring 510 of a first electrostatic discharge wiring 410 in the first wiring layer m3 is moved, so that a single-layer metal connecting wire is not arranged at a position F ', but at least two layers of metal connecting wires are arranged all the time, the situation that the bottleneck appears in the total width of a local wiring (the position F') on a wiring path H 'is improved, namely, the layout design defect of the wiring path H' from a PAD body to an ESD protection device is improved, the possibility that the wiring path H 'is burnt due to the electromigration effect is reduced, the possibility that the wiring path H' from the PAD body to the ESD protection device is broken is reduced, and the ESD protection capability is improved.

Based on the above embodiments, the embodiment of the present invention further provides a chip, where the chip includes the IO circuit provided by any of the above technical solutions. The chip and the IO circuit provided by the embodiment of the invention belong to the same invention conception, can realize the same technical effect, and are not repeated here.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. An IO circuit, comprising:

2. The IO circuit of claim 1 wherein the first trace layer comprises a first electrostatic discharge trace and a plurality of first power traces, the first electrostatic discharge trace extending in the same direction as the first power traces;

3. The IO circuit of claim 2 wherein a second partial structure of the first power supply trace adjacent to the first electrostatic discharge trace forms a third comb structure, the third comb structure and the first comb structure forming a first inter-digitated structure;

4. The IO circuit of claim 2 wherein the first power supply trace adjacent to the first electrostatic discharge trace is a first one of the first power supply traces and the first power supply trace adjacent to the first one of the first power supply traces is a second one of the first power supply traces;

5. The IO circuit of claim 1 wherein the first trace layer comprises a first electrostatic discharge trace and a plurality of first power traces, the first electrostatic discharge trace extending in the same direction as the first power traces;

6. The IO circuit of claim 1 wherein the first trace layer comprises a first electrostatic discharge trace and a plurality of first power traces, the first electrostatic discharge trace extending in the same direction as the first power traces;

7. The IO circuit of claim 1 wherein the second sliver is electrically connected to metal lines in the first metal layer through the first via, the metal lines being disposed opposite the second sliver.

8. The IO circuit of claim 7 wherein a vertical projection of the first base does not overlap a vertical projection of the metal line; the length of the first sliver is smaller than that of the metal wire, and the length of the metal wire is smaller than that of the second sliver.

9. The IO circuit of claim 7 wherein the metal line is electrically connected to a connection terminal of the ESD protection device through a fourth via; a perpendicular projection of a fourth hole area for providing the fourth through hole overlaps with a perpendicular projection of the first hole area.

10. A chip comprising the IO circuit of any one of claims 1-9.