CN113169161A - 半导体封装件、其制造方法及半导体装置 - Google Patents

半导体封装件、其制造方法及半导体装置 Download PDF

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CN113169161A
CN113169161A CN201880099699.8A CN201880099699A CN113169161A CN 113169161 A CN113169161 A CN 113169161A CN 201880099699 A CN201880099699 A CN 201880099699A CN 113169161 A CN113169161 A CN 113169161A
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conductor
semiconductor
substrate
semiconductor package
package according
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中田洋辅
藤田淳
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

目的在于提供能够实现半导体封装件的成本降低或小型化的技术。配线用元件包含：第2基板；多个第1中继焊盘，它们配设于第2基板的与导体基板相反侧的面，通过导线与多个半导体元件的控制焊盘连接；多个第2中继焊盘，它们配设于第2基板的与导体基板相反侧的面，个数小于或等于多个第1中继焊盘的个数；以及多个配线，它们配设于第2基板的与导体基板相反侧的面，选择性地将多个第1中继焊盘和多个第2中继焊盘连接。

Description

半导体封装件、其制造方法及半导体装置
技术领域
本发明涉及半导体封装件、其制造方法及半导体装置。
背景技术
针对电力用半导体装置提出了各种技术。例如，在专利文献1中提出了如下半导体装置，即，通过用树脂对半导体元件、与该半导体元件连接的柱电极进行封装，从而从柱电极获取由半导体元件控制的电力。
另一方面，在使用了碳化硅(SiC)的MOSFET(Metal Oxide Semiconductor FieldEffect Transistor)模块等电力用半导体装置中，难以实现该MOSFET的大面积化、乃至电流容量的增大，无法直接使用专利文献1的技术。因此，提出了为了能够应对电流容量的增大而将多个半导体芯片并联连接的结构。例如，在专利文献2中提出了从多个半导体芯片经由导线将信号输入至绝缘基板之上的信号配线图案的结构。
专利文献1：日本特开2014-1999555号公报
专利文献2：国际公开第2014/046058号
发明内容
但是，在专利文献2的技术中，与栅极电极对应的信号配线图案和与源极电极对应的主电流电路图案配设于同一部件之上。因此，当在主电流电路图案流动比较大的电流的情况下，例如，为了确保信号配线图案和主电流电路图案之间的绝缘，需要使这些图案充分远离。其结果，存在半导体装置的尺寸变大、由于组装方法繁杂而使成本变大这样的问题。
因此，本发明就是鉴于上述那样的问题而提出的，其目的在于提供能够实现半导体封装件的成本降低或小型化的技术。
本发明涉及的半导体封装件具有：导体基板；多个半导体元件，它们与所述导体基板的第1主面接合，具有开关功能；以及配线用元件，其与所述导体基板的所述第1主面接合，所述多个半导体元件各自包含：第1基板；第1主电极部，其配设于所述第1基板的与所述导体基板相反侧的面；第2主电极部，其配设于所述第1基板的所述导体基板侧的面，与所述导体基板接合；以及控制焊盘，其用于对在所述第1主电极部和所述第2主电极部之间流动的电流进行控制，所述配线用元件包含：第2基板；多个第1中继焊盘，它们配设于所述第2基板的与所述导体基板相反侧的面，通过导线与所述多个半导体元件的所述控制焊盘连接；多个第2中继焊盘，它们配设于所述第2基板的与所述导体基板相反侧的所述面，个数小于或等于所述多个第1中继焊盘的个数；以及多个配线，它们配设于所述第2基板的与所述导体基板相反侧的所述面，选择性地将所述多个第1中继焊盘和所述多个第2中继焊盘连接，该半导体封装件还具有：多个第1导体部件，它们与所述多个半导体元件的所述第1主电极部接合；多个第2导体部件，它们与所述配线用元件的所述多个第2中继焊盘接合；以及封装材料，其以使所述多个第1导体部件的与所述导体基板相反侧的面即露出面、所述多个第2导体部件的与所述导体基板相反侧的面即露出面、及所述导体基板的与所述第1主面相反侧的第2主面露出的状态，覆盖所述多个半导体元件、所述配线用元件、所述多个第1导体部件的至少一部分、所述多个第2导体部件的至少一部分、及所述导体基板的所述第1主面。
发明的效果
根据本发明，配线用元件包含：第2基板；多个第1中继焊盘，它们通过导线与多个半导体元件的控制焊盘连接；多个第2中继焊盘，它们的个数小于或等于多个第1中继焊盘的个数；以及多个配线，它们选择性地将多个第1中继焊盘和多个第2中继焊盘连接。由此，能够实现半导体封装件的成本降低或小型化。
通过下面的详细的说明和附图，本发明的目的、特征、方式及优点会变得更加清楚。
附图说明
图1是表示实施方式1涉及的半导体封装件的结构的平面示意图。
图2是表示实施方式1涉及的半导体封装件的结构的剖面示意图。
图3是表示实施方式1涉及的半导体装置的结构的斜视示意图。
图4是表示实施方式1涉及的半导体装置的结构的剖面示意图。
图5是表示实施方式1涉及的半导体装置的结构的斜视示意图。
图6是表示实施方式2涉及的半导体封装件的结构的剖面示意图。
图7是表示实施方式3涉及的半导体封装件的结构的剖面示意图。
图8是表示实施方式4涉及的半导体装置的结构的斜视示意图。
图9是表示实施方式5涉及的半导体装置的结构的剖面示意图。
具体实施方式
<实施方式1>
图1是表示本发明的实施方式1涉及的半导体封装件1的结构的平面示意图，图2示出该半导体封装件1的结构，是沿图1的A-A’线的剖面示意图。
如图1及图2所示，半导体封装件1具有导体基板2、多个半导体元件3、配线用元件4。下面，以多个半导体元件3的个数为5个进行说明，但只要是大于或等于2个即可。另外，下面以配线用元件4的个数为1个进行说明，但只要是比多个半导体元件3的个数少的数量即可。
多个半导体元件3接合于导体基板2的第1主面2S1(图2)，多个半导体元件3各自具有开关功能。配线用元件4接合于导体基板2的第1主面2S1。在图1的例子中，在俯视观察时配线用元件4的除了1个方向(下方)外的3个方向(上方、左方及右方)在被多个半导体元件3包围的状态下接近多个半导体元件3。
多个半导体元件3各自包含第1基板即半导体基板31、第1主电极部即表面电极32f、第2主电极部即背面电极33b、大于或等于1个控制焊盘34c。此外，多个半导体元件3中的至少1者也可以进一步包含未图示的电流感测元件及温度感测元件中的至少1者。
表面电极32f配设于半导体基板31的与导体基板2相反侧的面即表面。表面电极32f例如作为主要材料包含镍，在该材料的最表面包含金或银。此外，表面电极32f与源极电极对应。
背面电极33b配设于半导体基板31的导体基板2侧的面即背面，与导体基板2接合。由此，多个半导体元件3的背面电极33b的电位彼此相等。背面电极33b例如作为主要材料包含镍，在该材料的最表面包含金或银。此外，背面电极33b与漏极电极对应。
控制焊盘34c是用于对在表面电极32f和背面电极33b之间流动的电流进行控制的焊盘。此外，控制焊盘34c与栅极电极对应。
配线用元件4包含第2基板即配线用基板41、多个第1中继焊盘42r、多个第2中继焊盘43r、多个配线即多个内部配线44i。
多个第1中继焊盘42r、多个第2中继焊盘43r、及内部配线44i配设于配线用基板41的与导体基板2相反侧的面即表面，通过配线用基板41等与导体基板2绝缘。
多个第1中继焊盘42r通过导线5与多个半导体元件3的控制焊盘34c连接。导线5例如具有小于或等于100μmΦ的线径，作为主要材料包含金。
多个第2中继焊盘43r的个数小于或等于多个第1中继焊盘42r的个数。此外，在图1的例子中，多个第2中继焊盘43r沿配线用基板41中的与半导体封装件1的外侧接近的缘部而排列，但多个第2中继焊盘43r的位置不限于此。
多个内部配线44i在配线用元件4的内部选择性地将多个第1中继焊盘42r和多个第2中继焊盘43r连接。此外，在图1的例子中，第1中继焊盘42r的宽度比内部配线44i的宽度大，第2中继焊盘43r的宽度比第1中继焊盘42r的宽度大。
如图1及图2所示，半导体封装件1还具有多个第1导体部件即多个导体板38、多个第2导体部件即多个导体片48、封装材料6。
多个导体板38接合于多个半导体元件3的表面电极32f，多个导体片48接合于配线用元件4的多个第2中继焊盘43r。此外，表面电极32f及第2中继焊盘43r各自作为主要材料包含能够进行焊料接合的金属，例如镍。
封装材料6覆盖多个半导体元件3、配线用元件4、多个导体板38的至少一部分、多个导体片48的至少一部分、及导体基板2的第1主面2S1，实质性地对它们进行封装。封装材料6包含环氧树脂，例如，是通过传递模塑法、压缩模塑法、或浇注法形成的。
此外，多个导体板38的与导体基板2相反侧的面即露出面、多个导体片48的与导体基板2相反侧的面即露出面、及导体基板2的与第1主面2S1相反侧的第2主面2S2从封装材料6露出。如图2所示，半导体封装件1具有彼此朝向相反方向的第1表面1S1和第2表面1S2。导体基板2的第2主面2S2与半导体封装件的第1表面1S1对应，多个导体板38的露出面及多个导体片48的露出面与半导体封装件1的第2表面1S2对应。
从封装材料6露出多个导体板38及多个导体片48的一部分的结构例如是通过研磨工序形成的，该研磨工序是在利用成为封装材料6的封装部件覆盖了成为多个导体板38及多个导体片48的金属部件后，对它们的一部分进行研磨，将金属部件露出。此时，在研磨后的封装材料6的高度比导线5的线环高度h充分高，并且导线5没有从封装材料6露出的程度的时刻，结束研磨。
在本实施方式1中，将多个半导体元件3和导体基板2接合的接合材料21的熔点比焊料的熔点高。此外，由于通常的半导体装置的制造工序中的焊料接合工序小于或等于450℃，因此优选接合材料21的熔点比450℃高。
这里，多个半导体元件3和导体基板2例如通过银类材料或铜类材料进行烧结接合(烧制接合)。
在将银类材料用于接合材料21的结构中，例如，在将成为接合材料21的糊剂通过印刷或分配器形成于导体基板2的规定位置后，在糊剂之上载置半导体元件3，使糊剂尽量没有气泡地将半导体元件3和导体基板2密接。之后，不进行加压地在200℃～300℃的温度下以几十分钟，在氮环境下对糊剂进行烧结。如上所述，在将银类材料用于接合材料21的结构中，将多个半导体元件3和导体基板2接合的烧结接合是在没有伴随加压的情况下进行的。
在将铜类材料用于接合材料21的结构中，例如，在将成为接合材料21的糊剂通过印刷或分配器形成于导体基板2的规定位置后，在糊剂之上载置半导体元件3，通过以10～40MPa施加载荷而进行加压，与此同时，在200℃～300℃的温度下以几十分钟，在氮环境中对糊剂进行烧结。在该烧结时，为了防止由施加载荷造成的半导体元件3表面的损伤，例如，使用特氟隆片材。另外，在将片材成型品用于烧结材料供给的情况下，预先在半导体元件3的背面暂时附着了烧结材料后，将半导体元件3暂时压接于导体基板2的规定位置，之后在相同的条件下进行加压烧结。如上所述，在将铜类材料用于接合材料21的结构中，将导体基板2和多个半导体元件3接合的烧结接合是伴随加压而进行的。
此外，导体基板2和多个半导体元件3也可以不进行烧结接合而是进行扩散接合。另外，以上，对将导体基板2和多个半导体元件3接合的接合材料21进行了说明，但将配线用元件4和导体基板2接合的接合材料22也可以与接合材料21相同。
本实施方式1涉及的半导体封装件1还具有保护膜36。保护膜36是覆盖多个半导体元件3的端部即缘部，并且杨氏模量比封装材料6低的膜。该保护膜36例如包含聚酰亚胺。此外，例如，在将配线用元件4和多个半导体元件3接合于导体基板2后，使用分配器对保护膜36的前驱体溶液进行描绘，通过对该前驱体溶液进行烧制而形成保护膜36。
导体基板2例如作为主要材料包含铜。在导体基板2的第1主面2S1中的与配线用元件4及多个半导体元件3接合的区域之外的区域配设有凹部即槽2d。此外，凹部也可以不是槽2d而是凹陷孔等。
多个导体板38及多个导体片48例如作为主要材料包含铜。另外，如图2所示，多个导体板38、多个半导体元件3的表面电极32f例如通过焊料37进行接合，多个导体片48、配线用元件4的多个第2中继焊盘43r例如通过焊料47进行接合。多个导体板38及多个导体片48的厚度即上述研磨工序后的多个导体板38及多个导体片48的厚度d充分大于导线5的线环高度h。
在本实施方式1中，多个半导体元件3包含化合物半导体。例如，多个半导体元件3作为化合物半导体的主要材料包含碳化硅(SiC)。多个半导体元件3各自例如包含进行通断动作的MOSFET(未图示)、进行续流动作的体二极管(未图示)。而且，能够进行该MOSFET和该体二极管的双向通电。
在本实施方式1中，在形成了多个导体板38后，进一步形成半导体封装件1，然后进行检测多个半导体元件3内的缺陷的筛选试验。由此，能够对筛选试验的体二极管通电所导致的电极等元件的特性劣化进行抑制。此外，在不将体二极管通电用于主要续流路径的结构中，半导体元件3也可以例如包含续流用SBD(Schottky barrier diode)来替代体二极管。
配线用元件4的配线用基板41例如也可以是作为主要材料包含硅(Si)的硅基板等。在该情况下，在硅基板之上，例如，形成氧化膜，在该氧化膜之上形成多个第1中继焊盘42r、多个第2中继焊盘43r、及多个内部配线44i。这些焊盘及配线的图案例如能够使用由溅射后的照相制版实现的图案化等通常的晶片工艺方法形成。这些焊盘及配线例如被覆盖膜46覆盖，覆盖膜46例如与保护膜36相同地包含聚酰亚胺。
配线用元件4的配线用基板41并不限于上述基板，例如，也可以是包含树脂的树脂基板等。在该情况下，例如，在将配线用基板41接合于导体基板2前，在树脂基板的表面，通过铜材料事先形成第1中继焊盘42r及第2中继焊盘43r。然后，通过烧结接合将导体片48接合于与外部电连接的第2中继焊盘43r。之后，将配线用基板41接合于导体基板2。此外，在树脂基板背面例如选择性地形成接合用膜即铜等的薄膜、连接膜即镍、银、铜等的薄膜、防氧化膜即金等的薄膜中的至少1者。此外，在将镍的薄膜用于连接膜的情况下，为了确保使用了银的烧结接合的接合性，优选在连接膜的最表面设置金的薄膜。
半导体元件3的半导体基板31例如被研磨为100μm厚度左右。另一方面，配线用元件4例如被研磨为400μm左右、250厚度μm左右，根据需要而被研磨为150μm左右。在将硅基板用于配线用基板41，并且将配线用元件4薄化至150μm左右的情况下，也难以产生晶片工艺上的问题。这样，如果在半导体元件3和配线用基板4之间具有高低差，则产生容易进行导线5的导线键合这样的效果。除此之外，半导体元件3的外周部具有保护环等耐压保持构造，由于变为高电场，因此优选使剖视中的半导体元件3的外周部上方的导线5的线环部尽量远离半导体元件3的表面。在半导体元件3比配线用基板4薄的情况下，由于能够使导线5的线环部远离半导体元件3的表面，因此优选半导体元件3比配线用元件4薄。
图3是表示本实施方式1涉及的使用了半导体封装件1的半导体装置7的结构的斜视示意图，图4是表示其一部分的剖面示意图。
如图3及图4所示，半导体装置7具有大于或等于1个半导体封装件1。另外，如图3及图4所示，半导体装置7还具有树脂壳体71、绝缘基板72、第1电路图案即第1主电流电路图案73、外部电极74、电路图案75、导线76、主端子即外部电极77、导线78、控制端子即信号端子79。另外，如图4所示，半导体装置7还具有封装材料80、盖81、金属层82。此外，大于或等于1个半导体封装件1也可以是作为单位而包含构成全桥电路的6个半导体封装件。
树脂壳体71及绝缘基板72构成具有在上方开口的空间的容器体。第1主电流电路图案73配设于绝缘基板72中的形成该容器体的空间的部分。另外，第1主电流电路图案73例如通过焊料与半导体封装件1的第1表面1S1中的从封装材料6露出的导体基板2的第2主面2S2(图2)进行接合。就这样构成的半导体装置7而言，第1主电流电路图案73被用作漏极电极。该第1主电流电路图案73与外部电极74连接。
电路图案75通过导线76与半导体封装件1的第2表面1S2中的导体板38的露出面(图2)连接。另外，该电路图案75与外部电极77连接。这样，外部电极77通过导线76与导体板38的露出面电连接。将导体板38的露出面和外部电极77电连接的导线76例如可以是具有大于或等于400μmΦ线径的、作为主要材料包含铝的导线，也可以是作为主要材料包含铜等的导线。此外，在导线76为作为主要材料包含铜的导线的情况下，能够提高电导率。
信号端子79通过导线78与半导体封装件1的第2表面1S2中的导体片48的露出面(图2)连接。将导体片48的露出面和信号端子79电连接的导线78例如也可以是具有大于或等于200μmΦ线径的、作为主要材料包含铝的导线。
如上所述，半导体封装件1与外部电极74、外部电极77、及信号端子79电连接。此外，在本实施方式1中，树脂壳体71、外部电极74、77及信号端子79是一体地形成的，但并不限于此。在将半导体封装件1连接于外部电极74等后，如图4所示，通过在上述容器体的空间中封入封装材料80，从而通过封装材料80对半导体封装件1周边进行封装。封装材料80例如包含硅凝胶。在凝胶封装后，如图4及图5所示，通过在树脂壳体71安装盖81，从而将半导体装置7外部与包含半导体封装件1及半导体封装件1周边的接合构造在内的半导体装置7内部隔离。
在图4的例子中，导体板等金属层82配设于绝缘基板72的与半导体封装件1相反侧的面，与未图示的冷却鳍片连接。金属层82向冷却鳍片的连接例如使用钎料、焊料、导热脂等通常的接合材料及方法。通过对冷却鳍片进行冷却，从而对从半导体元件3产生的热量进行散热。此外，也可以不将金属层82向冷却鳍片连接，而是通过直接使冷却水接触金属层82而对金属层82乃至半导体元件3进行冷却。
<实施方式1的总结>
根据本实施方式1涉及的半导体封装件1，通过利用例如包含Si的配线用元件4对例如包含SiC的MOSFET等多个半导体元件3进行信号配线，从而能够将导体片48用作控制焊盘(例如，栅极电极、源极开尔文电极、电流感测源极电极、温度感测元件电极等)、将导体板38用作源极电极、将导体基板2用作漏极电极。由此，能够将多个半导体元件3像单一半导体元件，乃至单一半导体芯片那样使用。因此，例如，能够实现由导线键合、芯片焊接工序等中的半导体装置7的组装性提高带来的成本降低、半导体装置7的小型化。另外，由于在配线用元件4没有配设与源极电极对应的主电流电路图案，因此能够实现由半导体封装件1的组装性提高带来的成本降低、半导体封装件1的小型化。
另外，通过具有配线用元件4，从而能够尽量缩短导线78的长度，并且能够减小导线78的直径。因此，能够尽量减小半导体元件3的控制焊盘34c的尺寸。由此，能够扩大半导体元件3的有效面积。特别地，在将SiC等昂贵的材料用于半导体元件3的母材的情况下，通过扩大半导体元件3的有效面积来降低产品成本是有效的。
另外，在本实施方式1中，多个半导体元件3各自例如包含进行通断动作的MOSFET(未图示)、进行续流动作的体二极管(未图示)。根据这样的结构，由于能够省略SBD等半导体元件，因此能够实现半导体封装件1的小型化和成本降低。
此外，在包含SiC的MOSFET内存在晶体缺陷的情况下，如果对体二极管进行通电，则有时该缺陷生长而使特性恶化。但是，通过进行筛选试验，能够避免将内含缺陷的半导体封装件1搭载于半导体装置7。在该筛选试验中，由于需要流动比较大的电流，因此担心如果向薄的表面电极32f流过大的电流，则会对表面电极32f造成损伤，另外，担心由于由通电产生的热量没有被高效地排热而积蓄于半导体元件3，因此使半导体元件3变为高温，例如还担心电流、热量集中于探针等试验工具所接触的位置处等。但是，如本实施方式1所示，通过在形成了多个导体板38后，进一步形成半导体封装件1，然后实施筛选试验，从而能够对这样的电极损伤进行抑制。另外，由于将如铜那样热容量大的材料直接接合而进行电及热连接，因此与以半导体元件3单体对筛选试验时的发热进行了试验的情况相比，能够有效地从半导体元件3进行排热。除此之外，由于探针等试验工具一度与导体板38接触，因此能够分配电流，能够向半导体元件3均匀地通入筛选试验的电流。即，优选向导体板38应用热容量大、电导率高的铜等材料。另外，如本实施方式1所示，在半导体封装件1为电路结构上的最小单位(1合1)的结构中，与对2合1、6合1这样的更大电路规模的半导体装置实施了筛选试验的情况相比，能够降低不良率。
在配线用元件4的配线用基板41作为主要材料包含Si的结构中，能够通过现有的晶片工艺容易地形成配线用元件4。因此，如果将与半导体元件3相同或类似的背面电极也形成于配线用元件4，则能够通过与半导体元件3相同的方法形成配线用元件4，因此能够降低制造成本。
在配线用元件4的配线用基板41包含树脂的结构中，由于能够将事先接合有导体片48的树脂基板接合于导体基板2，因此能够提高半导体封装件1的组装性。另外，例如，在配设于树脂基板表面的多个第1中继焊盘42r及多个第2中继焊盘43r包含铜材料的情况下，能够在通过烧结接合将导体片48接合于第2中继焊盘43r后，将配线用基板41接合于导体基板2。另外，通过在树脂基板背面选择性地形成例如接合用膜即铜等的薄膜、连接膜即镍、银、铜等的薄膜、防氧化膜即金等的薄膜中的至少1者，从而能够提高焊料接合性、使用了银、铜的烧结接合性，因此能够提高制造性。另外，根据由树脂基板构成的配线用基板41，与由硅基板构成的配线用基板41相比，能够缩短将导体片48接合于第2中继焊盘43r的加工时间，因此能够对制造成本进行抑制。
另外，在本实施方式1中，将导体基板2和多个半导体元件3接合的接合材料21使用具有比焊料的熔点高的熔点的接合材料。由此，在将半导体封装件1焊料接合于例如绝缘基板72之上的第1主电流电路图案73时，能够对半导体元件3之下的接合材料21再熔融进行抑制。其结果，能够对成品率、散热性能的劣化进行抑制。而且，由于还能够对在高的结温下使半导体元件3进行动作的情况下的接合材料21的劣化进行抑制，因此能够改善半导体封装件1的可靠性。
另外，在本实施方式1中，将导体基板2和多个半导体元件3接合的烧结接合是不伴随加压地使用银类材料进行的。由此，由于能够避免加压时的位置偏移，能够降低尺寸公差，因此能够将半导体封装件1小型化。除此之外，由于能够削减加压加工所使用的特氟隆片材等消耗部件，因此能够降低制造成本。此外，在使用铜类材料而进行将导体基板2和多个半导体元件3接合的烧结接合的情况下，与使用金类材料而进行该烧结接合的情况相比，由于该接合为高强度，因此能够期待半导体封装件1的可靠性的提高。
另外，在本实施方式1中，通过保护膜36覆盖半导体元件3的端部。由此，不仅能够改善半导体元件3和封装材料6的密合性，还由于得到应力缓冲而能够改善半导体封装件1的可靠性。在保护膜36包含聚酰亚胺的结构中，由于半导体元件3表面的结构材料与封装材料6的相容性良好，因此能够改善半导体封装件1的可靠性。
另外，在本实施方式1中，在将配线用元件4及多个半导体元件3接合于导体基板2后，使用分配器对保护膜36的前驱体溶液进行描绘，对该前驱体溶液进行烧制，从而形成保护膜36。由此，能够抑制在对保护膜36进行烧制的工序中半导体元件3之下的接合材料21熔融。
另外，在本实施方式1中，导体基板2作为主要材料包含铜。由此，能够容易地将半导体封装件1与半导体封装件1外部的电路图案(例如第1主电流电路图案73)焊料接合。另外，根据这样的结构，能够高效地使半导体元件3的热量扩散，因此能够降低热阻。通常，由于如果包含SiC的MOSFET的温度升高则损耗恶化，因此优选高效地对该MOSFET进行冷却，但存在由于成品率的影响难以大面积化、热阻高这样的问题。相对于此，在本实施方式1中，在半导体元件3正下方使用银而进行了烧结接合的导体基板2包含导热高的铜材料。因此，能够促进热扩散，具体而言，实质上能够通过与半导体元件3的面积相等或更大的面积进行高效的热扩散，因此能够降低热阻。
另外，在本实施方式1中，在导体基板2的第1主面2S1中的与配线用元件4及多个半导体元件3接合的区域之外的区域配设有凹部即槽2d。由此，封装材料6与导体基板2的密合性提高，因此能够改善半导体封装件1的可靠性。另外，由于能够分散导体基板2表面的拉伸应力，因此能够对半导体封装件1的翘曲进行抑制。
另外，在本实施方式1中，导体板38及导体片48的主要材料包含铜。由此，能够廉价地形成导体板38及导体片48，并且能够容易地通过焊料将它们接合。
另外，在本实施方式1中，外部电极74、77、信号端子79使用导线键合、焊料接合等各种接合方法。由此，能够容易地将半导体封装件1搭载及接合于半导体装置7，并且能够将以往的半导体装置和制造设备共通化，因此能够抑制半导体装置7的制造成本、及对制造设备的投资。
<实施方式2>
图6是表示本发明的实施方式2涉及的半导体封装件1的结构的与图2对应的剖面示意图。以下，对本实施方式2所涉及的结构要素中的与上述结构要素相同或类似的结构要素标注相同的参照标号，主要对不同的结构要素进行说明。
如图6所示，本实施方式2涉及的半导体封装件1的导体基板2包含内含碳纤维2cf的层叠板2e。碳纤维2cf沿多个半导体元件3的半导体基板31的平面方向排列。通过对碳纤维2cf的含量、直径及长度等参数进行调整，从而任意地对半导体元件3的横向的热传导率及线膨胀系数进行调整。层叠板2e作为主要材料包含铝。
此外，在本实施方式2中，导体基板2包含：层叠板材2f，其配设于第1主面2S1侧，不包含碳纤维2cf；以及层叠板材2g，其配设于第2主面2S2侧，不包含碳纤维2cf。层叠板材2f、2g各自也可以包含配设于层叠板2e的最表面的、例如作为主要材料包含镍或铜的连接膜。另外，层叠板材2f、2g各自也可以包含配设于连接膜的最表面的、例如作为主要材料包含金的防氧化膜。连接膜和防氧化膜例如能够通过镀敷处理形成。此外，即使连接膜被氧化，通过在还原环境下进行焊料接合等处理，也能够比较容易地除去氧化膜，因此防氧化膜并非是必须的。
<实施方式2的总结>
在本实施方式2中，导体基板2包含内含碳纤维2cf的层叠板2e。根据这样的结构，通过对导体基板2的线膨胀系数进行调整，从而能够对半导体封装件1的翘曲进行抑制，因此能够提高半导体封装件1的组装性及可靠性。
另外，在本实施方式2中，碳纤维2cf沿多个半导体元件3的半导体基板31的平面方向排列。由此，能够高效地将从半导体元件3发出的热量扩散，因此能够以大于或等于半导体元件3的有效面积的范围高效地进行冷却。
另外，如本实施方式2所示，在层叠板2e作为主要材料包含铝的结构中，与层叠板2e作为主要材料包含铜的结构相比，能够降低杨氏模量。通过利用这一点以及由于内含碳纤维2cf而实现的导体基板2的线膨胀系数的调整，能够降低在半导体元件3及封装材料6产生的应力。其结果，能够对半导体封装件1的翘曲进行抑制，能够对封装材料6从导体基板2剥离进行抑制，因此能够提高半导体封装件1的组装性及可靠性。
此外，在层叠板材2f、2g各自由在包含铝的层叠板2e的最表面配设的作为主要材料包含镍或铜的连接膜、在连接膜的最表面配设的作为主要材料包含金的防氧化膜等构成的情况下，由于能够提高焊料接合性、使用了银的烧结接合性，因此能够提高制造性。此外，在将镍用于连接膜的情况下，为了确保使用了银的烧结接合性，优选在最表面设置金。
<实施方式3>
图7是表示本发明的实施方式3涉及的半导体封装件1的结构的与图2对应的剖面示意图。以下，对本实施方式3所涉及的结构要素中的与上述结构要素相同或类似的结构要素标注相同的参照标号，主要对不同的结构要素进行说明。
如图7所示，本实施方式3涉及的半导体封装件1的导体基板2包含具有大于或等于3个金属膜的层叠金属膜。在图7的例子中，大于或等于3个金属膜为在层叠方向上位于内侧的第1金属膜即内层金属膜2j、及在层叠方向上位于外侧的第2金属膜及第3金属膜即表层金属膜2k及表层金属膜2l。表层金属膜2k配设于内层金属膜2j的一个面，表层金属膜2l配设于内层金属膜2j的另一面。内层金属膜2j的线膨胀系数比表层金属膜2k、2l的线膨胀系数低。表层金属膜2k、2l作为主要材料包含铜，内层金属膜2j作为主要材料包含镍及铁。此外，大于或等于3个金属膜并不限于内层金属膜2j及表层金属膜2k、2l。
<实施方式3的总结>
在本实施方式3中，由于通过内层金属膜2j及表层金属膜2k、2l能够对导体基板2的线膨胀系数进行调整，因此能够对半导体封装件1的翘曲进行抑制，其结果能够提高半导体封装件1的组装性及可靠性。
另外，在本实施方式3中，由于表层金属膜2k作为主要材料包含铜，因此能够容易地使半导体元件3发出的热量扩散。另外，由于表层金属膜2l作为主要材料包含铜，因此能够容易地进行焊料接合。而且，通过利用包含铜的表层金属膜2k、2l夹着包含线膨胀系数比铜低的镍的内层金属膜2j，从而能够对半导体封装件1的翘曲进行抑制。另外，由于铜和镍的接合性比较好，因此能够确保内层金属膜2j和表层金属膜2k、2l的接合性，其结果，能够对上述翘曲进行抑制，并且确保半导体封装件1的制造性及可靠性。
<实施方式4>
图8是表示本实施方式4涉及的半导体装置7的结构的斜视示意图。以下，对本实施方式4所涉及的结构要素中的与上述结构要素相同或类似的结构要素标注相同的参照标号，主要对不同的结构要素进行说明。
如图8所示，就本实施方式4涉及的半导体装置7而言，替代图3的导线76而使用导体框架83。具体而言，电路图案75通过导体框架83与半导体封装件1的第2表面1S2中的导体板38的露出面连接，并且电路图案75与外部电极77连接。即，外部电极77通过导体框架83与导体板38的露出面电连接。此外，导体框架83和外部电极77也可以一体地形成。导体板38的露出面和导体框架83例如可以通过焊料进行接合，也可以进行例如超声波接合。
<实施方式4的总结>
在本实施方式4中，外部电极77通过导体框架83与导体板38的露出面电连接。由此，与使用了导线76的图3的半导体装置7相比能够降低电阻，并且能够容易地进行接合。另外，与导线键合相比，能够缩短加工时间，能够对制造成本进行抑制。
<实施方式5>
图9是表示本实施方式5涉及的半导体装置7的结构的剖面示意图。以下，对本实施方式5所涉及的结构要素中的与上述结构要素相同或类似的结构要素标注相同的参照标号，主要对不同的结构要素进行说明。
如图9所示，本实施方式5涉及的半导体装置7与图4的半导体装置7相同地，具有半导体封装件1、绝缘基板72、第1主电流电路图案73、金属层82。第1主电流电路图案73与实施方式1相同地，例如通过焊料与半导体封装件1的第1表面1S1中的导体基板2的第2主面2S2接合。第1主电流电路图案73与对应于图3的外部电极74的第1主电极87连接。
另外，本实施方式5涉及的半导体装置7还具有绝缘基板84、第2电路图案即第2主电流电路图案85、第3电路图案即控制端子图案86。绝缘基板84与导体板38的露出面及导体片48的露出面相对配置。
第2主电流电路图案85配设于绝缘基板84，与半导体封装件1的第2表面1S2中的导体板38的露出面接合。导体板38的露出面和第2主电流电路图案85例如通过焊料进行接合。第2主电流电路图案85与对应于图3的外部电极77的第2主电极88连接。
控制端子图案86配设于绝缘基板84，与半导体封装件1的第2表面1S2中的导体片48的露出面接合。导体片48的露出面和控制端子图案86例如通过焊料进行接合。控制端子图案86与对应于图3的信号端子79的控制端子89连接。由此，来自半导体装置7外部的控制信号经由信号端子79等向半导体封装件1内的半导体元件3输入。
在绝缘基板72的与配设有第1主电流电路图案73的面相反的面配设冷却用金属层82，在绝缘基板84的与配设有第2主电流电路图案85的面相反的面配设有冷却用金属层90。而且，通过将冷却用金属层82、90直接或间接地冷却，从而从两面对半导体封装件1进行冷却。在进行直接冷却的结构中，通过使冷却用金属层82、90的一部分为水密区域，直接使冷却水与金属层82、90的冷却部分接触而进行冷却。在进行间接冷却的结构中，例如使用钎料、焊料、导热脂等通常的接合材料及方法，将冷却用金属层82、90与冷却鳍片连接。通过对冷却鳍片进行冷却，从而对从半导体元件3产生的热量进行散热。
<实施方式5的总结>
在本实施方式5中，通过对半导体装置7的两面进行冷却的双面冷却构造，能够高效地对半导体封装件1进行冷却。另外，根据通过2块绝缘基板72、84夹着半导体封装件1的本实施方式5的结构，与将多个芯片尺寸比较小的包含SiC的MOSFET并列地单独排列而进行组装的情况相比，能够容易地对半导体装置进行组装。
此外，由于半导体封装件1的面积比单体的半导体元件3大，因此与将半导体元件3直接安装于双面冷却构造的情况相比，能够容易地提高倾斜精度，其结果，能够使双面冷却构造的热阻稳定化。而且，由于使倾斜精度及位置精度提高，因此能够抑制在加压或通过工具固定的情况下产生的对半导体元件的损伤。
此外，本发明可以在其发明的范围内将各实施方式自由地组合，对各实施方式适当进行变形、省略。
虽然对本发明进行了详细说明，但上述说明在所有方面都是例示，本发明并不限定于此。应当理解为，在不脱离本发明的范围的情况下能够想到未例示的无数的变形例。
标号的说明
1半导体封装件，2导体基板，2cf碳纤维，2d槽，2e层叠板，2j内层金属膜，2k、2l表层金属膜，2S1第1主面，2S2第2主面，3半导体元件，4配线用元件，5、76、78导线，6封装材料，7半导体装置，31半导体基板，32f表面电极，33b背面电极，34c控制焊盘，36保护膜，37焊料，38导体板，41配线用基板，42r第1中继焊盘，43r第2中继焊盘，44i内部配线，47焊料，48导体片，73第1主电流电路图案，77外部电极，79信号端子，83导体框架，84绝缘基板，85第2主电流电路图案，86控制端子图案。

Claims (37)

1.一种半导体封装件，其具有：
导体基板；
多个半导体元件，它们与所述导体基板的第1主面接合，具有开关功能；以及
配线用元件，其与所述导体基板的所述第1主面接合，
所述多个半导体元件各自包含：
第1基板；
第1主电极部，其配设于所述第1基板的与所述导体基板相反侧的面；
第2主电极部，其配设于所述第1基板的所述导体基板侧的面，与所述导体基板接合；以及
控制焊盘，其用于对在所述第1主电极部和所述第2主电极部之间流动的电流进行控制，
所述配线用元件包含：
第2基板；
多个第1中继焊盘，它们配设于所述第2基板的与所述导体基板相反侧的面，通过导线与所述多个半导体元件的所述控制焊盘连接；
多个第2中继焊盘，它们配设于所述第2基板的与所述导体基板相反侧的所述面，个数小于或等于所述多个第1中继焊盘的个数；以及
多个配线，它们配设于所述第2基板的与所述导体基板相反侧的所述面，选择性地将所述多个第1中继焊盘和所述多个第2中继焊盘连接，
该半导体封装件还具有：
多个第1导体部件，它们与所述多个半导体元件的所述第1主电极部接合；
多个第2导体部件，它们与所述配线用元件的所述多个第2中继焊盘接合；以及
封装材料，其以使所述多个第1导体部件的与所述导体基板相反侧的面即露出面、所述多个第2导体部件的与所述导体基板相反侧的面即露出面、及所述导体基板的与所述第1主面相反侧的第2主面露出的状态，覆盖所述多个半导体元件、所述配线用元件、所述多个第1导体部件的至少一部分、所述多个第2导体部件的至少一部分、及所述导体基板的所述第1主面。
2.根据权利要求1所述的半导体封装件，其中，
将所述多个半导体元件和所述导体基板接合的接合材料的熔点比焊料的熔点高。
3.根据权利要求1或2所述的半导体封装件，其中，
所述多个半导体元件和所述导体基板通过银类材料或铜类材料进行烧结接合。
4.根据权利要求1或2所述的半导体封装件，其中，
所述多个半导体元件和所述导体基板被进行了扩散接合。
5.根据权利要求1至4中任一项所述的半导体封装件，其中，
还具有保护膜，该保护膜覆盖所述多个半导体元件的端部，并且与所述封装材料相比杨氏模量低。
6.根据权利要求5所述的半导体封装件，其中，
所述保护膜包含聚酰亚胺。
7.根据权利要求1至6中任一项所述的半导体封装件，其中，
所述导体基板作为主要材料包含铜。
8.根据权利要求1至7中任一项所述的半导体封装件，其中，
在所述导体基板的所述第1主面中的除了与所述多个半导体元件及所述配线用元件接合的区域之外的区域配设有凹部。
9.根据权利要求1至6中任一项所述的半导体封装件，其中，
所述导体基板包含内含碳纤维的层叠板。
10.根据权利要求9所述的半导体封装件，其中，
所述碳纤维沿所述多个半导体元件的所述第1基板的平面方向排列。
11.根据权利要求9或10所述的半导体封装件，其中，
所述层叠板作为主要材料包含铝。
12.根据权利要求1至6中任一项所述的半导体封装件，其中，
所述导体基板包含具有大于或等于3个金属膜的层叠金属膜，
所述大于或等于3个金属膜中的在层叠方向上位于内侧的金属膜的线膨胀系数比在该层叠方向上位于外侧的金属膜的线膨胀系数低。
13.根据权利要求12所述的半导体封装件，其中，
所述层叠金属膜包含：
第1金属膜；以及
第2金属膜及第3金属膜，它们各自配设于所述第1金属膜的一个面及另一面，
所述第2金属膜及所述第3金属膜作为主要材料包含铜。
14.根据权利要求13所述的半导体封装件，其中，
所述第1金属膜作为主要材料包含镍及铁。
15.根据权利要求1至14中任一项所述的半导体封装件，其中，
所述多个第1导体部件及所述多个第2导体部件作为主要材料包含铜。
16.根据权利要求1至15中任一项所述的半导体封装件，其中，
所述多个第1导体部件和所述多个半导体元件的所述第1主电极部通过焊料进行了接合。
17.根据权利要求1至16中任一项所述的半导体封装件，其中，
所述多个半导体元件包含化合物半导体。
18.根据权利要求17所述的半导体封装件，其中，
所述多个半导体元件作为所述化合物半导体的主要材料包含碳化硅。
19.根据权利要求1至18中任一项所述的半导体封装件，其中，
所述配线用元件的所述第2基板作为主要材料包含硅。
20.根据权利要求1至18中任一项所述的半导体封装件，其中，
所述配线用元件的所述第2基板包含树脂。
21.根据权利要求1至20中任一项所述的半导体封装件，其中，
所述半导体元件比所述配线用元件薄。
22.根据权利要求1至21中任一项所述的半导体封装件，其中，
所述多个半导体元件各自包含进行通断动作的MOSFET、进行续流动作的体二极管，
能够进行所述MOSFET和所述体二极管的双向通电。
23.一种半导体封装件的制造方法，其是权利要求3所述的半导体封装件的制造方法，在该制造方法中，
将所述多个半导体元件和所述导体基板接合的烧结接合是不伴随加压地使用银类材料进行的。
24.一种半导体封装件的制造方法，其是权利要求5或6所述的半导体封装件的制造方法，在该制造方法中，
在将所述多个半导体元件及所述配线用元件接合于所述导体基板后，使用分配器对所述保护膜的前驱体溶液进行描绘，对该前驱体溶液进行烧制，由此形成所述保护膜。
25.一种半导体封装件的制造方法，其是权利要求1至22中任一项所述的半导体封装件的制造方法，在该制造方法中，
在形成了所述多个第1导体部件后，进行检测所述多个半导体元件内的缺陷的筛选试验。
26.一种半导体装置，其具有至少1个权利要求1至22中任一项所述的半导体封装件。
27.根据权利要求26所述的半导体装置，其中，
至少1个所述半导体封装件构成为，作为单位而包含构成全桥电路的6个半导体封装件。
28.根据权利要求26或27所述的半导体装置，其中，
还具有第1电路图案，该第1电路图案通过焊料与从所述封装材料露出的所述导体基板的所述第2主面接合。
29.根据权利要求28所述的半导体装置，其中，
所述第1电路图案被用作漏极电极。
30.根据权利要求26至29中任一项所述的半导体装置，其中，
还具有控制端子，该控制端子通过导线与所述第2导体部件的所述露出面连接。
31.根据权利要求26至30中任一项所述的半导体装置，其中，
还具有主端子，该主端子通过导线与所述第1导体部件的所述露出面电连接。
32.根据权利要求31所述的半导体装置，其中，
将所述第1导体部件的所述露出面和所述主端子电连接的所述导线作为主要材料包含铜。
33.根据权利要求26至30中任一项所述的半导体装置，其中，
还具有主端子，该主端子通过导体框架与所述第1导体部件的所述露出面电连接。
34.根据权利要求33所述的半导体装置，其中，
所述第1导体部件的所述露出面和所述导体框架通过焊料进行了接合。
35.根据权利要求33所述的半导体装置，其中，
所述第1导体部件的所述露出面和所述导体框架被进行了超声波接合。
36.根据权利要求26或29所述的半导体装置，其中，
还具有：
绝缘基板，其与所述第1导体部件的所述露出面及所述第2导体部件的所述露出面相对配置；
第2电路图案，其配设于所述绝缘基板，与所述第1导体部件的所述露出面接合；以及
第3电路图案，其配设于所述绝缘基板，与所述第2导体部件的所述露出面接合。
37.根据权利要求36所述的半导体装置，其中，
所述第1导体部件的所述露出面和所述第2电路图案通过焊料进行了接合，
所述第2导体部件的所述露出面和所述第3电路图案通过焊料进行了接合。
CN201880099699.8A 2018-11-26 2018-11-26 半导体封装件、其制造方法及半导体装置 Pending CN113169161A (zh)

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