CN113161370A - Array substrate, display panel and display device - Google Patents

Array substrate, display panel and display device Download PDF

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Publication number
CN113161370A
CN113161370A CN202110219806.XA CN202110219806A CN113161370A CN 113161370 A CN113161370 A CN 113161370A CN 202110219806 A CN202110219806 A CN 202110219806A CN 113161370 A CN113161370 A CN 113161370A
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substrate
conductive
array substrate
area
orthographic projection
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CN202110219806.XA
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CN113161370B (en
Inventor
罗甜
陈增辉
颜文晶
郭智文
陈杰坤
廖中亮
余文剑
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Xiamen Tianma Microelectronics Co Ltd
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Xiamen Tianma Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The invention discloses an array substrate, a display panel and a display device, and relates to the technical field of display. The array substrate comprises a display area and a non-display area; the array substrate comprises a substrate; the scanning device also comprises a plurality of scanning lines which extend along a first direction and are arranged along a second direction, and the first direction is intersected with the second direction; the non-display region includes a plurality of conductive portions for discharging static charge on the scan lines having an overlapping area therewith; the overlapping area between the orthographic projection of any conductive part on the substrate and the orthographic projection of the scanning line arranged corresponding to the conductive part on the substrate is S1; the array substrate further comprises a plurality of active layer units which are arranged in an array mode in the display area, and the overlapping area between the orthographic projection of any active layer unit on the substrate and the orthographic projection of the scanning line correspondingly arranged on the active layer unit on the substrate is S2; wherein at least one S1 > S2. The static electricity on the scanning line is released by adding the conductive part in the non-display area, so that the edge pixel units in the display area are protected from being damaged by residual charges.

Description

Array substrate, display panel and display device
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a display panel and a display device.
Background
In the prior art, the manufacturing process of the display panel is complex, and is easily affected by static electricity during the manufacturing process, and the problem of impact damage to the tail end of a scanning line, explosion damage to an edge pixel unit and the like in the panel is easily caused by the accumulation of a large amount of static charges, so that the defects of short circuit, poor point and the like occur in the edge area in the display area of the display panel, and the display effect and the service life of the display panel are affected. Therefore, how to improve the antistatic ability of the edge area of the display panel is in need of solving.
Disclosure of Invention
In view of the above, the present invention provides an array substrate, a display panel and a display device, so as to solve the problem of how to improve the antistatic capability of the edge area of the display panel.
In a first aspect, the present application provides an array substrate, including a display area and a non-display area at least partially surrounding the display area; the array substrate comprises a substrate;
the scanning device also comprises a plurality of scanning lines which extend along a first direction and are arranged along a second direction, and the first direction is intersected with the second direction;
the non-display region includes a plurality of conductive portions for discharging static charge on the scan lines having an overlapping area therewith;
in a direction perpendicular to the plane of the substrate, an overlapping area between an orthographic projection of any one of the conductive parts on the substrate and an orthographic projection of the scanning line arranged corresponding to the conductive part on the substrate is S1;
the array substrate further comprises a plurality of active layer units which are arranged in an array mode in the display area, and the overlapping area of the orthographic projection of any active layer unit on the substrate and the orthographic projection of the scanning line correspondingly arranged to the active layer unit on the substrate is S2 along the direction perpendicular to the plane of the substrate;
wherein at least one S1 > S2.
In a second aspect, the present application provides a display panel including the array substrate.
In a third aspect, the present application provides a display device including the display panel.
Compared with the prior art, the array substrate, the display panel and the display device provided by the invention at least realize the following beneficial effects:
the application provides an array substrate, display panel and display device, through set up a plurality of conducting parts in array substrate's non-display area, and set up the orthographic projection of conducting part at the substrate and have the overlap area rather than the orthographic projection of the scanning line that corresponds the setting at the substrate, through the static charge of conducting part release rather than on the scanning line that has the overlap area, avoid static charge at the terminal accumulation of scanning line, thereby avoid the terminal problem that is wounded by static shock, the fried wound of marginal pixel unit, display panel's antistatic performance is greatly improved, corresponding display device's yields has been improved.
Of course, it is not necessary for any product in which the present invention is practiced to achieve all of the above-described technical effects simultaneously.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a schematic view illustrating a film layer structure of an array substrate according to an embodiment of the present disclosure;
FIG. 2 is a top view of area A of FIG. 1 according to an embodiment of the present disclosure;
FIG. 3 is a top view of FIG. 1 according to an embodiment of the present application;
FIG. 4 is a top view of area A of FIG. 1 according to an embodiment of the present disclosure;
FIG. 5 is a top view of area A of FIG. 1 according to an embodiment of the present disclosure;
FIG. 6 is a top view of area A of FIG. 1 according to an embodiment of the present disclosure;
FIG. 7 is a top view of area A of FIG. 1 according to an embodiment of the present disclosure;
FIG. 8 is a cross-sectional view of a BB' of the scan line of FIG. 7 according to an embodiment of the present disclosure;
FIG. 9 is a cross-sectional view CC' of the metal line of FIG. 7 according to an embodiment of the present application;
FIG. 10 is a top view of area A of FIG. 1 according to an embodiment of the present disclosure;
FIG. 11 is a top view of area A of FIG. 1 according to an embodiment of the present disclosure;
fig. 12 is a schematic view illustrating another film structure of an array substrate according to an embodiment of the present disclosure;
fig. 13 is a schematic view illustrating a further film structure of the array substrate according to the embodiment of the present disclosure;
fig. 14 is a schematic cross-sectional view illustrating a conductive multiplexing active layer unit in an array substrate according to an embodiment of the present application;
fig. 15 is another schematic cross-sectional view illustrating the formation of a conductive multiplexing active layer unit in an array substrate according to an embodiment of the present disclosure;
fig. 16 is a schematic view of a display panel according to an embodiment of the present disclosure;
fig. 17 is a schematic view of a display device according to an embodiment of the present application.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
In the prior art, the manufacturing process of the display panel is complex, and is easily affected by static electricity during the manufacturing process, and the problem of impact damage to the tail end of a scanning line, explosion damage to an edge pixel unit and the like in the panel is easily caused by the accumulation of a large amount of static charges, so that the defects of short circuit, poor point and the like occur in the edge area in the display area of the display panel, and the display effect and the service life of the display panel are affected. Therefore, how to improve the antistatic ability of the edge area of the display panel is in need of solving.
In view of the above, the present invention provides an array substrate, a display panel and a display device, so as to solve the problem of how to improve the antistatic capability of the edge area of the display panel.
Fig. 1 is a schematic diagram illustrating a film layer structure of an array substrate according to an embodiment of the present disclosure, fig. 2 is a top view of a region a in fig. 1 according to an embodiment of the present disclosure, and referring to fig. 1 and fig. 2, the present disclosure provides an array substrate 100 including a display region 10 and a non-display region 20 at least partially surrounding the display region 10; the array substrate 100 includes a substrate 01;
the scanning device also comprises a plurality of scanning lines 11 which extend along a first direction and are arranged along a second direction, and the first direction and the second direction are intersected;
the non-display area 20 includes a plurality of conductive portions 12, the conductive portions 12 for discharging static charges on the scanning lines 11 having an overlapping area therewith;
the overlapping area between the orthographic projection of any conductive part 12 on the substrate 01 and the orthographic projection of the scanning line 11 arranged correspondingly to the conductive part in the direction perpendicular to the plane of the substrate 01 is S1;
the array substrate 100 further includes a plurality of active layer units 13 arranged in an array in the display area 10, and along a direction perpendicular to a plane where the substrate 01 is located, an overlapping area between an orthographic projection of any active layer unit 13 on the substrate 01 and an orthographic projection of the scanning line 11 arranged correspondingly to the orthographic projection of the substrate 01 is S2;
wherein at least one S1 > S2.
Specifically, with continued reference to fig. 1 and fig. 2, the present application provides an array substrate 100, where the array substrate 100 includes a display area 10 and a non-display area 20, and an embodiment of the present application is that the non-display area 20 is disposed around the display area 10; however, the present application is not limited thereto, and the non-display area 20 may be at least partially disposed around the display area 10. The array substrate 100 provided by the present application includes a plurality of scan lines 11, and any one of the scan lines 11 extends along a first direction and is arranged along a second direction, where the first direction and the second direction are intersected, and specifically, the first direction and the second direction are perpendicular.
The array substrate 100 provided by the present application further includes a plurality of conductive portions 12, where the conductive portions 12 are disposed in the non-display area 20; the array substrate 100 includes a substrate 01, and in a direction perpendicular to a plane of the substrate 01, an orthogonal projection of any one of the conductive parts 12 provided in the array substrate 100 on the substrate 01 and an orthogonal projection of the scanning line 11 provided corresponding to the conductive part 12 on the substrate 01 have an overlapping area, so that transmission of electrostatic charges between the conductive part 12 and the scanning line 11 corresponding to the conductive part can be performed, that is, the conductive part 12 additionally provided in the non-display region 20 is used for discharging the electrostatic charges on the scanning line 11 having the overlapping area.
Note that, in the present application, it is not limited whether or not the conductive portion 12 and the scanning line 11 provided corresponding thereto have an electrical connection relationship. The principle of eliminating static electricity on the scanning line 11 by the conducting part 12 is realized by designing based on the principle that positive and negative charges generate directional motion in an electric field, namely, the positive charges move from a high potential to a low potential in the electric field, and the negative charges move from the low potential to the high potential in the electric field.
The application provides an alternative embodiment, an insulating layer is provided between the conductive part 12 and the scanning line 11 correspondingly disposed thereto, so that when the conductive part 12 and the scanning line 11 do not have an electrical connection relationship, the electrostatic charge existing on the scanning line 11 can be driven to move to the conductive part 12 by the potential difference existing between the conductive part 12 and the scanning line 11, that is, the electrostatic charge on the scanning line 11 reaches the corresponding conductive part 12 after being driven by the potential difference to break down the insulating layer, so that the conductive part 12 collects the redundant electrostatic charge on the scanning line 11, the residual electrostatic charge on the scanning line 11 is released, the accumulation of the electrostatic charge at the tail end of the scanning line 11 is avoided, and the problems that the tail end of the scanning line 11 is damaged by electrostatic shock and the edge pixel unit is damaged by explosion are solved; the antistatic capacity of the array substrate 100 can be improved, and the yield of the array substrate 100 can be improved.
It should be noted that, when there is an insulating layer between the conductive portion 12 and the scan line 11, there is a charge in the insulating layer itself, but the object itself does not discharge to the outside because of the balance of the electric quantities of the positive and negative charges. However, when there is a potential difference between the two ends of the insulating layer (specifically, the scan line 11 and the conductive part 12), i.e., when an electric field is formed, an electric field force is applied to the corresponding region of the insulating layer, and the electric field force drives the positive and negative charges in the insulating layer to form a path between the two ends of the potential difference (specifically, the scan line 11 and the conductive part 12), so as to form a directional movement of the charges. That is, the movement of the electrostatic charge on the scanning line 11 to the conductive portion 12 is realized by a passage formed in the insulating layer.
In addition, the array substrate 100 provided by the present application further includes a plurality of active layer units 13 arranged in an array in the display area 10, and along a direction perpendicular to the plane of the substrate 01, the present application sets an overlapping area between an orthographic projection of any conductive portion 12 in the non-display area 20 on the substrate 01 and an orthographic projection of a scanning line 11 correspondingly arranged on the substrate 01 to be S1, and sets an overlapping area between an orthographic projection of any active layer unit 13 on the substrate 01 and an orthographic projection of a scanning line 11 correspondingly arranged on the substrate 01 in the display area 10 to be S2, where the present application provides an optional manner that at least one S1 > S2 exists in the array substrate 100; that is, in the direction perpendicular to the plane of the substrate 01, the overlapping area S1 of the conductive portion 12 and the scanning line 11 in the non-display area 20 is set larger than the overlapping area S2 of the active layer unit 13 and the scanning line 11 in the display area 10; the conductive part 12 with a large overlapping area with the scanning lines 11 is arranged, so that the conductive part 12 has stronger collection capability on static charges existing on the scanning lines 11, the corresponding conductive part 12 is arranged at the tail end of each scanning line 11, each scanning line 11 can be protected, the release effect of the conductive part 12 on residual static charges on each scanning line 11 is improved, and the improvement of the yield of the array substrate 100 is facilitated.
Fig. 3 is a top view of fig. 1 according to an embodiment of the present disclosure, please refer to fig. 1 and fig. 3, in which optionally, any scan line 11 includes a first end 111 and a second end 112 opposite to each other along a first direction;
along the direction perpendicular to the plane of the substrate 01, the orthographic projection of at least 1 conductive part 12 on the substrate 01 at least partially overlaps with the orthographic projection of the first end 111 on the substrate 01, and the orthographic projection of at least 1 conductive part 12 on the substrate 01 at least partially overlaps with the orthographic projection of the second end 112 on the substrate 01.
Specifically, the scan lines 11 disposed in the array substrate 100 extend along a first direction and are arranged along a second direction, and each scan line 11 includes a first end 111 and a second end 112 opposite to each other along the first direction, in other words, each scan line 11 may extend into the non-display area 20 on both sides of the display area 10 in the first direction.
One positional relationship existing between the plurality of conductive portions 12 and the scanning lines 11 disposed in the non-display area 20 is that, along a direction perpendicular to a plane in which the substrate 01 is located, a forward projection of a first end 111 of the same scanning line 11 on the substrate 01 and a forward projection of the conductive portion 12 on the substrate 01 at least partially overlap, and a forward projection of a second end 112 of the same scanning line 11 on the substrate 01 and a forward projection of the conductive portion 12 on the substrate 01 at least partially overlap. So set up for two tip that same scanning line 11 extends to non-display area 20 all can carry out the release of electrostatic charge through the corresponding conducting part 12 that sets up, release the electrostatic charge on a scanning line 11 simultaneously through two tip, are favorable to improving the release effect of electrostatic charge on the scanning line 11, thereby are favorable to promoting corresponding display panel's display effect and life.
It should be noted that, the present application does not limit that each scan line 11 in the array substrate 100 can discharge electrostatic charges through the first end 111 and the second end 112, there may be a portion of the scan line 11 in the array substrate 100 that discharges electrostatic charges through only the first end 111, or there may be a portion of the scan line 11 that discharges electrostatic charges through only the second end 112; the user can carry out corresponding setting and adjustment according to actual demand.
An alternative embodiment is that, for all the scan lines 11 in one array substrate 100, the first end 111 and the second end 112 of each scan line 11 are provided with corresponding conductive portions 12, so that the first end 111 and the second end 112 of each scan line 11 can be used for releasing electrostatic charges into the corresponding conductive portions 12, thereby increasing a release path of the electrostatic charges on the scan lines 11 and improving the release efficiency of the electrostatic charges on the scan lines 11.
It should be noted that, in fig. 2, fig. 3 and the following drawings, the substrate 01 is shown in a perspective view to clearly illustrate that the orthographic projection of the scanning line 11, the conductive part 12 and the like along the direction perpendicular to the plane of the substrate 01 is located in the substrate 01.
Referring to fig. 2 and fig. 3, optionally, along a direction perpendicular to a plane of the substrate 01, an orthographic projection area of each conductive portion 12 on the substrate 01 is W1, and an orthographic projection area of each active layer unit 13 on the substrate 01 is W2;
wherein at least one W1 > W2.
Specifically, the non-display region 20 of the array substrate 100 of the present application includes a plurality of conductive parts 12, and the display region 10 includes a plurality of active layer units 13, and as shown in fig. 2 and 3, the area of the conductive parts 12 is larger than that of the active layer units 13. Specifically, in the direction perpendicular to the plane of the substrate 01, the orthographic projection area of each conductive part 12 on the substrate 01 is set to be W1, the orthographic projection area of each active layer unit 13 on the substrate 01 is set to be W2, and at least one of W1 > W2 is arranged. It should be noted that, the present application provides an alternative arrangement manner, in which the area of the conductive portion 12 in the non-display area 20 is set to be larger than the area of the active layer unit 13 in the display area 10, so as to be beneficial to achieve that the overlapping area of the orthographic projection of one conductive portion 12 and the end of the scanning line 11 on the substrate 01 is larger than the overlapping area of the orthographic projection of one active layer unit 13 and the scanning line 11 on the substrate 01, and to be beneficial to increase the overlapping area of the conductive portion 12 and the end of the scanning line 11. When W1 > W2 is provided, the overlapping area of the conductive portion 12 and the scanning line 11 can be increased, and the ability of the conductive portion 12 to collect and discharge static charge can be improved; specifically, the larger the overlapping area between the orthographic projection of the conductive portion 12 on the substrate 01 and the orthographic projection of the scanning line 11 on the substrate 01 is, the wider the path for transferring the electrostatic charge on the scanning line 11 to the conductive portion 12 is, so that the discharge efficiency of the electrostatic charge on the scanning line 11 is improved, and the phenomenon that the edge portion of the array substrate 100 is damaged by the electrostatic charge is avoided.
The application does not limit that the orthographic projection area of all the conductive parts 12 on the array substrate 100 on the substrate 01 is larger than the orthographic projection area of each active layer unit 13 on the substrate 01, and a user can correspondingly adjust the conductive parts according to actual requirements.
With reference to fig. 2 and fig. 3, optionally, along a direction perpendicular to the plane of the substrate 01, at least a portion of the conductive portions 12 have the same area and shape in the orthographic projection of the substrate 01.
Specifically, the present application provides an alternative embodiment that the orthographic projections of the conductive parts 12 on the substrate 01 have the same area and the same shape, that is, the conductive parts 12 in the array substrate 100 can be selected to be manufactured by the same process, which is beneficial to simplifying the manufacturing process of the array substrate 100 and improving the manufacturing efficiency of the array substrate 100.
In the present application, it is not limited that the orthographic projections of the conductive portions 12 on the substrate 01 have the same area and the same shape as the limitation condition of the array substrate 100, and only some of the conductive portions 12 in the array substrate 100 may have the same area and the same shape on the orthographic projection of the substrate 01, and in addition, the present application may further include a plurality of conductive portions 12 having different areas and different shapes on the orthographic projection of the substrate 01; the user can correspondingly adjust the device according to actual requirements.
With continued reference to fig. 2 and 3, optionally, at least a portion of the conductive portion 12 includes at least one tip.
Specifically, the conductive portion 12 for discharging static charge on the scanning line 11 provided by the present application may be configured such that at least a part of the conductive portion 12 includes a tip, for example, an orthographic projection of the conductive portion 12 on the substrate 01 is rectangular, rhombic, triangular, a droplet shape with a tip, or the like, as long as the conductive portion has at least one tip; such as the diamond shaped conductive sections 12 shown in fig. 2 and 3. The conductive portion 12 with the tip can discharge the electrostatic charges transmitted to the conductive portion 12 on the scan line 11 to the outside in a tip discharge manner, that is, the tip on the conductive portion 12 plays a role in effectively attracting and releasing the electrostatic charges at a fixed point, which is beneficial to improving the capability of the conductive portion 12 in collecting and releasing the electrostatic charges in the corresponding scan line 11, and avoiding the defects of short circuit, poor point and the like caused by electrostatic damage to the edge region in the display area 10 of the array substrate 100.
It should be noted that, the present application does not limit each conductive portion 12 in the array substrate 100 to include at least one tip, and only a portion of the conductive portion 12 may be selectively disposed to have a tip structure; the user can adjust the yield of the array substrate 100 according to actual requirements, such as the degree of influence of the corresponding position of the conductive portion 12 on the yield.
Fig. 4 is another top view of the area a in fig. 1 according to an embodiment of the present disclosure, referring to fig. 1 and fig. 4, optionally, the conductive portion 12 includes a first sub-conductive portion 121 and a second sub-conductive portion 122;
along a direction perpendicular to the plane of the substrate 01, at least one orthogonal projection of the scanning line 11 on the substrate 01 is overlapped with orthogonal projections of the first conductive sub-part 121 and the second conductive sub-part 122 on the substrate 01;
along the first direction, the first sub-conductive part 121 and the second sub-conductive part 122 are both located at the same end of the scanning line 11, and the second sub-conductive part 122 is located at a side of the first sub-conductive part 121 away from the display area 10;
along the direction perpendicular to the plane of the substrate 01, the orthographic projection area of the first sub-conductive part 121 on the substrate 01 is S11, and the orthographic projection area of the second sub-conductive part 122 on the substrate 01 is S12, wherein S12 > S11.
Specifically, one conductive part 12 may be composed of a plurality of sub-conductive parts (e.g., a first sub-conductive part 121 and a second sub-conductive part 122), and in this case, along a direction perpendicular to the plane of the substrate 01, an orthogonal projection of the scan line 11 on the substrate 01, which is correspondingly disposed on the conductive part 12, and orthogonal projections of the first sub-conductive part 121 and the second sub-conductive part 122 on the substrate 01 have overlapping areas, so that the first sub-conductive part 121 and the second sub-conductive part 122 can both be used for releasing electrostatic charges on the scan line 11.
It should be noted that the first sub-conductive part 121 and the second sub-conductive part 122 are both located on the same side of the scanning line 11, that is, along the first direction, the first sub-conductive part 121 and the second sub-conductive part 122 are both overlapped with the orthogonal projection of the same end of the scanning line 11; the second sub-conductive portion 122 may be disposed on a side of the first sub-conductive portion 121 away from the display area 10.
In an alternative embodiment, along a direction perpendicular to a plane of the substrate 01, an orthographic projection area of the first conductive sub-portion 121 in the same conductive portion 12 on the substrate 01 is S11, an orthographic projection area of the second conductive sub-portion 122 on the substrate 01 is S12, and S12 > S11 are set; that is, the orthographic projection area S11 of the first sub-conductive part 121 on the substrate 01 in the same conductive part 12 is smaller than the orthographic projection area S12 of the second sub-conductive part 122 on the substrate 01, and the second sub-conductive part 122 is located on the side of the first sub-conductive part 121 away from the display area 10. In other words, the conductive portion 12 disposed at one end of the scan line 11 for discharging the static charge on the scan line 11 is disposed to point to the non-display area 20 side along the display area 10, and the sub-conductive portions (e.g., the first sub-conductive portion 121 and the second sub-conductive portion 122) of the conductive portion 12 have larger orthographic projection areas. The greater the area of the sub-conductive portions (for example, the second sub-conductive portions 122) is, the greater the ability to attract the accumulation of the static charge, the better the effect for discharging the static charge in the scanning line 11 is, the greater the area of the forward projection of the second sub-conductive portions 122 is, the first sub-conductive portions 121 is, the farther the display area 10 is, the greater the ability of the second sub-conductive portions 122, which are farther the display area 10 side, to collect the static charge on the scanning line 11 can be achieved, and the smaller the number of the residual static charges on the sub-conductive portions (for example, the first sub-conductive portions 121) which are closer to the display area 10.
Furthermore, the static charges on the scan lines 11 collected in the conductive portions 12 are discharged from the conductive portions 12 to the vacant spaces around the conductive portions 12, and a greater amount of static charges are collected by the second sub-conductive portions 122 away from the display area 10, so that the risk that the static charges collected by the conductive portions 12 wander into the display area 10 can be reduced, the risk that the edge devices in the display area 10 are damaged by the static charges can be reduced, and the yield of the array substrate 100 can be further improved.
It should be noted that, in the present application, the shapes of the first sub-conductive portions 121 and the second sub-conductive portions 122 are not specifically limited, for example, the first sub-conductive portions 121 and the second sub-conductive portions 122 may be arranged in similar patterns, or the first sub-conductive portions 121 and the second sub-conductive portions 122 may be arranged in completely different patterns; for example, second sub-conductive portion 122 is provided with more tip structures than first sub-conductive portion 121. The present application is not limited to this, and the user may make corresponding adjustments according to the requirement.
Fig. 5 is another top view of the area a in fig. 1 provided in an embodiment of the present application, please refer to fig. 1, fig. 3, and fig. 5, and optionally, along a direction perpendicular to a plane of the substrate 01, at least one orthogonal projection of the scan line 11 on the substrate 01 overlaps with orthogonal projections of the conductive parts 12 on the substrate 01;
the area of the conductive portion 12 gradually increases along the direction in which the scanning line 11 extends toward both ends thereof, respectively.
Specifically, the present application provides an alternative embodiment that, along a direction perpendicular to the plane of the substrate 01, there is at least one orthogonal projection of the scan line 11 on the substrate 01 and orthogonal projections of the conductive portions 12 on the substrate 01, specifically, an orthogonal projection of at least one end of the scan line 11 on the substrate 01 and orthogonal projections of the conductive portions 12 on the substrate 01 overlap, and also an orthogonal projection of the first end 111 and the second end 112 of the scan line 11 on the substrate 01 and an orthogonal projection of the conductive portions 12 on the substrate 01 may overlap.
Fig. 5 shows only one arrangement of the conductive portion 12 in the non-display area 20 on the right side of the scanning line 11, and the right side of the non-display area 20 on the left side of the scanning line 11 may be referred to as the arrangement of the conductive portion 12. Moreover, the conductive portions 12 disposed corresponding to the same scan line 11 shown in fig. 5 have different shapes, which is only one possible embodiment provided in the present application, and the present application is not limited thereto, and the shapes of the conductive portions 12 may be changed accordingly according to actual requirements. The tips of the two conducting parts 12 close to the display area 10 in fig. 5 face the side far from the display area 10, so that when the conducting parts 12 discharge the collected static charges through the tips, the static charges are discharged towards the non-display area 20, which is beneficial to avoiding the damage to the devices at the edge of the display area 10 caused by the static charges discharged into the display area 10.
When the orthographic projection of the first end 111 of the scanning line 11 on the substrate 01 and the orthographic projection of the conductive parts 12 on the substrate 01 are overlapped along the direction vertical to the plane of the substrate 01, the area of the orthographic projection of the conductive parts 12 on the substrate 01 can be gradually increased along the extending direction of the scanning line 11 to the first end 111; when the orthographic projection of the second end 112 of the scanning line 11 on the substrate 01 is overlapped with the orthographic projection of the conductive parts 12 on the substrate 01, the area of the orthographic projection of the conductive parts 12 on the substrate 01 in the extending direction of the scanning line 11 to the second end 112 can be gradually increased; when the orthographic projections of the first end 111 and the second end 112 of the scanning line 11 on the substrate 01 are overlapped with the orthographic projections of the conductive parts 12 on the substrate 01, the areas of the conductive parts 12 are gradually increased along the direction in which the scanning line 11 extends towards the two ends of the scanning line.
The plurality of conductive parts 12 corresponding to the ends of the scanning lines 11 are arranged along the direction away from the display area 10 in such a manner that the area of the orthographic projection on the substrate 01 is gradually increased, so that the area of the conductive part 12 closest to the edge of the array substrate 100 is the largest, and the area of the conductive part 12 closest to the display area 10 is the smallest. Because the large-area conductive part 12 has stronger capability of attracting and gathering static charges, the static charges in the scanning lines 11 can be attracted as much as possible and gathered to the conductive part 12 with the largest area for releasing, so that the quantity of residual static charges in the direction closer to the display area 10 is smaller, the quantity of static charges further transferred from the conductive part 12 to the display area 10 can be reduced, pixel units at the edge of the display area 10 can be protected from being damaged by the static charges, and defects such as short circuit, poor point and the like of the edge area in the display area 10 can be avoided.
Fig. 6 is another top view of the area a in fig. 1 according to an embodiment of the present disclosure, referring to fig. 1 and fig. 6, optionally, the non-display area 20 further includes at least one metal line 113, and each metal line 113 is electrically connected to one scan line 11;
along the direction vertical to the plane of the substrate 01, the orthographic projection of at least one conductive part 12 on the substrate 01 is overlapped with the orthographic projection of the metal wire 113 on the substrate 01.
Specifically, the present application further provides an alternative embodiment that a plurality of metal lines 113 are additionally disposed in the non-display area 20 of the array substrate 100, at least one metal line 113 is electrically connected to one scan line 11, and specifically, the tail end of the scan line 11 is further electrically connected to one or more metal lines 113. Meanwhile, along the direction perpendicular to the plane of the substrate 01, the orthographic projection of the conductive part 12 on the substrate 01 and the orthographic projection of the metal wire 113 on the substrate 01 have an overlapping area, so that the electrostatic charge on the scanning line 11 can be released to the conductive part 12 through the metal wire 113, the releasing path of the electrostatic charge on the scanning line 11 is increased, and the releasing efficiency of the electrostatic charge on the scanning line 11 is favorably improved.
Note that the conductive portion 12 for discharging the electrostatic charge on the metal wire 113 may be a conductive portion 12 for discharging the electrostatic charge on the scanning line 11 at the same time, such as the conductive portion 12 shown in two regions of the upper right Q1 and the lower right Q2 in fig. 6; the conductive portion 12 that may be provided for each metal line 113 may be used only for discharging the electrostatic charge on the metal line 113, and not used for discharging the electrostatic charge on the remaining metal lines 113/scan lines 11, such as the metal lines 113 and the conductive portions 12 that are provided corresponding to the region Q3 in fig. 6. The arrangement relationship between the metal lines 113 and the conductive portions 12 is not particularly limited, and for example, one conductive portion 12 may correspond to the discharge of electrostatic charges on a plurality of metal lines 113 and/or scan lines 11; the metal lines 113 and the conductive portions 12 may be provided in a one-to-one correspondence relationship, and the conductive portions 12 directly corresponding to the scanning lines 11 may not have a corresponding overlapping area with the metal lines 113.
By arranging the metal wire 113, the static charges at the first end 111 and/or the second end 112 of the scanning line 11 can be dispersed on the metal wire 113, which is beneficial to avoiding the excessive accumulation of the static charges at the end part of the scanning line 11, and the static charges are released to the conducting part 12 through the metal wire 113 and the end part of the scanning line 11, thereby being beneficial to improving the releasing efficiency of the static charges on the scanning line 11, avoiding the problems that the tail end of the scanning line 11 is damaged by static electricity and the edge pixel unit is damaged by explosion, greatly improving the antistatic capability of the array substrate 100, and improving the yield of the array substrate 100.
Fig. 7 is another top view of the area a in fig. 1 provided in an embodiment of the present application, and referring to fig. 1 and fig. 7, optionally, in a direction perpendicular to a plane of the substrate 01, an orthogonal projection of each metal line 113 on the substrate 01 overlaps an orthogonal projection of at least one conductive portion 12 on the substrate 01.
Specifically, after the metal lines 113 are additionally arranged at the tail end of the scanning line 11, each metal line 113 may be at least correspondingly provided with one conductive part 12 for releasing the electrostatic charges thereon, that is, a plurality of conductive parts 12 may be simultaneously used for releasing the electrostatic charges on the same metal line 113, and at this time, along a direction perpendicular to the plane of the substrate 01, the orthographic projection of each metal line 113 on the substrate 01 is respectively overlapped with the orthographic projection of at least one conductive part 12 on the substrate 01. The static charges on one metal wire 113 are simultaneously released through the plurality of conductive parts 12, so that the releasing efficiency of the static charges on the corresponding scanning lines 11 is improved, the problems that the tail ends of the scanning lines 11 are damaged by static electricity and the edge pixel units are damaged by explosion are solved, the antistatic capacity of the array substrate 100 is greatly improved, and the yield of the array substrate 100 is improved.
Specifically, as shown in fig. 7, for example, one metal line 113 may be provided with 3 conductive portions 12, and the arrangement of the conductive portions 12 may be used to collect and separately discharge the residual electrostatic charges in the scan lines 11; one end part of one scanning line 11 can be electrically connected with a plurality of metal wires 113, so that the shunting effect of static charges is improved; and one conductive part 12 can also be used for collecting and releasing the static charges on the plurality of scanning lines 11, and the conductive part 12 with a large area has higher capacity of collecting the static charges, so that the releasing effect of the static charges on the scanning lines 11 is better.
Referring to fig. 6 and 7, alternatively, the metal line 113 and the scan line 11 electrically connected thereto are made of the same material and in the same process.
Specifically, in the manufacturing process, the metal line 113 additionally disposed at one end of the scan line 11 may be made of the same material as the scan line 11 in the same process, so that the manufacturing process of the array substrate 100 may be simplified and the manufacturing efficiency of the array substrate 100 may be improved. It should be noted that this is only an embodiment provided in the present application, and is not limited to the manner of manufacturing the metal line 113 and the scan line 11 in the present application, and the scan line 11 and the metal line 113 may also be made of different materials and manufactured in different processes as long as the metal line 113 can be used to shunt the static charge on the scan line 11. The user can adjust the manufacturing process of the metal lines 113 and the scan lines 11 according to actual requirements.
Fig. 8 is a BB 'cross-sectional view of the scan line of fig. 7 according to an embodiment of the present invention, and fig. 9 is a CC' cross-sectional view of the metal line of fig. 7 according to an embodiment of the present invention, and referring to fig. 7, 8 and 9, alternatively, the cross-sectional area of the metal line 113 along a direction perpendicular to the substrate 01 and along a direction perpendicular to the extending direction of the metal line 113 is D1; the cross-sectional area of the scan line 11 in a direction perpendicular to the substrate 01 and in a direction perpendicular to the extension of the scan line 11 is D2; d1 ═ D2.
Specifically, when the metal line 113 is additionally provided at one end of the scanning line 11, the present application sets the cross-sectional area of the metal line 113 to D1 in a direction perpendicular to the substrate 01 and in an extending direction perpendicular to the metal line 113; in a direction perpendicular to the substrate 01 and in a direction perpendicular to the extension of the scan line 11, the present application sets the cross-sectional area of the scan line 11 to D2, and provides an alternative setting of D1 ═ D2. In other words, the scan line 11 and each metal line 113 electrically connected thereto have the same line width, so that the electrostatic charge shunting effect of the electrostatic charge in the scan line 11 on the metal lines 113 is more balanced, thereby facilitating the uniform discharge of the electrostatic charge to the conductive portion 12 and improving the discharge effect of the electrostatic charge on the scan line 11.
Meanwhile, the present application also provides an alternative embodiment, in which the metal line 113 is electrically connected to the scan line 11, and the extending direction of the metal line is toward the side of the non-display area 20 away from the display area 10, so as to control the electrostatic charge on the metal line 113 to be discharged to the conducting portion 12 at the side away from the display area 10, thereby avoiding the situation that the electrostatic charge discharging position is too close to the display area 10 and further enters the display area 10; this arrangement makes the discharge path of the electrostatic charge in the scanning line 11 more excellent.
The present application is not limited to this, and the metal line 113 and the scan line 11 may be provided with different line widths.
Fig. 10 is another top view of the area a in fig. 1 according to an embodiment of the present disclosure, referring to fig. 1 and fig. 10, optionally, any one of the conductive portions 12 includes a plurality of sub-conductive portions 123 having the same shape, and the sub-conductive portions 123 are electrically connected to each other.
Specifically, any one of the conductive portions 12 may include a plurality of sub-conductive portions 123 having the same shape, and the areas of the plurality of sub-conductive portions 123 may be the same, and the sub-conductive portions 123 are electrically connected to each other, so as to form an integral conductive portion 12. The sub-conductive portions 123 having the same area and shape are simpler in manufacturing process, which is beneficial to improving the manufacturing efficiency of the array substrate 100.
By arranging the conductive part 12 to comprise the plurality of electric connection sub conductive parts 123, the overlapping area between the orthographic projection of the end part of the scanning line 11 on the substrate 01 and the orthographic projection of the conductive part 12 on the substrate 01 is increased, so that the transmission efficiency of static charges in the scanning line 11 is improved, the antistatic capacity of the array substrate 100 is improved, and the yield of the array substrate 100 is improved.
Fig. 11 is another top view of the area a in fig. 1 according to an embodiment of the present disclosure, referring to fig. 1 and fig. 11, optionally, the area of the sub-conductive portion 123 is gradually increased along a direction in which the scan line 11 extends toward two ends of the scan line, respectively.
Specifically, any one of the conductive portions 12 may include a plurality of sub-conductive portions 123 having the same shape, but the area of each of the plurality of sub-conductive portions 123 is not limited to be the same, and for example, the area of each of the plurality of sub-conductive portions 123 may be gradually increased along the direction from the display area 10 to the non-display area 20 (along the direction in which the scanning line 11 extends toward both ends of the scanning line), and the sub-conductive portions 123 are electrically connected to each other to form an integral conductive portion 12.
By arranging the conductive part 12 to comprise the plurality of sub-conductive parts 123 with the areas sequentially increased, the overlapping area between the orthographic projection of the end part of the scanning line 11 on the substrate 01 and the orthographic projection of the conductive part 12 on the substrate 01 can be increased, and the transmission efficiency of the static charges in the scanning line 11 is improved; the static charge in the scanning line 11 can be controlled to be released to the position of the sub-conducting part 123 with a larger area as much as possible, so that the situation that the static charge releasing position is too close to the display area 10 and further enters the display area 10 is avoided; this arrangement makes the discharge path of the electrostatic charge in the scanning line 11 more excellent.
Fig. 12 is a schematic view illustrating another film structure of the array substrate according to the embodiment of the present disclosure, referring to fig. 12, optionally, the array substrate 100 further includes a first insulating layer 14; a first insulating layer 14 is arranged between the conductive part 12 and the scanning line 11 correspondingly arranged;
the dielectric constant of the first insulating layer 14 is K, and K is more than or equal to 5.8 and less than or equal to 6.7.
Specifically, the array substrate 100 further includes a first insulating layer 14, and an insulating layer is included between the conductive portion 12 and the scan line 11, and in this case, the first insulating layer 14 is specifically included between the conductive portion 12 and the scan line 11 disposed corresponding thereto. The present application provides that the dielectric constant of the first insulating layer 14 is 5.8-6.7, and the first insulating layer 14 within the dielectric constant range has a better insulating effect.
And it is necessary to supplement that the first insulating layer 14 may be made of SiO and SiNxTwo layers, wherein, SiO and Poly-Si have good stress matching effect, which is beneficial to reducing Poly-SiLattice defects and interface traps; SiNxThe insulating property is excellent; from SiO and SiNxThe first insulating layer 14 composed of two layers is more capable of satisfying the electrical properties required for the array substrate 100.
Specifically, the electrostatic charge on the scanning line 11 is discharged to the corresponding conductive portion 12 after passing through the first insulating layer 14 by the potential difference existing between the scanning line 11 and the conductive portion 12, and the electrostatic charge on the scanning line 11 is discharged in such a non-contact type charge conduction manner, so that the accumulation of the electrostatic charge at the tail end of the scanning line 11 is avoided, and the problems that the tail end of the scanning line 11 is damaged by static electricity and the edge pixel unit is damaged by explosion are avoided.
Furthermore, the first insulating layer 14 is disposed between the conductive portion 12 and the scan line 11, which is beneficial to avoiding damage to other devices in the array substrate 100 in the process of removing static charges, and improving the yield of the array substrate 100.
Fig. 13 is a schematic view illustrating another film layer structure of the array substrate according to the embodiment of the present disclosure, referring to fig. 13, optionally, the array substrate 100 further includes a first insulating layer 14; a first insulating layer 14 is arranged between the conductive part 12 and the scanning line 11 correspondingly arranged;
the conductive portion 12 is electrically connected to the scanning line 11 provided in correspondence therewith.
Specifically, the array substrate 100 further includes a first insulating layer 14, and an insulating layer is included between the conductive portion 12 and the scan line 11, and in this case, the first insulating layer 14 is specifically included between the conductive portion 12 and the scan line 11 disposed corresponding thereto. In addition to the above-described method of releasing the electrostatic charge on the scanning line 11 in a non-contact manner, the conductive portion 12 may be electrically connected to the scanning line 11 provided in correspondence to the conductive portion, specifically, for example, by forming a hole in the first insulating layer 14, and adding the connection line 141 to the hole, the electrostatic charge on the scanning line 11 may be electrically conducted to the conductive portion 12 to be released.
In addition to the electrical connection between the scan line 11 and the conductive portion 12 by opening a hole in the first insulating layer 14 as shown in fig. 13, a portion of the first insulating layer 14 may be directly removed so that no insulating layer is disposed between the scan line 11 and the conductive portion 12, and the electrical connection between the scan line 11 and the conductive portion 12 is directly achieved by lapping.
Referring to fig. 12 and 13, alternatively, the conductive portion 12 and the active layer unit 13 are made of the same material and manufactured in the same process.
Specifically, the conductive portion 12 and the active layer unit 13 may be disposed in the same film structure of the array substrate 100, that is, at least a portion of the conductive portion 12 and the active layer unit 13 may be made of the same material and manufactured in the same process, which is beneficial to simplifying the manufacturing process of the array substrate 100 and improving the manufacturing efficiency of the array substrate 100.
An alternative embodiment is provided herein, when the active layer unit 13 of the display area 10 is manufactured, the manufacturing range of the active layer unit 13 is expanded to the non-display area 20, and the active layer unit 13 in the non-display area 20 is reused as the conductive part 12 for releasing the electrostatic charge at the end of the scan line 11 extending to the non-display area 20, so as to avoid the problem that the end of the scan line 11 is damaged by electrostatic shock and the edge pixel unit is damaged by explosion.
When the conductive portion 12 and the active layer element 13 are made of the same material and manufactured in the same process, the resistivity ρ of each active layer element 13 is1And resistivity ρ of each conductive portion 122Are equal; the manufacturing thickness L of each active layer unit 13 and each conductive part 12 is also the same; under this condition, when the present application sets the forward projection area W1 of each conductive portion 12 on the substrate 01 to be larger than the forward projection area W2 of each active layer unit 13 on the substrate 01 in the direction perpendicular to the plane of the substrate 01, it is known that the larger the area of the conductive portion 02, the smaller the resistance thereof is, that is, the conductive portion 02 is advantageously reduced in resistance. Where ρ is the resistivity, R is the resistance value, L is the resistance length, and S is the resistance area.
Fig. 14 is a schematic cross-sectional view illustrating formation of a conductive multiplexing active layer unit in an array substrate according to an embodiment of the present disclosure, and fig. 15 is a schematic cross-sectional view illustrating formation of a conductive multiplexing active layer unit in an array substrate according to an embodiment of the present disclosure; referring to fig. 14 and 15, in addition to the above, the process of fabricating the array substrate in the display region in the prior art may be extended to the non-display region, in the non-display region, an opening is controlled on the source electrode (source) of the ILD (interlayer spacer), an opening is controlled on the Drain electrode (Drain) ILD (interlayer spacer), the PLN (planarization layer), the ITO1 (first electrode layer) is not opened, and the PV (passivation layer) is opened; or source/drain ILD (interlayer spacer), PLN (planarization layer), ITO1 (first electrode layer), PV (passivation layer) are not opened; this realizes that the sub-pixel unit in the non-display region is not used for display, but is used only as a conductive portion for releasing residual electrostatic charges existing on the scanning line 11, wherein the film layer functioning as the conductive portion 12 is an active layer poly.
It should be noted that, the sub-pixel units located in the non-display area are not used for displaying contents, but only a few alternative embodiments are provided, and the present application is not limited thereto. As long as the sub-pixel units in the non-display area are controlled to be in an idle state, the active layer poly therein can be used as the conductive part 12 to discharge the electrostatic charge on the scan line 11.
Fig. 16 is a schematic view of a display panel according to an embodiment of the present application, please refer to fig. 16 on the basis of fig. 1 to 13, and based on the same inventive concept, the present application further provides a display panel 200, where the display panel 200 includes the array substrate 100. The array substrate 100 is any one of the array substrates 100 provided herein.
Fig. 17 is a schematic view of a display device according to an embodiment of the disclosure, referring to fig. 17, and based on the same inventive concept, the disclosure further provides a display device 300, where the display device 300 includes a display panel 200. The display panel 200 is any one of the display panels 200 provided in the present application.
It should be noted that, for the embodiments of the display device provided in the embodiments of the present application, reference may be made to the embodiments of the display panel described above, and repeated descriptions are omitted. The display device provided by the application can be: any product and component with a display function, such as a mobile phone, a tablet personal computer, a television, a step wiring area, a notebook computer, a vehicle-mounted display screen, a navigator and the like.
According to the embodiment, the array substrate, the display panel and the display device provided by the invention at least realize the following beneficial effects:
the application provides an array substrate, display panel and display device, through set up a plurality of conducting parts in array substrate's non-display area, and set up the orthographic projection of conducting part at the substrate and have the overlap area rather than the orthographic projection of the scanning line that corresponds the setting at the substrate, through the static charge of conducting part release rather than on the scanning line that has the overlap area, avoid static charge at the terminal accumulation of scanning line, thereby avoid the terminal problem that is wounded by static shock, the fried wound of marginal pixel unit, display panel's antistatic performance is greatly improved, corresponding display device's yields has been improved.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims (18)

1. The array substrate is characterized by comprising a display area and a non-display area at least partially surrounding the display area; the array substrate comprises a substrate;
the scanning device also comprises a plurality of scanning lines which extend along a first direction and are arranged along a second direction, and the first direction is intersected with the second direction;
the non-display region includes a plurality of conductive portions for discharging static charge on the scan lines having an overlapping area therewith;
in a direction perpendicular to the plane of the substrate, an overlapping area between an orthographic projection of any one of the conductive parts on the substrate and an orthographic projection of the scanning line arranged corresponding to the conductive part on the substrate is S1;
the array substrate further comprises a plurality of active layer units which are arranged in an array mode in the display area, and the overlapping area of the orthographic projection of any active layer unit on the substrate and the orthographic projection of the scanning line correspondingly arranged to the active layer unit on the substrate is S2 along the direction perpendicular to the plane of the substrate;
wherein at least one S1 > S2.
2. The array substrate of claim 1, wherein any one of the scan lines comprises a first end and a second end opposite along the first direction;
along the direction perpendicular to the plane of the substrate, at least 1 orthographic projection of the conductive parts on the substrate at least partially overlaps with the orthographic projection of the first end on the substrate, and at least 1 orthographic projection of the conductive parts on the substrate at least partially overlaps with the orthographic projection of the second end on the substrate.
3. The array substrate of claim 1, wherein along a direction perpendicular to the plane of the substrate, the area of the conductive portion projected onto the substrate is W1, and the area of the active layer unit projected onto the substrate is W2;
wherein at least one W1 > W2.
4. The array substrate of claim 1, wherein at least a portion of the conductive portions have the same area and shape in the orthographic projection of the substrate along a direction perpendicular to the plane of the substrate.
5. The array substrate of claim 1, wherein at least a portion of the conductive portion comprises at least one tip.
6. The array substrate of claim 1, wherein the conductive portion comprises a first sub-conductive portion and a second sub-conductive portion;
along a direction perpendicular to the plane of the substrate, at least one orthographic projection of the scanning line on the substrate is overlapped with the orthographic projections of the first conductive sub-part and the second conductive sub-part on the substrate;
along the first direction, the first sub-conductive part and the second sub-conductive part are both positioned at the same end of the scanning line, and the second sub-conductive part is positioned at one side of the first sub-conductive part, which is far away from the display area;
the area of the orthographic projection of the first sub-conductive part on the substrate is S11, and the area of the orthographic projection of the second sub-conductive part on the substrate is S12, wherein S12 is more than S11.
7. The array substrate of claim 1, wherein along a direction perpendicular to the plane of the substrate, at least one orthographic projection of the scan line on the substrate overlaps with orthographic projections of the conductive parts on the substrate;
the area of the conductive part is gradually increased along the direction in which the scanning line extends toward both ends thereof, respectively.
8. The array substrate of claim 1, wherein the non-display area further comprises at least one metal line, and each metal line is electrically connected with one scan line;
along the direction perpendicular to the plane of the substrate, at least one conductive part is included, and the orthographic projection of the conductive part on the substrate is overlapped with the orthographic projection of the metal wire on the substrate.
9. The array substrate of claim 8, wherein an orthogonal projection of each metal line on the substrate overlaps an orthogonal projection of at least one of the conductive portions on the substrate in a direction perpendicular to a plane of the substrate.
10. The array substrate of claim 8, wherein the metal lines and the scan lines electrically connected thereto are made of the same material and in the same process.
11. The array substrate of claim 8, wherein the cross-sectional area of the metal line in a direction perpendicular to the substrate and in a direction perpendicular to the extension direction of the metal line is D1; the cross-sectional area of the scan line in a direction perpendicular to the substrate and in a direction perpendicular to the extension of the scan line is D2; d1 ═ D2.
12. The array substrate of claim 1, wherein any one of the conductive portions comprises a plurality of sub-conductive portions with the same shape, and the sub-conductive portions are electrically connected with each other.
13. The array substrate of claim 12, wherein the area of the sub-conductive portion gradually increases along a direction in which the scan line extends toward both ends thereof.
14. The array substrate of claim 1, wherein the array substrate further comprises a first insulating layer; the first insulating layer is arranged between the conductive part and the scanning line correspondingly arranged with the conductive part;
the dielectric constant of the first insulating layer is K, and K is more than or equal to 5.8 and less than or equal to 6.7.
15. The array substrate of claim 1, wherein the array substrate further comprises a first insulating layer; the first insulating layer is arranged between the conductive part and the scanning line correspondingly arranged with the conductive part;
the conductive part is electrically connected with the scanning line correspondingly arranged with the conductive part.
16. The array substrate of claim 1, wherein the conductive portion and the active layer unit are made of the same material and in the same process.
17. A display panel comprising the array substrate according to any one of claims 1 to 16.
18. A display device comprising the display panel according to claim 17.
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