CN113156216B - Testing device and method for calibrating and testing parasitic inductance of half-bridge module - Google Patents
Testing device and method for calibrating and testing parasitic inductance of half-bridge module Download PDFInfo
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- CN113156216B CN113156216B CN202110445247.4A CN202110445247A CN113156216B CN 113156216 B CN113156216 B CN 113156216B CN 202110445247 A CN202110445247 A CN 202110445247A CN 113156216 B CN113156216 B CN 113156216B
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
- G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
- G01R27/2611—Measuring inductance
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Abstract
The invention discloses a testing device for calibrating and testing parasitic inductance of a half-bridge module and a method for improving testing precision, which comprises a testing substrate, wherein the following access ports are arranged on the testing substrate (1): open calibration access ports (201) and (202) and power supply terminal access ports (203) to (208) in a first region, short calibration access ports (301) and (302) and power supply terminal access ports (303) to (308) in a second region, test circuit access ports (401) and (402) and power supply terminal access ports (403) to (408) in a third region; wherein the arrangement positions of the power supply terminal access ports (203) - (208) in the first area are consistent with the arrangement positions of the power supply terminal access ports (303) - (308) in the second area and the arrangement positions of the power supply terminal access ports (403) - (408) in the third area; the short circuit calibration access ports (301) and (302) are interconnected by a metal wire (5), and other access ports on the test substrate 1 are disconnected.
Description
Technical Field
The invention relates to the field of electrical measurement, in particular to a testing device for calibrating and testing parasitic inductance of a half-bridge module and a testing method for improving testing precision.
Background
In the development and packaging process of the half-bridge module, parasitic inductance introduced by device interconnection has a great influence on the performance of the module. Especially for half-bridge modules prepared on the basis of SiC, gaN-based power electronics devices, the sensitivity of the devices to parasitic inductances is higher due to the high switching speeds of the devices. Parasitic inductance in the power loop will cause overshoot and oscillation of the on-off voltage of the module, resulting in serious electromagnetic interference problems. Therefore, the parasitic inductance test characterization of the half-bridge module is necessary.
The current method for representing the parasitic inductance of the half-bridge module is mainly realized based on a digital bridge tester. However, since the parasitic inductance value of the half-bridge module to be tested is generally in the nH order, higher test accuracy is required for the digital bridge tester. In the prior art, due to crosstalk inductance between power supply wires, calibration is inaccurate, inductance introduced by a test connecting wire of a tester itself has higher error influence on a test result, jitter of the connecting wire in the test process, displacement of a test probe and the like can cause change of the test result.
Disclosure of Invention
In view of the above, the present invention is directed to a testing device and a testing method for calibrating and testing parasitic inductance of a half-bridge module, so as to solve the problem of inaccurate calibration caused by crosstalk inductance between power supply wires in the prior art.
To achieve the above object, the present invention provides a test apparatus for calibrating and testing parasitic inductance of a half-bridge module, comprising:
a test substrate 1;
the following access ports provided on the test substrate 1: open calibration inlets 201 and 202 and power supply terminal inlets 203 to 208 in the first region, short calibration inlets 301 and 302 and power supply terminal inlets 303 to 308 in the second region, test circuit inlets 401 and 402 and power supply terminal inlets 403 to 408 in the third region;
wherein the arrangement positions of the power supply terminal access ports 203 to 208 in the first area are consistent with the arrangement positions of the power supply terminal access ports 303 to 308 in the second area and the arrangement positions of the power supply terminal access ports 403 to 408 in the third area;
the short-circuit calibration access ports 301 and 302 are interconnected by a metal wire 5 and disconnected from the power supply terminal access ports 303 to 308 in the second region;
the open calibration access ports 201 and 202 are disconnected from each other and from the power supply terminal access ports 203 to 208 in the first region;
the test circuit access ports 401 and 402 are disconnected from each other, and are disconnected from the power supply terminal access ports 403 to 408 in the third region.
The spacing between open calibration access points 201 and 202 is equal to the spacing between test circuit access points 401 and 402.
According to an embodiment of the present disclosure, the power supply terminal 403 in the third area is a power supply terminal of the upper bridge arm driving chip of the half-bridge module.
The third power supply terminal 404 is a signal input terminal of the upper bridge arm driving chip of the half-bridge module.
The third region has electrical terminals 405 for supplying power to the upper arm driver chip of the half-bridge module.
The power supply terminal 406 in the third region is the power supply terminal of the lower bridge arm driving chip of the half-bridge module.
The power supply terminal 407 in the third area is a signal input end of a lower bridge arm driving chip of the half-bridge module.
The power supply terminal 408 in the third region supplies power to the lower bridge arm driving chip of the half-bridge module.
The invention also provides a test method for improving the test precision, which adopts the test device and combines a digital bridge tester to test the parasitic inductance of the half-bridge module with the drive.
According to an embodiment of the present disclosure, with the above-mentioned test device, performing parasitic inductance test on a half-bridge module with a drive in combination with a digital bridge tester includes:
two test lines of the digital bridge tester are respectively connected with open circuit calibration access ports 201 and 202, and power supply terminal access ports 203-208 in the first area are connected with a power supply source to perform open circuit calibration test;
two test lines of the digital bridge tester are respectively connected with the short circuit calibration access ports 301 and 302, and the power supply terminal access ports 303-308 in the second area are connected with a power supply source to perform short circuit calibration test;
connecting the positive pole of the half-bridge module power loop with the test circuit access port 401, connecting the negative pole of the half-bridge module power loop with the test circuit access port 402, and connecting the power supply terminal access ports 403-408 in the third area with the corresponding functional ports on the half-bridge module in sequence and with the power supply; and then two test wires of the digital bridge tester are respectively connected with the test circuit access ports 401 and 402 for testing.
Based on the technical scheme, compared with the prior art, the invention has at least one or a part of the following beneficial effects:
1. according to the testing device, the power supply terminals at the same positions as the testing circuit are arranged in the open-circuit calibration circuit and the short-circuit calibration circuit, crosstalk generated by the power supply wires is simulated, and in the calibration process, crosstalk inductance generated between the power supply wires is calibrated, so that the testing accuracy is improved.
2. The test device is provided with the power supply port while the test port is arranged, and is suitable for testing the parasitic inductance of the half-bridge module with the drive.
3. The testing device can avoid testing errors caused by movement of the testing connecting wire in the testing process by connecting the testing connecting wire of the digital bridge tester at the access port on the testing substrate.
Drawings
FIG. 1 is a schematic diagram of a test apparatus for calibration testing of parasitic inductance of a half-bridge module according to the present invention;
FIG. 2 is a schematic diagram of a test apparatus for calibrating and testing parasitic inductance of a half-bridge module according to the present invention used in conjunction with a digital bridge tester.
Detailed Description
The present invention will be further described in detail below with reference to specific embodiments and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.
The invention provides a testing device and a testing method for improving testing precision of parasitic inductance of a half-bridge module, and fig. 1 schematically shows an overall design diagram of the testing device of the invention in an embodiment of the invention.
As shown in fig. 1, the test device is used for calibrating and testing parasitic inductance of the half-bridge module, and comprises: test substrate 1, open calibration inlets 201 and 202, power supply terminal inlets 203 to 208, short calibration inlets 301 and 302, power supply terminal inlets 303 to 308, test circuit inlets 401 and 402, and power supply terminal inlets 403 to 408.
According to an embodiment of the present disclosure, the following access ports are included on the test substrate 1: open calibration inlets 201 and 202 and power supply terminal inlets 203 to 208 in the first region, short calibration inlets 301 and 302 and power supply terminal inlets 303 to 308 in the second region, test circuit inlets 401 and 402 and power supply terminal inlets 403 to 408 in the third region.
The arrangement positions of the power supply terminal inlets 203 to 208 in the first region are identical to those of the power supply terminal inlets 303 to 308 in the second region and the power supply terminal inlets 403 to 408 in the third region.
The short circuit calibration inlets 301 and 302 are interconnected by the metal wire 5 and are disconnected from the power supply terminal inlets 303 to 308 in the second region.
The open calibration access ports 201 and 202 are disconnected from each other and from the power supply terminal access ports 203 to 208 in the first region.
The test circuit access ports 401 and 402 are disconnected from each other, and are disconnected from the power supply terminal access ports 403 to 408 in the third region.
According to the embodiment of the invention, the first area is an open circuit calibration area, the second area is a short circuit calibration area, and the third area is a test circuit area. By arranging the power supply terminal access ports which are completely identical to the power supply terminal access ports of the third area in the first area and the second area, the connection mode of the power supply of the first area and the second area of the testing device is completely identical to the connection mode of the power supply of the testing circuit area, and crosstalk inductance generated by connecting wires of the testing circuit and the power supply can be respectively simulated in the first area and the second area.
The spacing between open calibration access points 201 and 202 is equal to the spacing between test circuit access points 401 and 402.
According to an embodiment of the present invention, the distance between the test circuit inlets 401 and 402 is determined according to the actual size of the half-bridge module to be tested, and for example, the distance may be 10mm, 15mm, 18mm, or 20mm. The distance between the open calibration interfaces 201 and 202 is kept consistent with the distance between the test circuit interfaces 401 and 402, and the test environment in which the module to be tested is placed on the test substrate 1 is simulated in the first area, so that when the digital bridge tester 6 performs open calibration, the test environment includes an air medium environment and is consistent with that when the half-bridge module to be tested is actually tested.
According to the embodiment of the invention, the power supply terminal 403 in the third area is the power supply terminal of the upper bridge arm driving chip of the half-bridge module. The third power supply terminal 404 is a signal input terminal of the upper bridge arm driving chip of the half-bridge module. The third region has electrical terminals 405 for supplying power to the upper arm driver chip of the half-bridge module. The power supply terminal 406 in the third region is the power supply terminal of the lower bridge arm driving chip of the half-bridge module. The power supply terminal 407 in the third area is a signal input end of a lower bridge arm driving chip of the half-bridge module. The power supply terminal 408 in the third region supplies power to the lower bridge arm driving chip of the half-bridge module.
According to the embodiment of the invention, the test device is used for carrying out parasitic inductance test on the half-bridge module with the drive by combining the digital bridge tester 6.
The invention also provides a test method for improving the test precision, which comprises the following steps:
the two test lines of the digital bridge tester 6 are connected to the open circuit calibration access ports 201 and 202, respectively, and the power supply terminal access ports 203 to 208 in the first region are connected to the power supply source, so that the open circuit calibration test is performed.
According to the embodiment of the invention, the power supply terminal access port 203 in the first area is connected with the positive pole of the power supply loop No. 1 of the power supply source, and applies the working voltage of the bridge arm driving chip on the half-bridge circuit. The first area power supply terminal access port 204 is connected to the positive electrode of the power supply circuit No. 2 of the power supply source, and applies the driving signal voltage of the bridge arm driving chip on the half-bridge circuit. The first area power supply terminal inlet 205 is connected to the negative electrodes of the power supply No. 1 power supply circuit and the power supply No. 2 power supply circuit. The first area power supply terminal access port 206 is connected to the positive electrode of the power supply 3 power supply loop, and the working voltage of the lower bridge arm driving chip of the half-bridge circuit is applied. The first area power supply terminal inlet 207 is connected to the positive electrode of the power supply circuit No. 4 of the power supply source, and applies the driving signal voltage of the lower arm driving chip of the half-bridge circuit. The first area power supply terminal access port 208 is connected to the cathodes of the power supply No. 3 power supply circuit and the power supply No. 4 power supply circuit, and is grounded. Open circuit calibration testing was performed.
Two test lines of the digital bridge tester 6 are respectively connected with the short circuit calibration access ports 301 and 302, and the power supply terminal access ports 303 to 308 in the second area are connected with a power supply source to perform short circuit calibration test;
according to the embodiment of the invention, the connection mode and the power supply voltage of the power supply terminal access ports 303 to 308 in the second area are completely consistent with the connection mode and the power supply voltage of the power supply terminal access ports 203 to 208 in the first area, and short circuit calibration test is performed;
connecting the positive pole of the half-bridge module power loop with the test circuit access port 401, connecting the negative pole of the half-bridge module power loop with the test circuit access port 402, and connecting the power supply terminal access ports 403-408 in the third area with the corresponding functional ports on the half-bridge module in sequence and with the power supply; and then two test wires of the digital bridge tester are respectively connected with the test circuit access ports 401 and 402 for testing.
According to an embodiment of the present invention, the positive pole of the half-bridge module power loop is connected to the test circuit access port 401, and the negative pole of the half-bridge module power loop is connected to the test circuit access port 402. The power supply positive end of the upper bridge arm driving chip is connected with the power supply terminal access port 403 of the test circuit. The upper bridge arm driving chip signal input end is connected with the test circuit power supply terminal access port 404. The upper bridge arm driving chip power supply negative terminal is connected with the test circuit power supply terminal access port 405. The power supply positive end of the lower bridge arm driving chip is connected with the power supply terminal access port 406 of the test circuit. The signal input end of the lower bridge arm driving chip is connected with the power supply terminal access port 407 of the test circuit. The lower bridge arm driver chip supply negative terminal is connected to the test circuit supply terminal access port 408.
According to the embodiment of the present invention, the connection patterns and the power supply voltages of the power supply terminal access ports 403 to 408 in the third region and the power supply in the first region are completely identical, and the test is performed.
According to the embodiment of the invention, the connection modes of the interfaces 203-208 of the first regional power supply terminal, the interfaces 303-308 of the second regional power supply terminal and the interfaces 403-408 of the third regional power supply terminal with the power supply and the applied power supply voltage are consistent, and when the open circuit calibration and the short circuit calibration are performed before the digital bridge test, the conditions of the power supply connection in the test process are simulated respectively in the open circuit calibration and the short circuit calibration processes, so that the crosstalk inductance introduced by the power supply connection can be calibrated in the open circuit calibration and the short circuit calibration processes, and the test result is more accurate when the calibrated digital bridge tester 6 tests the half bridge module to be tested.
According to the embodiment of the invention, when the digital bridge tester 6 performs open circuit calibration, short circuit calibration and test, the test connecting wires are connected to the corresponding terminal access ports on the test substrate 1, and the test connecting wires cannot move randomly in the test process, so that measurement errors are caused, and further the test precision is improved.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the invention thereto, but to limit the invention thereto, and any modifications, equivalents, improvements and equivalents thereof may be made without departing from the spirit and principles of the invention.
Claims (9)
1. A test device for calibration testing of parasitic inductance of a half-bridge module, comprising:
a test substrate (1);
the following access ports are provided on the test substrate (1): a first open calibration access (201) and a second open calibration access (202) and a first power supply terminal access (203) in a first region to a sixth power supply terminal access (208) in the first region, a first short calibration access (301) and a second short calibration access (302) and a first power supply terminal access (303) in a second region to a sixth power supply terminal access (308) in the second region, a first test circuit access (401) and a second test circuit access (402) and a first power supply terminal access (403) in a third region to a sixth power supply terminal access (408) in the third region;
the arrangement positions of the first power supply terminal access opening (203) in the first area to the sixth power supply terminal access opening (208) in the first area and the arrangement positions of the first power supply terminal access opening (303) in the second area to the sixth power supply terminal access opening (308) in the second area and the arrangement positions of the first power supply terminal access opening (403) in the third area to the sixth power supply terminal access opening (408) in the third area are consistent;
the first short circuit calibration access port (301) and the second short circuit calibration access port (302) are interconnected through a metal wire (5) and are disconnected from the first power supply terminal access port (303) in the second area to the sixth power supply terminal access port (308) in the second area;
the first open calibration access port (201) is disconnected from the second open calibration access port (202), and is disconnected from the first power supply terminal access port (203) in the first area to the sixth power supply terminal access port (208) in the first area;
the first test circuit access port (401) is disconnected from the second test circuit access port (402), and is disconnected from the first power supply terminal access port (403) in the third region to the sixth power supply terminal access port (408) in the third region;
the first area is an open circuit calibration area, the second area is a short circuit calibration area, and the third area is a test circuit area.
2. The test device of claim 1, a spacing between the first open calibration access (201) and the second open calibration access (202) being equal to a spacing between the first test circuit access (401) and the second test circuit access (402).
3. The test device according to claim 1, wherein the first supply terminal access (403) in the third area is a half-bridge module upper bridge arm drive chip supply terminal.
4. The test device of claim 1, wherein the second supply terminal access (404) in the third region is a half-bridge module upper leg drive chip signal input.
5. The test device of claim 1, wherein the third power terminal access (405) in the third region is a power ground for a half-bridge module upper leg driver chip.
6. The test device of claim 1, wherein the fourth supply terminal access (406) in the third region is a half-bridge module lower leg driver chip supply terminal.
7. The test device according to claim 1, wherein the fifth power supply terminal access (407) in the third region is a half-bridge module lower bridge arm driving chip signal input.
8. The test device of claim 1, the sixth power terminal access (408) in the third region providing power ground for a lower leg driver chip of the half-bridge module.
9. A test method for improving test accuracy, using the test device of any one of claims 1-8, in combination with a digital bridge tester for parasitic inductance testing of a half-bridge module with a drive, comprising:
two test lines of the digital bridge tester are respectively connected with a first open circuit calibration access port (201) and a second open circuit calibration access port (202), and a first power supply terminal access port (203) in a first area to a sixth power supply terminal access port (208) in the first area are connected with a power supply source to perform open circuit calibration test;
two test lines of the digital bridge tester are respectively connected with a first short circuit calibration access port (301) and a second short circuit calibration access port (302), and a first power supply terminal access port (303) in a second area to a sixth power supply terminal access port (308) in the second area are connected with a power supply source to perform short circuit calibration test;
connecting the positive electrode of the half-bridge module power loop with a first test circuit access port (401), connecting the negative electrode of the half-bridge module power loop with a second test circuit access port (402), and sequentially connecting a first power supply terminal access port (403) in a third area to a sixth power supply terminal access port (408) in the third area with corresponding functional ports on the half-bridge module and connecting with a power supply; and then, respectively connecting the two test wires of the digital bridge tester with the first test circuit access port (401) and the second test circuit access port (402) to perform a test.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110445247.4A CN113156216B (en) | 2021-04-23 | 2021-04-23 | Testing device and method for calibrating and testing parasitic inductance of half-bridge module |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110445247.4A CN113156216B (en) | 2021-04-23 | 2021-04-23 | Testing device and method for calibrating and testing parasitic inductance of half-bridge module |
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| Publication Number | Publication Date |
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| CN113156216A CN113156216A (en) | 2021-07-23 |
| CN113156216B true CN113156216B (en) | 2023-06-13 |
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Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7067842B1 (en) * | 2004-02-13 | 2006-06-27 | Altera Corporation | Method and apparatus for monitoring parasitic inductance |
| DE102011085555A1 (en) * | 2011-11-02 | 2013-05-02 | Robert Bosch Gmbh | Variable resistor arrangement, bridge circuit and method for calibrating a bridge circuit |
| CN102495294B (en) * | 2011-11-30 | 2014-11-26 | 台达电子企业管理（上海）有限公司 | System and method for testing parasitic inductance |
| CN104991131A (en) * | 2015-06-12 | 2015-10-21 | 中国科学院电工研究所 | Flexible direct-current power-transmission converter-valve half-bridge structure power module test device |
| CN110138195B (en) * | 2019-05-24 | 2020-10-27 | 哈尔滨工业大学 | Nondestructive buffer circuit for restraining voltage spike and current resonance of GaN half-bridge module and test circuit thereof |
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