CN210230705U - Chip-level Hall device testing and sorting device - Google Patents
Chip-level Hall device testing and sorting device Download PDFInfo
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- CN210230705U CN210230705U CN201920989131.5U CN201920989131U CN210230705U CN 210230705 U CN210230705 U CN 210230705U CN 201920989131 U CN201920989131 U CN 201920989131U CN 210230705 U CN210230705 U CN 210230705U
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Abstract
The utility model relates to a hall device capability test equipment technical field, concretely relates to chip-level hall device test sorting unit, aim at solving among the prior art hall device's test sorting need be accomplished after the chip encapsulates into the device, have the problem that test cost is big, test cycle is long, its technical essential lies in including the probe platform, is used for connecting four pins of hall device, and marks the hall device that the output is unqualified; the electromagnet is arranged on the automatic probe station and used for providing a constant magnetic field for the Hall device; the current source is connected with two pins of the Hall device and is used as an input end; and the universal meter is connected with the other two pins of the Hall device and is used as an output end to test the Hall voltage. The utility model discloses effectively reduce the encapsulation cost, shortened test cycle.
Description
Technical Field
The utility model relates to a hall device capability test equipment technical field, concretely relates to hall device test sorting unit of chip level.
Background
The hall element is a magnetic sensor based on the hall effect. They can be used to detect magnetic fields and their changes and can be used in various fields related to magnetic fields. The hall effect is a physical phenomenon in which a magnetic field acts on carriers in a current-carrying metal conductor or semiconductor, and a potential difference occurs in a lateral direction. The hall device has many advantages, and is currently used as a hall current sensor, a hall power sensor, a hall speed sensor, and the like.
The Hall voltage is an important parameter for evaluating the performance of the Hall device. At present, Hall devices in the market mostly adopt a four-pin symmetrical structure, and a Hall voltage testing method mainly comprises the steps of placing the packaged Hall devices in a magnetic field environment, applying input current/voltage to two nonadjacent pins, and testing and outputting Hall voltage on the other two nonadjacent pins. Although the method can effectively measure the Hall voltage and complete the sorting of the devices, the testing must be carried out after the chips are packaged into the devices, thereby increasing the testing cost and the testing period.
Therefore, a chip-level hall device test sorting apparatus is needed.
SUMMERY OF THE UTILITY MODEL
Therefore, the to-be-solved technical problem of the utility model lies in overcoming among the prior art test of hall device and sorting and need accomplish after the chip encapsulates into the device, has the defect that test cost is big, test cycle length to a chip-level hall device test sorting unit is provided.
The above technical purpose of the present invention can be achieved by the following technical solutions:
a chip-level Hall device testing and sorting device comprises:
the probe station is used for connecting four pins of the Hall device and calibrating the Hall device with unqualified output;
the electromagnet is arranged on the probe station and used for providing a constant magnetic field for the Hall device;
the current source is connected with two pins of the Hall device and is used as an input end;
and the universal meter is connected with the other two pins of the Hall device and is used as an output end to test the Hall voltage.
Optionally, the probe station comprises a probe station main body, a microscope is arranged at the top of the probe station main body, a wafer bearing table is arranged under the microscope, and a probe device and a dotter device are arranged on two sides of the wafer bearing table.
Optionally, the probe device includes a probe frame installed on the probe station main body, a probe is arranged on one side of the probe frame close to the wafer bearing table, and a fixed lock button, a front and rear adjusting button, a left and right adjusting button, and an up and down adjusting button are distributed on the probe frame.
Optionally, the dotting device includes a dotting support installed on the probe station main body, a dotting line is arranged on one side of the dotting support close to the support table, the dotting line is connected with an ink cartridge, and a jacking screw, a limiting nut and a positioning nut are distributed on the dotting support.
Optionally, the electromagnet, the current source, and the multimeter are all connected to a control end, the control end includes at least one personal computer and at least one programmable logic controller that uses a stack algorithm to store data, and the personal computer is in communication connection with the programmable logic controller to achieve data synchronization.
Optionally, the personal computer and the programmable logic controller perform mutual checking of the working state through interaction of heartbeat signals.
Optionally, the control terminal, the electromagnet, the current source, and the multimeter perform mutual inspection of working states through interaction of handshake signals.
The utility model discloses a chip-level hall device test sorting unit, through exerting the electric current size control magnetic field intensity on the electro-magnet, directly provide controllable invariable magnetic field for the hall device, two pins that recycle probe platform corresponds the hall device are connected to the current source on as the input, its other two pins are connected to the universal meter on as the output, with this test hall voltage, and rely on the probe platform can mark the unqualified hall device of output in the test, the packaging cost has effectively been reduced, test cycle has been shortened.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the technical solutions in the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic block diagram of a chip-scale hall device testing and sorting apparatus according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a chip-scale hall device testing and sorting apparatus according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a probe device in the chip-scale hall device testing and sorting apparatus according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a dotter device in the chip-scale hall device testing and sorting apparatus according to an embodiment of the present invention.
Description of reference numerals:
01. a Hall device; 1. a probe station; 11. a probe station main body; 12. a microscope; 13. a wafer bearing table; 14. a probe device; 141. a probe holder; 142. a probe; 143. fixing the lock knob; 144. a front and rear adjusting knob; 145. A left and right adjusting button; 146. an upper and lower adjusting knob; 15. a dotter device; 151. a dotter support; 152. dotting; 153. an ink cartridge; 154. jacking the screw tightly; 155. a limit nut; 156. positioning a nut; 2. an electromagnet; 3. a current source; 4. a universal meter; 5. a control end; 51. a personal computer; 52. a programmable logic controller.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
A chip-level Hall device testing and sorting device is shown in figure 1 and comprises a probe platform 1, an electromagnet 2, a current source 3 and a universal meter 4, wherein the probe platform 1 is used for connecting four pins of a Hall device 01 and calibrating the Hall device 01 with unqualified output, the electromagnet 2 is arranged on the probe platform 1 and used for providing a constant magnetic field for the Hall device 01, in addition, the current source 3 is connected with two pins of the Hall device 01 and used as an input end, and the universal meter 4 is connected with the other two pins of the Hall device 01 and used as an output end for testing Hall voltage. Therefore, two same electromagnets 2 are fixed on a support (not marked in the figure), the distance between the two electromagnets 2 is adjusted, the two electromagnets can be placed on the upper side and the lower side of a probe station 1, the magnetic field intensity is controlled through the current applied to the electromagnets 2, a controllable constant magnetic field is directly provided for the Hall device 01, the two pins corresponding to the Hall device 01 are connected to a current source 3 as input ends by utilizing the probe station 1, the other two pins are connected to a universal meter 4 as output ends, the Hall voltage is tested, the Hall device 01 with unqualified output can be calibrated by virtue of the probe station 1 during testing, the packaging cost is effectively reduced, and the testing period is shortened. In this embodiment of the present invention, the current source 3 can provide a current in the range of-105 mA-105mA, and the output current is relatively stable; the universal meter can test current, voltage and resistance, and the test precision can reach 10E-4 orders of magnitude.
As shown in fig. 1 and 2, the probe station 1 includes a probe station body 11, a microscope 12 is disposed on a top of the probe station body 11, a wafer stage 13 is disposed directly below the microscope 12, and a probe device 14 and a dotter device 15 are disposed on both sides of the wafer stage 13. The utility model discloses in this embodiment, probe device 14 uses four probes, connect four pins of hall device 01 simultaneously, thereby realize that two pins connect the input, two pins connect the designing requirement of output, thereby place hall device 01 on wafer stage 13, the calibration is to the probe position under microscope 12, make it align on the corresponding solder joint of hall device 01, ensure the highly uniform of needle point, it connects to check simultaneously that the test line makes, after the test, by dotting device 15 directly to unqualified sample mark, accomplish and select separately.
As shown in fig. 3, the probe apparatus 14 includes a probe frame 141 mounted on the probe station body 11, a probe 142 is disposed on one side of the probe frame 141 close to the wafer stage 13, and a fixing lock button 143, a front and rear adjusting button 144, a left and right adjusting button 145, and an up and down adjusting button 146 are distributed on the probe frame 141. The fixing lock button 143 fixes the probe holder 141 to position the probe holder 141, and the front and rear adjusting button 144, the left and right adjusting button 145, and the up and down adjusting button 146 are all used for fine adjustment, so that the probe holder 141 can be accurately positioned under the microscope 12, and the hall device 01 can be tested more accurately.
As shown in fig. 4, the dotter device 15 includes a dotter support 151 mounted on the probe station body 11, a dotting line 152 is disposed on one side of the dotter support 151 close to the support table 13, the dotting line 152 is connected with an ink cartridge 153, and a tightening screw 154, a limit nut 155 and a positioning nut 156 are distributed on the dotter support 151. The structure is matched with the probe device 14 to have a three-dimensional adjusting function, and can automatically and accurately mark unqualified samples.
As shown in fig. 1, the electromagnet 2, the current source 3, and the multimeter 4 are all connected to a control terminal 5, so that the magnetic field value of the electromagnet 2, the input current of the current source 3, and the test mode of the multimeter 4 can be remotely controlled, and the degree of automation can be further improved, specifically, the control terminal 5 includes at least one personal computer 51 and at least one programmable logic controller 52 that stores data by using a stack algorithm, a database is disposed in the programmable logic controller 52, the personal computer 51 has a visual operation interface, the personal computer 51 is in communication connection with the programmable logic controller 52, so that an operator can control and operate the programmable logic controller 52 through the personal computer 51, and at the same time, data synchronization between the personal computer 51 and the programmable logic controller 52 is realized, but in this embodiment, the database of the programmable logic controller 52 has a small amount of stored data, therefore, the stack algorithm is adopted to temporarily store data, the personal computer 51 adopts a hard disk for storage, the data storage amount is large, the programmable logic controller 52 receives new preset information and then synchronizes to the personal computer 51 for storage, so that data loss is prevented, meanwhile, the programmable logic controller realizes repeated coverage of data, namely, if new data comes, the latest data is covered and replaced with the old data, so that data iteration is realized.
As shown in fig. 1, in order to improve the stability of the system, in the present embodiment, the control terminal 5 performs mutual inspection of the working states with the electromagnet 2, the current source 3, and the multimeter 4 through interaction of handshake signals, and when the control terminal 5 is started each time, a signal is provided to the electromagnet 2, the current source 3, and the multimeter 4, and then a signal is fed back to the control terminal 5, where the feedback signal includes ID information of each electromagnet 2, current source 3, and multimeter 4, and the control terminal 5 compares the feedback signal with corresponding ID information in the database to determine, and when there is a problem with the electromagnet 2, current source 3, and multimeter 4, or when a certain symptom needs to be processed but does not temporarily affect normal operation, and when a change of a sensor is within an error range, indication information of rejecting use, warning, or enabling normally is made.
As shown in fig. 1, in order to prevent information loss, in the present embodiment, the personal computer 51 and the programmable logic controller 52 perform mutual check of the operating state by interaction of heartbeat signals. That is, when it is set that the programmable logic controller 52 and the personal computer 51 cannot receive the signals of the other party within the preset time, it is determined that the personal computer 51 or the programmable logic controller 52 is down, when one of the personal computer 51 or the programmable logic controller 52 is down, the system stops operating, the personal computer 51 or the programmable logic controller 52 in the down state is waited to restart, or the system continues operating, but data is directly stored in the personal computer 51 or the programmable logic controller 52 which normally operates, and after the down party is restarted, the data is transmitted to the down party. Wherein the preset time for judging whether the personal computer 51 or the programmable logic controller 52 is normal is not more than 1 minute.
The working principle of the chip-level Hall device testing and sorting device is as follows: selecting the required probe device 14 (four probes 142) according to the unit graph condition of the Hall device 01 to be tested, then installing the probe frame 141 on the probe station main body 11, locking and fixing the probe frame through the fixing lock button 143, the front and back adjusting button 144, the left and right adjusting button 145 and the up and down adjusting button 146, then placing the Hall device 01 on the bearing table 13, calibrating the position of the probes 142 under the microscope 12, then sequentially connecting the four probe 142 tips of the probe station 1 to the four welding points of the Hall device 01, ensuring the consistent height of the tips, simultaneously checking the test connecting line to connect the probes, and in addition, installing the dotter bracket 151 on the probe station main body 11 through the jacking screw 154, the limiting nut 155 and the positioning nut 156, and aligning the probes in the same chip unit graph.
During testing, connecting a lead wire of a probe 142 connected with a welding spot of the Hall device 01 to a current source 3, connecting the lead wire of the probe 142 connected with the welding spot of the Hall device 01 to a universal meter 4, electrifying an electromagnet 2, adjusting the magnitude of input current through a control end 5, changing the magnetic field value, calibrating the magnetic field value by using a gauss meter, adjusting the current level of the current source 3 to a current level, and setting the input current of 10 mA; the universal meter 4 is adjusted to a voltage test mode, the reading is observed, whether the device is qualified or not is judged, if the device is qualified, the next unit test is automatically carried out, if the device is unqualified, the dotting device 15 is automatically dotted on the chip unit, and then the next unit test is automatically carried out.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications can be made without departing from the scope of the invention.
Claims (7)
1. A chip-level Hall device testing and sorting device is characterized by comprising:
the probe station (1) is used for connecting four pins of the Hall device (01) and calibrating the Hall device (01) with unqualified output;
the electromagnet (2) is arranged on the probe station (1) and used for providing a constant magnetic field for the Hall device (01);
the current source (3) is connected with two pins of the Hall device (01) and is used as an input end;
and the universal meter (4) is connected with the other two pins of the Hall device (01) and is used as an output end to test the Hall voltage.
2. The chip-scale hall device testing and sorting apparatus according to claim 1, wherein the probe station (1) comprises a probe station main body (11), a microscope (12) is arranged on the top of the probe station main body (11), a wafer bearing table (13) is arranged right below the microscope (12), and a probe device (14) and a dotter device (15) are arranged on two sides of the wafer bearing table (13).
3. The chip-scale hall device testing and sorting apparatus according to claim 2, wherein the probe apparatus (14) comprises a probe frame (141) installed on the probe table main body (11), a probe (142) is arranged on one side of the probe frame (141) close to the wafer supporting table (13), and a fixed lock button (143), a front and rear adjusting button (144), a left and right adjusting button (145) and an up and down adjusting button (146) are distributed on the probe frame (141).
4. The chip-scale Hall device testing and sorting apparatus according to claim 3, wherein the dotter apparatus (15) comprises a dotter support (151) installed on the probe station main body (11), a dotting line (152) is arranged on one side of the dotter support (151) close to the wafer bearing table (13), the dotting line (152) is connected with an ink cartridge (153), and a tightening screw (154), a limit nut (155) and a positioning nut (156) are distributed on the dotter support (151).
5. The chip-level Hall device testing and sorting device according to claim 1, wherein the electromagnet (2), the current source (3) and the multimeter (4) are all connected with a control terminal (5), the control terminal (5) comprises at least one personal computer (51) and at least one programmable logic controller (52) which stores data by using a stack algorithm, and the personal computer (51) is in communication connection with the programmable logic controller (52) for realizing data synchronization.
6. The chip-scale hall device testing and sorting apparatus of claim 5, wherein the personal computer (51) and the programmable logic controller (52) perform mutual checking of the working state through the interaction of heartbeat signals.
7. The chip-scale Hall device testing and sorting apparatus according to claim 5, wherein said control terminal (5) and said electromagnet (2), current source (3), multimeter (4) perform mutual inspection of working status through interaction of handshaking signals.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201920989131.5U CN210230705U (en) | 2019-06-27 | 2019-06-27 | Chip-level Hall device testing and sorting device |
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| CN201920989131.5U CN210230705U (en) | 2019-06-27 | 2019-06-27 | Chip-level Hall device testing and sorting device |
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| CN210230705U true CN210230705U (en) | 2020-04-03 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116087571A (en) * | 2023-04-03 | 2023-05-09 | 有研国晶辉新材料有限公司 | Miniature probe station for testing high-purity germanium monocrystal Hall and testing method |
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2019
- 2019-06-27 CN CN201920989131.5U patent/CN210230705U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116087571A (en) * | 2023-04-03 | 2023-05-09 | 有研国晶辉新材料有限公司 | Miniature probe station for testing high-purity germanium monocrystal Hall and testing method |
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