CN113141226A - Global clock synchronization method combining data packets and short pulses - Google Patents
Global clock synchronization method combining data packets and short pulses Download PDFInfo
- Publication number
- CN113141226A CN113141226A CN202010067805.3A CN202010067805A CN113141226A CN 113141226 A CN113141226 A CN 113141226A CN 202010067805 A CN202010067805 A CN 202010067805A CN 113141226 A CN113141226 A CN 113141226A
- Authority
- CN
- China
- Prior art keywords
- clock
- slave device
- master device
- clock count
- master
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
Abstract
The invention provides a hardware global clock synchronization algorithm combining short pulses and data packets capable of reducing data transmission quantity, which mainly comprises that a master device sends a short pulse to a slave device every time a first time interval (for example, 1mS) passes, so that the slave device adjusts the clock counting value of the slave device according to the first time interval, the master device sends a clock counting data packet to the slave device every time a second time interval (for example, 10mS) passes, so that the slave device loads the clock counting value of the master device from the clock counting value of the slave device, and the global clock synchronization is completed. In addition, the invention can automatically recover the clock count value when the main equipment or the auxiliary equipment generates electrostatic shock or other abnormal conditions. After the invention is implemented, because it is not necessary to send clock count data packet every time, the data transmission amount between the global clock synchronization master device and the slave device can be reduced, and further the communication power consumption required by the clock synchronization of the digital hardware system can be reduced.
Description
Technical Field
The present invention relates to global clock synchronization (global clock synchronization) technology, and more particularly, to a method for combining a Data Packet and a burst transmitted by a master device, so that the master device reduces the number of times of transmitting the clock count Packet to a subsystem requiring synchronization, thereby reducing the Data transmission amount.
Background
The global clock ensures the synchronization of the cooperative work between the hardware devices (chip modules or circuit boards) in the system. When multiple hardware devices work together, data communication between the devices needs to complete synchronization of global beats by sending and receiving data packets. In order to facilitate synchronization of different types of data packets and to distinguish the sequence of the same type of data packets, the data packet sending device usually stamps the data packets with a time stamp (Timestamp), so that each data packet sending device needs to have a separate counter (Timer). When a plurality of devices work cooperatively, each device generally needs to send and receive a data packet at the same time, and each device uses its own dedicated counter, so that the timestamp of the data packet sent by each device and the timestamp of the received data packet have no correlation, and meanwhile, the timestamp of the data packet sent by different sending ends received by each device has no correlation, which easily causes the chaos of sending and receiving the data packet.
Therefore, in practical applications, counters of the cooperative devices are usually synchronized by a clock synchronization algorithm, so that the master device issues a data packet (which includes clock count data generated by the counter of the master device counting) at intervals, the slave device acquires the clock count data in the data packet, and adjusts the clock count of the slave device by the algorithm, so that the clock count values of the count clocks of the devices are approximately the same at the same time, or the error of the clock count values is within an acceptable range.
In this regard, the timing of the clock count value of the master device being transmitted to the slave device may be completely controlled by the master device, so that the time intervals of the 2 clock count packets transmitted from the master device to the slave device may be completely the same, so that after the slave device receives the clock count packet transmitted from the master device for the 1 st time, the clock of the slave device may be initialized and counted using the data in the packet, and then, after the slave device receives the clock count packet transmitted from the master device for the 2 nd time, the slave device may obtain the clock count value of the master device by adding the clock count value received for the 1 st time to the time interval of the 2 packet transmissions, thereby reducing the data communication power consumption by reducing the number of data transmissions, as long as the interval of the 2 clock count packets transmitted by the master device is a fixed time known to both the master device and the slave device, then the slave device may not have to track the clock count value in the packet, starting with counting the packet at the 2 nd clock, but rather just count the exact time of transmission of the packet with the clock in mind.
Therefore, the inventor proposes that the clock counting data packet can be replaced by a short pulse which can accurately indicate the clock counting time sent by the master device from the 2 nd clock counting data packet, as shown in fig. 1, after the slave device receives the nth clock counting data packet D1' sent by the master device at 21000 μ S (microseconds), the clock counting data packets of the following master device can be completely replaced by the short pulse, and the clock counting values in the data packets can be calculated by the slave device.
With continued reference to fig. 2, if the master clock count is 22000 μ S and a short pulse P 'is sent to the slave device, and if the slave device receives an Electrostatic shock (ESD, also called Electrostatic Discharge), all register values will be cleared or confused, and no short pulse P' sent by the master device is received, and then if the master clock count is 23000 μ S, the slave device will receive the short pulse sent by the master device, but because the last Electrostatic shock has lost the master clock count (21000 μ S), the slave device will calculate the master clock count (0+1000 μ S) in error at this time, and because the master device will only send the short pulse later and no complete clock count data packet has been sent, when the slave device receives the subsequent short pulse, it is also only necessary to calculate the clock count continuously, for example, when the master clock count is 24000 μ S, the slave device calculates the master clock count of 1000+1000 to 2000 μ S, and there is no chance to correct the error.
In other words, the foregoing method will synchronize the slave device to the wrong master device clock, which may not reduce the error between the master device and the slave device, and therefore, in order to achieve global clock synchronization, a "global clock synchronization method combining packets and short pulses" is proposed, which can reduce the data transmission amount generated in the clock synchronization algorithm, thereby reducing the power consumption of data communication, and can automatically recover the clock count value when electrostatic shock occurs, and the problem to be solved by the present invention is solved.
Disclosure of Invention
In order to achieve the above object, the present invention provides a global clock synchronization method combining data packets and short pulses, which mainly comprises the following steps:
(1) after a master device completes initialization, a counter of the master device carries out counting operation based on a clock counting period, and the master device sends a clock counting data packet containing a clock counting value of the master device to at least one slave device;
(2) after receiving a clock counting data packet sent by the master device, the slave device initializes a slave device clock counting value of the slave device based on the clock counting data packet and starts counting operation;
(3) the master device sends a short pulse to the slave device every time a first time interval passes, so that the slave device updates the clock count value of the slave device according to the first time interval after receiving the short pulse;
(4) the master device sends the clock counting data packet to the slave device every time a second time interval passes, so that the slave device synchronizes the clock counting value of the master device with the clock counting value of the slave device according to the clock counting data packet of the master device, wherein the second time interval is greater than the first time interval; and
(5) when the slave device is restarted due to electrostatic shock or other abnormality, the clock count value temporarily stored by the slave device is reset to zero, and further the slave device receives a short pulse sent every time when the master device passes a first time interval every time, and continuously calculates an error clock count value, and when the master device sends a clock count data packet every time when the master device passes a second time interval, the slave device sets the clock count value temporarily stored by the counter as the clock count value of the master device according to the received clock count data packet, so that the aim of automatically recovering the clock count value of the synchronous slave device and the clock count value of the master device is fulfilled.
(6) And (3) when the clock count of the master device is cleared due to the occurrence of an abnormality such as electrostatic shock in the master device, initializing the master device, and then executing the steps (1) to (4) again by the master device and the slave device.
Therefore, after the implementation of the present invention, compared with the aforementioned hardware global clock synchronization method, the present invention can achieve the effect of reducing the number of times of clock counting data packets sent to each slave device (subsystem) to be synchronized by the master device, thereby reducing the amount of data to be sent in the global clock synchronization method and saving the power consumption of data communication.
In order to make the examination and review board clear the objects, technical features and effects of the invention, please refer to the following description together with the drawings.
Drawings
Fig. 1 is a schematic diagram of a conventional global clock synchronization algorithm in which a packet is replaced with a short pulse.
Fig. 2 is a schematic diagram of an exception occurring after a packet is replaced with a short pulse in the global clock synchronization algorithm.
Fig. 3 is a system architecture diagram of the present invention.
FIG. 4 is a flow chart of the present invention.
FIG. 5 is a schematic diagram of the present invention.
Fig. 6 is a schematic diagram (two) illustrating an embodiment of the present invention.
Fig. 7 is another embodiment of the present invention.
Detailed Description
Referring to fig. 3, which is a system architecture diagram of the present invention, the present invention provides a global clock synchronization method for combining packets and short pulses, which is mainly implemented by a digital hardware system 10, and is implemented based on hardware (i.e. synchronization is accomplished by a counter between a plurality of chips connected by a PCB circuit board or a dedicated data line, and the synchronization error is generally small), rather than software (i.e. synchronization is performed by a network on clock count values between a plurality of servers or computers connected by the network, and the synchronization error is generally large), the digital hardware system 10 mainly comprises a master device 101 and at least one slave device (102, 102', 102 "), the master device 101 and each slave device (102, 102', 102 ") have a counter T, which is used for executing counting tasks and comparing counting data.
As mentioned above, the master device 101 and the slave devices (102, 102', 102 ") may be chips on the same circuit board, or different circuit boards with chips mounted thereon connected by data lines. The master device 101 and the slave devices (102, 102 ', 102 ") can be connected through a data line, the data line can be a differential line or a single-end line, when the master device 101 sends a clock counting data packet of the master device to all the slave devices (102, 102 ', 102") through the data line timing, each slave device (102, 102 ', 102 ") can further trigger the counter T to count after receiving the clock counting data packet of the master device 101.
Accordingly, the slave device (102, 102 ', 102 ") may adjust the slave device in comparison with the data of the master device clock count data packet, so that the error between the clock count data of the slave device (102, 102 ', 102") and the clock count data of the master device 101 is within a very small error range, and thus, the counter T of the slave device (102, 102 ', 102 ") may lock the counter T of the master device 101, and the slave device (102, 102 ', 102") may transmit the lock signal through the data line transmitting the clock count data packet, may also establish a dedicated lock data line to transmit to the master device, or the slave device (102, 102 ', 102 ") may not transmit the lock information to the master device 101, so as to simplify the global clock synchronization procedure.
In the process of the aforementioned global clock synchronization transmission, the master device 101 may periodically transmit the complete clock count value to the slave devices (102, 102 ', 102 ") in the form of a data packet through the data line, where the data line may only be a dedicated data line dedicated to global clock synchronization, but not a general data line for inter-device communication, and if the dedicated data line dedicated to global clock synchronization is adopted, the time for the master device 101 to accurately transmit the clock count value due to the transmission of other data may not be affected when other data is transmitted between the master device 101 and the slave devices (102, 102', 102").
With continuing reference to fig. 4 and with further reference to fig. 3 and 5, the global clock synchronization method S for combining packets and short pulses according to the present invention, when implemented in the digital hardware system 10, can perform the following steps:
(1) the master device transmits an nth clock count packet (step S10): after a master device 101 completes initialization, a counter T of the master device 101 performs counting operation based on one clock count cycle, and the master device transmits a clock count packet D1 (shown as an nth master clock count packet) including a master clock count value to at least one slave device (102, 102', 102 ").
(2) The slave device starts counting clocks after receiving the clock count packet (step S20): in step S10, when the slave device (102, 102 ', 102 ") receives the clock count packet D1 transmitted from the master device 101, one of the slave devices (102, 102', 102") initializes its clock count value based on the master clock count value in the clock count packet D1, and starts a count job with its counter T.
(3) The master transmits a short pulse over a first time interval (step S30): following step S20, the master device 101 sends a short pulse P to the slave device (102, 102 ', 102 ") every time a first time interval I1 (e.g., 1000 μ S as shown in fig. 5, i.e., 1mS (milliseconds), but not limited thereto) elapses, so that the slave device (102, 102', 102") updates the slave clock count value according to the first time interval I1 after receiving the short pulse P.
(4) The master device transmits a clock count packet through the second time interval (step S40): following step S30, the master device 101 may send another clock count packet D2 (e.g., the N +1 st master clock count packet shown in fig. 5) to the slave device (102, 102 ', 102 ") every time a second time interval I2 (e.g., 10000 μ S, i.e., 10mS, as shown in fig. 5, but not limited to this value) elapses, so that the slave device (102, 102', 102") synchronizes the master clock count value and the slave clock count value according to the master clock count value of the clock count packet D2, wherein the second time interval is greater than the first time interval.
(5) In step S30 or step S40, when the slave device (102, 102 ', 102 ") is restarted due to an electrostatic shock or other abnormality, the clock count value temporarily stored in the slave device (102, 102', 102") is reset to zero, and further, when step S30 (the master device sends a short pulse over the first time interval) is executed, the slave device (102, 102 ', 102 ") is continuously allowed to calculate an erroneous clock count value (such as the slave device clock count value 6000 μ S shown in fig. 6), and when step S40 is executed again, the slave device clock count value of the slave device (102, 102', 102") and the master device clock count value are synchronized.
Continuing with FIG. 6, more specifically, assuming that the master 101 sends a short pulse P to the slaves (102, 102') in step S30 when the master clock counts 23000 μ S, if, however, the slave device (102, 102 ', 102 ") is subjected to an electrostatic shock at this time, all register data of the slave device (102, 102', 102") is zeroed, at this time, the slave devices (102, 102') do not receive the short pulse P sent by the master device 101 because of the electrostatic shock, the counter T of the slave device (102, 102', 102 ") will restart counting by the slave device clock counting 0 mus, thereafter until the master clock count of the master 101 is 29000 μ S, the slave (102, 102', 102 ") calculates the slave clock count of 0+6000 ═ 6000 μ S at this time, resulting in an excessively large error between the slave clock count and the correct master clock count (29000 μ S).
When the present invention is executed again in step S40, for example, when the master device 101 is 30000 μ S, the slave device (102, 102 ', 102 ") may load the master device clock count value (30000 μ S) of the clock count data packet D2 (e.g., the N +1 st master device clock count data packet shown in fig. 6) sent by the master device 101 and received in step S40, and set the slave device clock count value of the counter T of the slave device (102, 102', 102") to be 30000 μ S, so that the clock count value (6000 μ S) calculated in the past may be corrected, thereby ensuring that the slave device (102, 102 ', 102 ") may frequently adjust its own clock count, and reducing the clock count error between the slave device (102, 102', 102") and the master device 101.
As mentioned above, when the first time interval I1 overlaps the second time interval T2, the master device 101 only needs to execute step S40, so that the master clock count value and the slave clock count value are synchronized at this step.
In this regard, when step S30 is executed, the time at which the master device 101 transmits the clock count value may be the rising edge (also referred to as the rising edge) or the falling edge (also referred to as the falling edge) of the short pulse P
Referring to fig. 7, which is another embodiment of the present invention and referring to fig. 3, when the present invention is executed in step S30, the present embodiment is substantially the same as the techniques of fig. 4 to fig. 6, and the main difference is that, when the master device 101 is restarted due to electrostatic shock or other abnormality in step S20, step S30 or step S40, the master device 101 may first re-execute step S10, perform initialization, and re-send the clock count data packet D _ NEW to the slave devices (102, 102 ', 102 ") based on the NEW clock count value of the master device, so as to continue step S20, so that the slave devices (102, 102', 102") can discard the clock count value of the master device previously received from the master device 101 after receiving the NEW clock count data packet D _ NEW, and introduce the NEW clock count of the master device, perform initialization and re-count operations, to begin a new global clock synchronization.
In summary, the present invention can replace the conventional well-known global clock synchronization method for sending the clock count data packet of the master device in specific applications, and can automatically recover and report the occurrence of the abnormal event as early as possible for various abnormal events such as static electricity shock encountered by the master device and the slave device.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all equivalent changes and modifications that can be made by one skilled in the art without departing from the spirit and scope of the present invention should be covered by the appended claims.
[ notation ] to show
10 digital hardware system
101 master 102 slave
102 'Slave 102' Slave
T counter D1' clock count data packet
P' short pulse D1-D2 clock counting data packet
D _ NEW clock count packet
P short pulse I1 first time interval
I2 second time interval
Global clock synchronization method for S-combined data packet and short pulse
S10 the master device sends a first clock count packet
S20 starting counting clock after receiving clock counting data packet from device
S30 the master device transmits a short pulse over a first time interval
S40 the master device sends a clock count packet over a second time interval.
Claims (7)
1. A method for global clock synchronization in conjunction with packets and short bursts, comprising:
(A) after a master device completes initialization, a counter of the master device performs counting operation based on a clock counting period, and the master device sends a clock counting data packet containing a clock counting value of the master device to at least one slave device;
(B) after the slave device receives the clock counting data packet sent by the master device, initializing a slave device clock counting value of the slave device based on the clock counting data packet, and starting counting operation;
(C) the master device sends a short pulse to the slave device every time a first time interval passes, so that the slave device updates the clock count value of the slave device according to the first time interval after receiving the short pulse;
(D) the master device sends the clock counting data packet to the slave device every time a second time interval passes, so that the slave device synchronizes the clock counting value of the master device with the clock counting value of the slave device according to the clock counting value of the master device of the clock counting data packet, wherein the second time interval is greater than the first time interval; and
(E) when the slave device is restarted due to electrostatic shock or other abnormality, the clock count value temporarily stored by the slave device is reset to zero, and further the slave device continuously calculates an error clock count value when the master device is executed after a first time interval short pulse sending step, and then the clock count value of the slave device and the clock count value of the master device are synchronized when the master device is executed again after a second time interval clock count data packet sending step.
2. The method of global clock synchronization combining packets and short pulses as claimed in claim 1, wherein the slave device sends a lock signal to the master device when the clock count value of the slave device is within an error tolerance from the clock count value of the master device.
3. The method for global clock synchronization with combined packets and short pulses as claimed in claim 1, wherein when the master device is restarted due to electrostatic shock or other abnormality, the master device performs step (a) to initialize and resends the clock count packet to the slave device based on the new clock count value of the master device to continue step (B).
4. The method for global clock synchronization of combined packets and short pulses as claimed in claim 1 or 3, wherein when said slave device receives a new said clock count packet, said slave device discards said slave device clock count value calculated in the past, and then said slave device initializes according to said new master device clock count value to resume counting operation.
5. The method of claim 1, wherein the master device only performs step (D) when the first time interval overlaps the second time interval, and the master device clock count value and the slave device clock count value are synchronized in step (D).
6. The method of claim 1, wherein the clock count packet or the short pulse is sent to the slave device via a pair of differential lines or a single-ended data line.
7. The method for global clock synchronization of a combination of data packets and short pulses of claim 1, wherein step (C) is performed such that the master device transmits a rising edge or a falling edge of the short pulse.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010067805.3A CN113141226A (en) | 2020-01-20 | 2020-01-20 | Global clock synchronization method combining data packets and short pulses |
| PCT/CN2020/131024 WO2021147502A1 (en) | 2020-01-20 | 2020-11-24 | Method for global time synchronization by combining data packet and short pulse |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010067805.3A CN113141226A (en) | 2020-01-20 | 2020-01-20 | Global clock synchronization method combining data packets and short pulses |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113141226A true CN113141226A (en) | 2021-07-20 |
Family
ID=76809201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010067805.3A Pending CN113141226A (en) | 2020-01-20 | 2020-01-20 | Global clock synchronization method combining data packets and short pulses |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN113141226A (en) |
| WO (1) | WO2021147502A1 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101202921A (en) * | 2006-12-11 | 2008-06-18 | 中兴通讯股份有限公司 | Clock synchronous system of moving multimedia network |
| US20090088821A1 (en) * | 2005-05-04 | 2009-04-02 | Hans Abrahamson | Synchronization of implantable medical devices |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI415497B (en) * | 2010-08-27 | 2013-11-11 | Univ Nat Taiwan | Device, system, and method for time synchronization |
| CN102882669A (en) * | 2012-08-23 | 2013-01-16 | 上海柏飞电子科技有限公司 | Two-wire interface time synchronization protocol method |
| US10498474B2 (en) * | 2016-01-04 | 2019-12-03 | Qatar Foundation For Education, Science And Community Development | Cross-layer time synchronization method |
| CN109286459B (en) * | 2017-07-21 | 2020-09-15 | 北京智云芯科技有限公司 | Time synchronization method and system |
| CN109687927B (en) * | 2017-10-19 | 2020-07-07 | 深圳市中兴微电子技术有限公司 | Method for determining timestamp, communication equipment and communication system |
| CN110120846B (en) * | 2018-02-05 | 2020-11-13 | 大唐移动通信设备有限公司 | Clock synchronization method and system |
-
2020
- 2020-01-20 CN CN202010067805.3A patent/CN113141226A/en active Pending
- 2020-11-24 WO PCT/CN2020/131024 patent/WO2021147502A1/en active Application Filing
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090088821A1 (en) * | 2005-05-04 | 2009-04-02 | Hans Abrahamson | Synchronization of implantable medical devices |
| CN101202921A (en) * | 2006-12-11 | 2008-06-18 | 中兴通讯股份有限公司 | Clock synchronous system of moving multimedia network |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2021147502A1 (en) | 2021-07-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP1525693B1 (en) | Clock synchronizing method over fault-tolerant etherent | |
| EP2976866B1 (en) | Timestamp correction in a multi-lane communication link with skew | |
| CN101296066B (en) | Real time clock synchronization method of distributed system, master control board and cable fastener plate | |
| US20060222125A1 (en) | Systems and methods for maintaining synchronicity during signal transmission | |
| US10169171B2 (en) | Method and apparatus for enabling temporal alignment of debug information | |
| US20080298398A1 (en) | Transparent Spider | |
| CN111181555B (en) | PTP clock synchronization system and clock synchronization method | |
| CN103516423B (en) | A kind of method and apparatus zoomed out for fiber bit clock | |
| US20210004043A1 (en) | Multichip Timing Synchronization Circuits and Methods | |
| CN109361485B (en) | Method for calibrating PTP (precision time protocol) master clock in non-real-time system | |
| CN107636627B (en) | Time synchronization device, time synchronization system, and time synchronization method | |
| JP2020195056A (en) | Time synchronization program, information processing device and time synchronization method | |
| CN113141226A (en) | Global clock synchronization method combining data packets and short pulses | |
| TWI712299B (en) | Global clock synchronization method combining packet and short pulse | |
| US6502197B1 (en) | Method and architecture for synchronizing a transport and path overhead generator and/or extractor to an path overhead transport and path processor | |
| US11258633B2 (en) | Timestamp unit and communication control unit for a user station of a communication network | |
| US11294421B2 (en) | Precision timing between systems | |
| CN117009267B (en) | Method for inserting time information in source synchronous data stream | |
| WO2023073970A1 (en) | Time synchronization device, time synchronization method, and program | |
| CN117908630A (en) | High-precision time service system and method based on PCIE board card | |
| CN114301566A (en) | Clock synchronization method of redundancy system, redundancy system and network system | |
| CN103500320B (en) | Based on the radio frequency anticollision synchronous method of Internet of Things electric power temperature measuring equipment | |
| TW202415046A (en) | Synchronizing method and electronic system | |
| JPH05111083A (en) | Inter-device synchronism settling system | |
| JPS60180244A (en) | Cyclic data transmission system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20210720 |