CN109361485B - Method for calibrating PTP (precision time protocol) master clock in non-real-time system - Google Patents
Method for calibrating PTP (precision time protocol) master clock in non-real-time system Download PDFInfo
- Publication number
- CN109361485B CN109361485B CN201811571615.4A CN201811571615A CN109361485B CN 109361485 B CN109361485 B CN 109361485B CN 201811571615 A CN201811571615 A CN 201811571615A CN 109361485 B CN109361485 B CN 109361485B
- Authority
- CN
- China
- Prior art keywords
- time
- ptp
- real
- pulse
- adjustment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0644—External master-clock
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Electric Clocks (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The embodiment of the invention discloses a method for calibrating a PTP (precision time protocol) master clock in a non-real-time system, and relates to the technical field of clock synchronization. The calibration method comprises the steps of configuring a PTP chip in a non-real-time system and calibrating the accuracy of the time of the PTP chip; setting a timer thread for detecting system clock change and second pulse jump in a non-real-time system; the non-real time system checks the satellite messages and the pulse-per-second signals and adjusts the PHY hardware time and the system time when the satellite messages and the pulse-per-second signals are valid. The method for calibrating the PTP master clock in the non-real-time system has high real-time performance, the non-real-time operating system can be used for calibrating the precision of the PTP master clock very conveniently, the calibration precision reaches a sub-microsecond level, and the requirements of most PTP time systems are met.
Description
Technical Field
The embodiment of the invention relates to the technical field of clock synchronization, in particular to a method for calibrating a PTP (precision time protocol) master clock in a non-real-time system.
Background
PTP (Precision Time Protocol) is a Time synchronization Protocol, and can be used for high-Precision Time synchronization between devices and can also be borrowed for frequency synchronization between devices. Compared with the NTP (network time Protocol), the PTP can meet the requirement of time synchronization with higher precision, the NTP generally can only achieve the time synchronization precision of a sub-second level, the PTP can achieve the sub-second level, and the real-time performance is very high.
In some non-real-time operating systems, for example, Linux operating system, Linux itself has powerful network functions and has an open source PTP protocol stack, but standard Linux does not provide strong real-time performance. Based on the method, the invention provides a method for calibrating the PTP master clock in the non-real-time system, which is used for conveniently calibrating the precision of the PTP master clock and meets the requirements of most PTP time systems.
Disclosure of Invention
The embodiment of the invention provides a method for calibrating a PTP (precision time protocol) master clock in a non-real-time system, which is used for calibrating the precision of the PTP master clock, wherein the calibration precision reaches a sub-microsecond level, and the precision requirement of most PTP time systems is met.
In order to solve the technical problem, the embodiment of the invention discloses the following technical scheme:
a method of calibrating a PTP master clock in a non-real time system, the method comprising the steps of:
configuring a PTP chip in a non-real-time system, and calibrating the accuracy of the time of the PTP chip;
setting a timer thread for detecting system clock change and second pulse jump in a non-real-time system;
the non-real-time system checks the satellite message and the pulse per second signal, and when the satellite message and the pulse per second signal are effective, PHY hardware time is adjusted by taking satellite time as a reference, and then system time is adjusted according to the PHY hardware time.
Based on the scheme, the method is optimized as follows:
further, the configuring of the PTP chip and the calibrating of the accuracy of the time of the PTP chip include the following steps:
connecting the PTP chip with a processor operating a non-real-time system;
adjusting a PTP trigger configuration register PTP _ TRIG, and configuring the GPIO2 to output a trigger signal generated by the PHY;
and adjusting a PTP time register PTP _ TDR, configuring the trigger signal into pulse width output, and triggering at a rising edge.
Further, the setting of a timer thread for detecting system clock change and second pulse jump in a non-real-time system includes the following steps:
connecting the GPS/Beidou receiving module and the CPLD processing module with a processor operating a non-real-time system;
setting a timer thread for detecting system clock change and second pulse jump in a non-real-time system, if the second pulse jump occurs, sending a heartbeat checking command to a watchdog program module by the system, and executing heartbeat checking by the watchdog program module;
the system checks the second pulse valid bit in the message transmission of the GPS/Beidou receiving module, and judges whether to adjust the system time and the PHY hardware time according to the valid bit.
Further, the non-real-time system adjusts PHY hardware time and system time, and includes the following steps:
the pulse per second generated by the PHY hardware clock and the pulse per second of the GPS/Beidou receiving module are accessed to the CPLD processing module;
the CPLD processing module counts the time difference between the mainboard second pulse and the PHY second pulse;
and after the CPLD finishes counting, interruption is generated, the output circuit outputs the counted data to a processor of a non-real-time system through a bus, the non-real-time system takes the counted data away, and the PHY hardware time is adjusted according to the taken data.
The CPLD processing module inputs 50MHZ frequency to count the time difference of the occurrence of the mainboard second pulse and the PHY second pulse, and two 16-bit counters are used for counting.
Preferably, the non-real-time system adjusting the PHY hardware time is mainly realized by three ways, namely, single step time adjustment, fixed rate adjustment, and temporary rate adjustment, and the specific implementation includes the following steps:
updating the counted pulse deviation count value in real time within the first N times of effective interruption;
at the N +1 th time of the effective interruption, a coarse adjustment is made to the time and the fixed rate, and the adjusted time is calculated by the following formula (1)
Wherein PPSCount is the pulse offset count value, and RATEDIVAL is the PHY output clock effective frequency division value;
the adjusted fixed rate is calculated by the following equation (2)
Wherein, PrePPSCount is the counting value of the last second pulse;
next, when the pulse deviation count value PPSCount comes, the filtering is performed for removing the pole, the time is adjusted in a single step after the filtering is completed, and the adjustment parameter of the fixed rate is calculated by the following formula (3)
Rate＝PreRate+34.3597×PPSCount (3)
And the PreRate is a last calculation adjustment value, the value of each adjustment is stepped on the basis of the last adjustment value, and an average filtering algorithm is adopted, and the adjustment is performed every M times.
Preferably, in the step of adjusting the PHY hardware time, a value of N is 15, and a value of M is 10.
Further, a method for calibrating a PTP master clock in a non-real time system as described above, wherein the processor running the non-real time system is an ARM processor, and the PTP chip is a DP83640 chip.
The technical scheme provided by the application comprises the following beneficial effects:
the method for calibrating the PTP master clock in the non-real-time system comprises the steps of configuring a PTP chip and calibrating the accuracy of the time of the PTP chip; setting a timer thread for detecting system clock change and second pulse jump in a non-real-time system; the non-real time system checks the satellite messages and the pulse-per-second signals and adjusts the PHY hardware time and the system time when the satellite messages and the pulse-per-second signals are valid. The method for calibrating the PTP master clock in the non-real-time system simplifies the processing difficulty of peripheral signals, is high in real-time performance, can be used for calibrating the precision of the PTP master clock very conveniently by the non-real-time operating system, achieves the precision of submicrosecond, meets the requirements of most PTP time systems, and is a new, quick and effective method for correcting the local clock.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.
Fig. 1 is a schematic flowchart of a method for calibrating a PTP master clock in a non-real-time system according to an embodiment of the present application;
FIG. 2 is a diagram illustrating a hardware connection of a method for calibrating a PTP master clock in a non-real-time system according to an embodiment of the present invention;
FIG. 3 is a flow chart of a configuration process of the PTP chip of FIG. 1;
FIG. 4 is a flowchart illustrating operation of the timer thread of FIG. 1;
fig. 5 is a circuit diagram of a frequency counting circuit of the CPLD processing module.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 and fig. 2 are a flowchart and a hardware connection diagram of a method for calibrating a PTP master clock in a non-real-time system according to an embodiment of the present application. In the embodiment, a Linux operating system is adopted in software, the Linux operating system is set, and a PTP protocol stack is operated; an ARM processor capable of running a Linux system, a CPLD processor, a GPS/Beidou receiving module and a PTP chip are adopted in hardware, and the DP83640 chip is adopted in the PTP chip.
As shown in fig. 1, a method for calibrating a PTP master clock in a non-real-time system according to this embodiment includes the following steps:
s1, configuring a PTP chip, and calibrating the accuracy of the PTP chip time;
s2, setting a timer thread for detecting system clock change and second pulse jump in the Linux system;
s3, the Linux system checks the satellite message and the pulse signal, and adjusts the PHY hardware time and the system time when the satellite message and the pulse signal are effective.
Specifically, in step S1, the configuration process of the PTP chip includes:
connecting the PTP chip with a processor running a Linux system;
adjusting a PTP TRIGGER configuration register PTP _ TRIG, and configuring the GPIO2 to output a TRIGGER signal generated by the PHY;
and adjusting a PTP time register PTP _ TDR, configuring the TRIGGER signal into pulse width output, and triggering a rising edge.
Further, in the above step S1, the specific configuration process of the PTP chip is as shown in fig. 3: firstly, whether a DP83640 chip exists is detected, and the function of the chip exits when the chip function cannot be detected; clearing a PTP EVENT register PTP _ EVENT and a trigger configuration register PTP _ TRIG to prepare for configuring the two registers; enabling DP83640 chip 10M network support; then initializing a clock source output configuration register PTP _ COC and a clock source register PTP _ CLKRC, configuring a PTP _ CLKOUT EN bit to output a CLK signal in the output clock signal initialization process, setting a frequency division value to be 4, and configuring a PTP clock source to select an internal PGM by default; setting a PTP _ ENABLE bit of the control register to ENABLE a PTP clock; initializing a PTP TRIGGER configuration register PTP _ TRIG, configuring GPIO2 to output a pulse per second generated by a PHY, configuring a TRIGGER signal as an output signal of a DP83640, configuring the output signal to be pulse width output, wherein the period is 1s, the rising edge is triggered, the duty ratio is 10%, setting the sequence that firstly, a TRIGGER function is selected through the PTP control register, the TRIG _ LOAD starts a PTP loading process, and then the rising edge TRIGGER time of the pulse per second of the TRIGGER signal is written (the rising edge time of the TRIGGER signal takes the local 1588 hardware clock quasi-second time of the DP83640 as the reference, and is set as the time lagging 1s relative to the IEEE1588 hardware time), the TRIGGER mode and the pulse high-low level; initializing a sending configuration register and an output configuration register, forbidding the functions of sending a timestamp and receiving the timestamp, and clearing the sending and receiving timestamps; enabling GPIO interruption of a Linux system; and then initializing a PTP status register, enabling interruption, and finishing the configuration of the PTP chip.
In initializing PTP transmit timestamp operation, bits IP1588_ EN, TX _ L2_ EN, TX _ IPV4_ EN, and TX _ TS _ EN are set in PTP transmit configuration register PTP _ TXCFG 0. The method has the advantages that an IEEE1588 self-defined IP address filtering mechanism is enabled, the detection of the PTP event message time stamp of the IEEE802.3/Ethernet packet is enabled, the detection of the PTP event message time stamp of the IPv4 packet is enabled, and the time stamp sending function is enabled. The PTP transmit configuration register PTP _ TXCFG1 is initialized for matching Byte0 in PTP messages. The operations of initializing the PTP reception timestamp and initializing the PTP transmission timestamp are similar, and 5 PTP reception configuration registers PTP _ RXCFG and PTP reception hash value registers are configured to enable reception of hash values. And finally configuring a PTP interruption control register to enable GPIO interruption, and configuring a PTP status register PTP _ STS to enable sending of a time stamp RDY interruption, receiving of the time stamp RDY interruption, triggering of a completion interruption and event time stamp RDY interruption.
Specifically, in step S2, the setting of a timer thread for detecting system clock change and pulse-to-second transition in the Linux system includes the following steps:
connecting the GPS/Beidou receiving module and the CPLD processing module with a processor running a Linux system;
setting a timer thread for detecting system clock change and second pulse jump in a Linux system, if the second pulse jump occurs, sending a heartbeat checking command to a watchdog program module by the system, and executing heartbeat checking by the watchdog program module;
the system checks the second pulse valid bit in the message transmission of the GPS/Beidou receiving module, and judges whether to adjust the system time and the PHY hardware time according to the valid bit. The workflow of the timer thread is shown in fig. 4.
Specifically, in step S3, the adjusting of the PHY hardware time and the system time by the Linux system includes the following steps:
the pulse per second generated by the PHY hardware clock and the pulse per second of the GPS/Beidou receiving module are accessed to the CPLD processing module;
the CPLD processing module counts the time difference between the mainboard second pulse and the PHY second pulse;
and after the CPLD counts, interruption is generated, the output circuit outputs the counted data to a processor of the Linux system through a bus, and the Linux system takes the counted data away and adjusts the PHY hardware time according to the taken data.
Furthermore, the CPLD processing module counts the time difference of occurrence of the mainboard second pulse and the PHY second pulse by the 50MHZ frequency input by the CPLD, and uses two 16-bit counters to reach a 32-bit counting range. After the data counting is finished, the CPLD is interrupted, then the data is output to the ARM processor through the bus by the output circuit, the counting value is taken away by the Linux software system twice, and the system time and the PHY hardware time are adjusted according to the taken data. The frequency counting circuit is shown in fig. 5.
The Linux system mainly adjusts the PHY hardware time by three modes, namely single step time adjustment, fixed rate adjustment and temporary rate adjustment, and the specific implementation steps are as follows:
(1) updating the counted pulse deviation count value in real time within the first 15 times of effective interruption, and preventing excessive time oscillation of the PHY chip caused by unstable initial count value;
(2) at the 16 th time of the active interrupt, a coarse adjustment is made to the time and fixed rate, and the adjusted time is calculated by the following equation (1)
Wherein PPSCount is a pulse deviation count value, and RATEDIVAL is a PHY output clock effective frequency division value;
the adjusted fixed rate is calculated by the following equation (2)
Wherein, PrePPSCount is the counting value of the last second pulse;
(3) in the next adjustment, in order to reduce the jitter of the PHY hardware clock, the filtering of the depolarization value is temporarily performed every time the pulse deviation count value PPSCount is detected, the excessive deviation value is removed, the time is adjusted in a single step after the filtering is completed, and the adjustment parameter of the fixed rate is calculated by the following formula (3)
Rate＝PreRate+34.3597×PPSCount (3)
Wherein, preRate is the last calculation adjustment value, the value of each adjustment is stepped on the basis of the last adjustment value, and an average filtering algorithm is adopted, and the adjustment is performed every 10 times.
In the method for calibrating the PTP master clock in the non-real-time system, based on the core unit of the ARM and CPLD framework, the ARM processor is combined with the Linux system to realize a network protocol stack, and the CPLD processor conditions peripheral signals, so that the processing difficulty of the peripheral signals of the ARM processor is simplified. In addition, under the design of maintaining the local clock source of the main clock DP83640, the CPLD is adopted to process the satellite second pulse and the second pulse generated by the PHY, the second pulse and the second pulse are compared, and the compared error is sent to a Linux system to be processed, so that the method is quick and effective, and is a new method for correcting the local clock source of the DP83640 PHY.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (4)
1. A method of calibrating a PTP master clock in a non-real time system, the method comprising the steps of:
configuring a PTP chip in a non-real-time system, and calibrating the accuracy of the time of the PTP chip;
the method for setting the timer thread for detecting the clock change and the second pulse jump of the system in the non-real-time system specifically comprises the following steps: connecting the GPS/Beidou receiving module and the CPLD processing module with a processor operating a non-real-time system;
setting a timer thread for detecting system clock change and second pulse jump in a non-real-time system, if the second pulse jump occurs, sending a heartbeat checking command to a watchdog program module by the system, and executing heartbeat checking by the watchdog program module; the system checks the second pulse valid bit in the message transmission of the GPS/Beidou receiving module, and judges whether to adjust the system time and the PHY hardware time according to the valid bit;
the non-real-time system checks the satellite message and the pulse per second signal, and when the satellite message and the pulse per second signal are effective, PHY hardware time is adjusted by taking satellite time as a reference, and then system time is adjusted according to the PHY hardware time;
the non-real-time system adjusts PHY hardware time and system time, and comprises the following steps:
the pulse per second generated by the PHY hardware clock and the pulse per second of the GPS/Beidou receiving module are accessed to the CPLD processing module;
the CPLD processing module counts the time difference between the pulse per second of the GPS/Beidou receiving module and the PHY pulse per second;
the CPLD processing module generates interruption after counting is completed, then the output circuit outputs the counted data to a processor of a non-real-time system through a bus, the non-real-time system takes the counted data away, and the PHY hardware time is adjusted according to the taken data;
the CPLD processing module inputs a PHY hardware clock frequency reference signal after frequency division, counts the time difference of the second pulse of the GPS/Beidou receiving module and the second pulse of the PHY, and counts by using two 16-bit counters;
the non-real-time system adjusts the PHY hardware time and is realized by single-step time adjustment, fixed rate adjustment and temporary rate adjustment;
the non-real-time system adjusts PHY hardware time through single step time adjustment and fixed rate adjustment, and comprises the following steps:
updating the counted pulse deviation count value in real time within the first N times of effective interruption;
at the N +1 th time of the effective interruption, a coarse adjustment is made to the time and the fixed rate, and the adjusted time is calculated by the following formula (1)
Wherein PPSCount is a pulse deviation count value, and RATEDIVAL is a PHY output clock effective frequency division value;
the adjusted fixed rate is calculated by the following equation (2)
Wherein, PrePPSCount is the last pulse deviation counting value;
next, when the pulse deviation count value comes, the depolarization filtering is performed, and after the filtering is completed, the single step adjustment of the fixed rate is performed, and the adjustment parameter of the fixed rate is calculated by the following formula (3)
Rate＝PreRate+34.3597×PPSCount (3)
And the PreRate is a last calculation adjustment value, the value of each adjustment is stepped on the basis of the last adjustment value, and an average filtering algorithm is adopted, and the adjustment is performed every M times.
2. The method for calibrating the PTP master clock in the non-real-time system according to claim 1, wherein the configuring of the PTP chip in the non-real-time system and the calibration of the accuracy of the PTP chip time, comprises the following steps:
connecting the PTP chip with a processor operating a non-real-time system;
adjusting a PTP trigger configuration register PTP _ TRIG, and configuring the GPIO2 to output a trigger signal generated by the PHY;
and adjusting a PTP time register PTP _ TDR, configuring the trigger signal into pulse width output, and triggering at a rising edge.
3. The method according to claim 1, wherein the value of N is 15 and the value of M is 10.
4. A method for calibrating a PTP master clock in a non real time system according to any one of claims 1 to 3 characterised in that the processor running the non real time system uses an ARM processor and the PTP chip uses a DP83640 chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811571615.4A CN109361485B (en) | 2018-12-21 | 2018-12-21 | Method for calibrating PTP (precision time protocol) master clock in non-real-time system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811571615.4A CN109361485B (en) | 2018-12-21 | 2018-12-21 | Method for calibrating PTP (precision time protocol) master clock in non-real-time system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109361485A CN109361485A (en) | 2019-02-19 |
| CN109361485B true CN109361485B (en) | 2020-06-16 |
Family
ID=65329884
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811571615.4A Active CN109361485B (en) | 2018-12-21 | 2018-12-21 | Method for calibrating PTP (precision time protocol) master clock in non-real-time system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109361485B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111726185B (en) * | 2019-03-20 | 2022-10-04 | 北京米文动力科技有限公司 | Method for synchronizing system clocks of external device and local computing device |
| CN113099466A (en) * | 2020-01-09 | 2021-07-09 | 大唐移动通信设备有限公司 | Time difference detection method and device |
| CN111884746B (en) * | 2020-07-17 | 2022-10-18 | 爱瑟福信息科技(上海)有限公司 | Pps second pulse signal output method and system for gptp time synchronization on soc platform |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101789627A (en) * | 2010-01-06 | 2010-07-28 | 江苏方天电力技术有限公司 | High-precision Ethernet timing device |
| CN102013967A (en) * | 2009-09-08 | 2011-04-13 | 郑州威科姆科技股份有限公司 | 1588 protocol-based beidou time synchronization device and application thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100876776B1 (en) * | 2007-04-17 | 2009-01-09 | 삼성전자주식회사 | Method and apparatus for synchronizing time in a communication system using gps information |
| CN101923315A (en) * | 2009-06-17 | 2010-12-22 | 华东电力试验研究院有限公司 | Time synchronization method of electric power system and device thereof |
| ES2547028R1 (en) * | 2012-10-19 | 2015-12-02 | Schweitzer Engineering Laboratories, Inc. | Time distribution device with multi-band antenna |
-
2018
- 2018-12-21 CN CN201811571615.4A patent/CN109361485B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102013967A (en) * | 2009-09-08 | 2011-04-13 | 郑州威科姆科技股份有限公司 | 1588 protocol-based beidou time synchronization device and application thereof |
| CN101789627A (en) * | 2010-01-06 | 2010-07-28 | 江苏方天电力技术有限公司 | High-precision Ethernet timing device |
Non-Patent Citations (2)
| Title |
|---|
| 5G系统中高稳定主时钟技术的研究与实现;张宁;《中国优秀硕士学位论文全文数据库》;20180415(第4期);第23-43页 * |
| LXI设备中精确时钟同步协议的研究与实现;齐靓;《中国优秀硕士学位论文全文数据库》;20131115(第11期);第21-30页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109361485A (en) | 2019-02-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109361485B (en) | Method for calibrating PTP (precision time protocol) master clock in non-real-time system | |
| KR102652569B1 (en) | Implementation of PHY-level hardware timestamping and time synchronization in cost-optimized environments | |
| US7835402B2 (en) | Synchronization module | |
| US11177896B2 (en) | Time synchronization device and time synchronization method | |
| US11994896B2 (en) | Maintaining the correct time when counter values are transferred between clock domains | |
| EP1525693B1 (en) | Clock synchronizing method over fault-tolerant etherent | |
| US8225128B2 (en) | Electronic timer system, time control and generation of timing signals | |
| CN102098194B (en) | Method and system for realizing time synchronization in local area network | |
| US11552871B2 (en) | Receive-side timestamp accuracy | |
| CN103563287B (en) | Synchronization device and synchronization method | |
| US11039408B2 (en) | Methods and apparatus for synchronization among integrated circuits within a wireless network | |
| CN112162591B (en) | Electronic device with multiple processors and synchronization method thereof | |
| WO2010060294A1 (en) | Time synchronization method and apparatus | |
| CN116318510A (en) | Digital conference system and audio clock synchronization method thereof | |
| US11303376B2 (en) | Information processing apparatus and time synchronization method | |
| CN117675072A (en) | Synchronization time determining method, time synchronization device, time synchronization system and medium | |
| JP2001324584A (en) | Time synchronizer, time synchronizing system, and method of controlling time synchronizer | |
| CN214627000U (en) | Network card equipment compatible with definable deterministic communication Ethernet | |
| US11695537B2 (en) | Digital signal processor/network synchronization | |
| US11294421B2 (en) | Precision timing between systems | |
| CN115664627B (en) | 1588 protocol-based frequency synchronization precision detection method and adaptive system | |
| CN111740799B (en) | Smooth synchronization method for Ethernet distributed node | |
| JP3808424B2 (en) | PLL circuit and phase synchronization method | |
| CN117978575A (en) | Method, device and communication system for updating baud rate | |
| CN117478259A (en) | Clock control method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |