CN109361485A - A method of in non real-time system alignment PTP master clock - Google Patents
A method of in non real-time system alignment PTP master clock Download PDFInfo
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- CN109361485A CN109361485A CN201811571615.4A CN201811571615A CN109361485A CN 109361485 A CN109361485 A CN 109361485A CN 201811571615 A CN201811571615 A CN 201811571615A CN 109361485 A CN109361485 A CN 109361485A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0644—External master-clock
Abstract
The embodiment of the invention discloses a kind of methods in non real-time system alignment PTP master clock, are related to Clock Synchronization Technology field.Calibration method is included in configuration PTP chip in non real-time system, and calibrates the accuracy of PTP chip time；The timer thread that detection system clock changes and pulse per second (PPS) jumps is set in non real-time system；Non real-time systems inspection satellite message and second pulse signal, and PHY hardware timeout and system time adjustment are carried out when satellite message and effective second pulse signal.The method in non real-time system alignment PTP master clock of the application, real-time is high, and non-real time operating system very easily can be used to calibrate the precision of PTP master clock, and the precision of calibration reaches submicrosecond grade, meets the requirement of most of PTP time systems.
Description
Technical field
The present embodiments relate to Clock Synchronization Technology fields, and in particular to one kind is in non real-time system alignment PTP master
The method of clock.
Background technique
PTP (Precision Time Protocol, Precision Time Protocol) is a kind of agreement of time synchronization, itself
The precise synchronization that can be used between equipment, the Frequency Synchronization that can also be borrowed between equipment.Compared to NTP (Network
Time Protocol, Network Time Protocol), PTP can satisfy the time synchronization requirement of higher precision, and NTP generally can only achieve
The timing tracking accuracy of submicrosecond grade, and PTP then can reach submicrosecond grade, real-time is very high.
In some non-real time operating systems, by taking (SuSE) Linux OS as an example, Linux itself has powerful network function
Can, and there is the PTP protocol stack of open source, but standard Linux does not provide hard real-time.Based on this, the present invention provides one
Kind meets most of in the method for non real-time system alignment PTP master clock for easily calibrating the precision of PTP master clock
The requirement of PTP time system.
Summary of the invention
The embodiment of the invention provides a kind of methods in non real-time system alignment PTP master clock, for calibrating PTP master
The precision of clock, calibration accuracy reach submicrosecond grade, meet the required precision of most of PTP time systems.
In order to solve the above-mentioned technical problem, the embodiment of the invention discloses following technical solutions:
A method of in non real-time system alignment PTP master clock, the described method comprises the following steps:
PTP chip is configured in non real-time system, and calibrates the accuracy of PTP chip time；
The timer thread that detection system clock changes and pulse per second (PPS) jumps is set in non real-time system；
Non real-time systems inspection satellite message and second pulse signal, and when satellite message and effective second pulse signal, with
The adjustment that PHY hardware timeout is carried out on the basis of satellite time, then carries out system time adjustment according to PHY hardware timeout.
Based on above scheme, this method does following optimization:
Further, the configuration PTP chip is calibrated the accuracy of PTP chip time, is included the following steps:
PTP chip is connect with the processor for running non real-time system；
It adjusts PTP and triggers configuration register PTP_TRIG, GPIO2 is configured as output to the trigger signal of PHY generation；
PTP time register PTP_TDR is adjusted, configures pulsewidth output, rising edge triggering for trigger signal.
Further, described that the timer line that detection system clock changes and pulse per second (PPS) jumps is set in non real-time system
Journey includes the following steps:
GPS/ Beidou receiving module and CPLD processing module are connect with the processor for running non real-time system；
The timer thread that detection system clock changes and pulse per second (PPS) jumps is set in non real-time system, in case of the second
Impulse hits, system, which is sent, checks heartbeat commands to house dog program module, the execution heartbeat inspection of house dog program module；
Pulse per second (PPS) significance bit in the transmission of systems inspection GPS/ Beidou receiving module message, and judged whether according to significance bit
Carry out the adjustment of system time and the adjustment of PHY hardware timeout.
Further, the non real-time system carries out PHY hardware timeout and system time adjustment, includes the following steps:
The pulse per second (PPS) of pulse per second (PPS) and GPS/ Beidou receiving module that PHY hardware clock is generated accesses CPLD processing module；
The time difference that CPLD processing module occurs mainboard pulse per second (PPS) with PHY pulse per second (PPS) counts；
Interruption is generated after the completion of CPLD numeration, then will be counted by bus according to output to non real-time system by output circuit
The processor of system, non real-time system will count according to taking away, and are adjusted according to evidence of fetch to PHY hardware timeout.
The time difference that mainboard pulse per second (PPS) and PHY pulse per second (PPS) occurs in the CPLD processing module input 50MHZ frequency carries out
Numeration, and counted using two 16 digit counters.
Preferably, non real-time system call interception PHY hardware timeout mainly passes through the adjustment of single step time, fixed rate adjustment and faces
When three kinds of modes of speed adjust realize that specific implementation includes the following steps:
In the preceding n times effectively interrupted, the pulse deviation count value of real-time update counting；
In the N+1 times effectively interrupted, a coarse adjustment is carried out to time and fixed rate, the time of adjustment passes through following
Formula (1) calculates
Wherein, PPSCount is pulse deviation count value, and RATEDIVAL is that PHY exports the effective frequency division value of clock；
The fixed rate of adjustment is calculated by following formula (2)
Wherein, PrePPSCount is the count value of last pulse per second (PPS)；
Next, when pulse deviation count value PPSCount temporarily to carry out extreme value and filter, when filtering carries out after completing
Between single step adjustment, the adjusting parameter of fixed rate passes through following formula (3) calculating
Rate=PreRate+34.3597 × PPSCount (3)
Wherein, PreRate is last calculating adjusted value, the value adjusted every time on the basis of upper primary adjusted value into
Row stepping, and average value filtering algorithm is used, every M adjustment is primary.
Preferably, in the above-mentioned adjustment PHY hardware timeout the step of, the value that the value of the N is 15, M is 10.
Further, a kind of method in non real-time system alignment PTP master clock as described above, the non-reality of operation
When system processor use arm processor, PTP chip use DP83640 chip.
The technical scheme provided by the application includes following the utility model has the advantages that
A kind of method in non real-time system alignment PTP master clock provided by the present application, including configuration PTP chip, school
The accuracy of quasi- PTP chip time；The timer that detection system clock changes and pulse per second (PPS) jumps is set in non real-time system
Thread；Non real-time systems inspection satellite message and second pulse signal, and PHY is carried out when satellite message and effective second pulse signal
Hardware timeout and system time adjustment.The method in non real-time system alignment PTP master clock of the application, simplifies peripheral letter
Number processing difficulty, real-time is high, and non-real time operating system very easily can be used to calibrate the precision of PTP master clock, school
Quasi- precision reaches submicrosecond grade, meets the requirement of most of PTP time systems, is new to one of local clock correction fast
The effective method of speed.
Detailed description of the invention
The drawings herein are incorporated into the specification and constitutes part of specification, shows the implementation for meeting the application
Example, and together with specification it is used to explain the principle of the application.
Fig. 1 is that a kind of process in non real-time system alignment PTP master clock method provided by the embodiments of the present application is illustrated
Figure；
Fig. 2 is that a kind of hardware in non real-time system alignment PTP master clock method provided by the embodiments of the present application connects
Schematic diagram；
Fig. 3 is the configuration process flow chart of PTP chip in Fig. 1；
Fig. 4 is the work flow diagram of timer thread in Fig. 1；
Fig. 5 is the frequency counting circuit figure of CPLD processing module.
Specific embodiment
To make those skilled in the art more fully understand the technical solution in the present invention, implement below in conjunction with the present invention
Attached drawing in example, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment
Only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, the common skill in this field
Art personnel every other embodiment obtained without making creative work all should belong to what the present invention protected
Range.
Fig. 1, Fig. 2 are respectively provided by the embodiments of the present application a kind of in non real-time system alignment PTP master clock method
Flow diagram and hardware connection diagram.In the present embodiment, (SuSE) Linux OS is used on software, to (SuSE) Linux OS
It is configured, runs PTP protocol stack；Using arm processor, CPLD processor, the GPS/ north that can run linux system on hardware
Struggle against receiving module and PTP chip, and PTP chip uses DP83640 chip.
As shown in Figure 1, a kind of method in non real-time system alignment PTP master clock of the present embodiment, including following step
It is rapid:
S1, configuration PTP chip, calibrate the accuracy of PTP chip time；
S2, the timer thread that detection system clock changes and pulse per second (PPS) jumps is set in linux system；
S3, linux system check satellite message and pulse signal, and carry out when satellite message and effective pulse signal
PHY hardware timeout and system time adjustment.
Specifically, in the step S1, the configuration process of PTP chip includes:
PTP chip is connect with the processor of operation linux system；
It adjusts PTP and triggers configuration register PTP_TRIG, GPIO2 is configured as output to the TRIGGER signal of PHY generation；
PTP time register PTP_TDR is adjusted, configures pulsewidth output, rising edge triggering for TRIGGER signal.
Furthermore, it is understood that the concrete configuration process of PTP chip is as shown in Figure 3: first detecting whether in above-mentioned steps S1
There are DP83640 chips, and can't detect chip function will exit；Then PTP event registers PTP_EVENT and triggering are reset
Configuration register PTP_TRIG prepares for two registers of configuration；Enabled DP83640 chip 10M network support；Then initial
Change clock source and export configuration register PTP_COC and clock source register PTP_CLKSRC, was initialized in output clock signal
Cheng Zhong configures PTP_CLKOUT EN output CLK signal, and frequency division value is set as 4, PGM inside configuration clock synchronization compliant with precision time protocol source default choice；
The enabled clock synchronization compliant with precision time protocol in the position PTP_ENABLE of set control register；It initializes PTP and triggers configuration register PTP_TRIG, it will
GPIO2 is configured as output to the pulse per second (PPS) of PHY generation, and it is defeated to be configured to pulsewidth for output signal of the TRIGGER signal as DP83640
Out, period 1s, rising edge triggering, duty ratio 10%, setting sequence are to control register selection triggering function by PTP first
Can, TRIG_LOAD starts PTP loading procedure, is subsequently written the rising edge triggered time (TRIGGER of TRIGGER signal pulse per second (PPS)
The rising edge time of signal is arranged with respect to IEEE on the basis of local 1588 hardware clocks quasi- moment second of DP83640
1588 hardware timeouts lag 1s), time of triggering mode, pulse low and high level；Next initialization send configuration register and
Configuration register is exported, forbids sending time stamp and receiving time stamp function, empties transmitting and receiving timestamp；Enabled Linux system
The GPIO that unites is interrupted；Next PTP status register is initialized, enables to interrupt, the configuration of PTP chip terminates.
In initialization PTP sending time stamp operation, PTP sends set IP1588_ in configuration register PTP_TXCFG0
EN, TX_L2_EN, TX_IPV4_EN and TX_TS_EN.The enabled customized IP address strobe utility of IEEE 1588, enables
The detection of the PTP event message timestamp of IEEE802.3/Ethernet package enables the PTP event message time of IPv4 package
The detection of stamp and enabled sending time stamp function.It initializes PTP and sends configuration register PTP_TXCFG1, for matching PTP
Byte0 in message.It is similar with initialization PTP sending time stamp operation to initialize PTP receiving time stamp, configures 5 PTP and receives
Configuration register PTP_RXCFG and PTP receive Hash value register to enable cryptographic Hash is received.Finally configuration PTP interrupts control
Register enables GPIO interruption, and the enabled sending time stamp RDY of configuration PTP status register PTP_STS is interrupted, receiving time is stabbed
RDY is interrupted, triggering completes to interrupt and Event Timestamp RDY is interrupted.
Specifically, setting detection system clock changes in linux system and what pulse per second (PPS) jumped determines in the step S2
When device thread, include the following steps:
GPS/ Beidou receiving module and CPLD processing module are connect with the processor of operation linux system；
The timer thread that detection system clock changes and pulse per second (PPS) jumps is set in linux system, in case of the second
Impulse hits, system, which is sent, checks heartbeat commands to house dog program module, the execution heartbeat inspection of house dog program module；
Pulse per second (PPS) significance bit in the transmission of systems inspection GPS/ Beidou receiving module message, and judged whether according to significance bit
Carry out the adjustment of system time and the adjustment of PHY hardware timeout.The workflow of timer thread is as shown in Figure 4.
Specifically, linux system carries out the adjustment of PHY hardware timeout and system time, including following in the step S3
Step:
The pulse per second (PPS) of pulse per second (PPS) and GPS/ Beidou receiving module that PHY hardware clock is generated accesses CPLD processing module；
The time difference that CPLD processing module occurs mainboard pulse per second (PPS) with PHY pulse per second (PPS) counts；
Interruption is generated after the completion of CPLD numeration, then will be counted by bus according to output to Linux system by output circuit
The processor of system, linux system will count according to taking away, and are adjusted according to evidence of fetch to PHY hardware timeout.
Further, CPLD processing module is to be gone out by the 50MHZ frequency of CPLD input to mainboard pulse per second (PPS) and PHY pulse per second (PPS)
The existing time difference counts, and reaches 32 numeration ranges using two 16 counters.CPLD is produced after the completion of data numeration
It is raw to interrupt, then data are exported to arm processor by bus by output circuit, Linux software systems in two times will numeration
Value is taken away, and is adjusted according to evidence of fetching to system time and PHY hardware timeout.Frequency counting circuit is as shown in Figure 5.
Linux system adjustment PHY hardware timeout mainly passes through the adjustment of single step time, fixed rate adjustment and interim rate tune
Whole three kinds of modes realize that the specific implementation steps are as follows:
(1) in first 15 times effectively interrupted, the pulse deviation count value that real-time update counts is prevented due to initial count
It is worth the unstable excessive concussion for leading to the PHY chip time；
(2) in the 16th time effectively interrupted, a coarse adjustment is carried out to time and fixed rate, under the time of adjustment passes through
State formula (1) calculating
Wherein, PPSCount is pulse deviation count value, and RATEDIVAL is that PHY exports the effective frequency division value of clock；
The fixed rate of adjustment is calculated by following formula (2)
Wherein, PrePPSCount is the count value of last pulse per second (PPS)；
(3) in next adjustment, in order to reduce the shake of PHY hardware clock, whenever pulse deviation count value
PPSCount temporarily to carry out extreme value and filter, and removes excessive deviation, and filtering carries out the single step adjustment of time after completing, Gu
The adjusting parameter of constant speed rate is calculated by following formula (3)
Rate=PreRate+34.3597 × PPSCount (3)
Wherein, PreRate is last calculating adjusted value, the value adjusted every time on the basis of upper primary adjusted value into
Row stepping, and average value filtering algorithm is used, every 10 adjustment are primary.
A kind of method in non real-time system alignment PTP master clock of the present embodiment, the core based on ARM Yu CPLD framework
Heart unit, arm processor combination linux system realize that network protocol stack, CPLD processor improve peripheral signal, simplify ARM
The processing difficulty of processor peripheral signal.In addition, this method is adopted under the design in maintenance master clock DP83640 local clock source
The pulse per second (PPS) of satellite pulse per second (PPS) and PHY generation is handled with CPLD, and the two pulse per second (PPS) is compared, and the error of comparison is sent into
Linux system processing is quickly and effectively a new method to the correction of DP83640PHY local clock source.
The above is only a specific embodiment of the invention, is made skilled artisans appreciate that or realizing this hair
It is bright.Various modifications to these embodiments will be apparent to one skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (8)
1. a kind of method in non real-time system alignment PTP master clock, which is characterized in that the described method comprises the following steps:
PTP chip is configured in non real-time system, and calibrates the accuracy of PTP chip time；
The timer thread that detection system clock changes and pulse per second (PPS) jumps is set in non real-time system, is specifically included: will
GPS/ Beidou receiving module and CPLD processing module are connect with the processor for running non real-time system；It is arranged in non real-time system
The timer thread of the variation of detection system clock and pulse per second (PPS) jump, jumps in case of pulse per second (PPS), and system, which is sent, checks heartbeat
House dog program module is ordered, house dog program module executes heartbeat inspection；Systems inspection GPS/ Beidou receiving module message
Pulse per second (PPS) significance bit in transmission, and according to significance bit judge whether to system time adjustment and PHY hardware timeout tune
It is whole；
Non real-time systems inspection satellite message and second pulse signal, and when satellite message and effective second pulse signal, with satellite
The adjustment that PHY hardware timeout is carried out on the basis of time, then carries out system time adjustment according to PHY hardware timeout.
2. a kind of method in non real-time system alignment PTP master clock according to claim 1, which is characterized in that institute
The configuration PTP chip in non real-time system is stated, and calibrates the accuracy of PTP chip time, is included the following steps:
PTP chip is connect with the processor for running non real-time system；
It adjusts PTP and triggers configuration register PTP_TRIG, GPIO2 is configured as output to the trigger signal of PHY generation；
PTP time register PTP_TDR is adjusted, configures pulsewidth output, rising edge triggering for trigger signal.
3. a kind of method in non real-time system alignment PTP master clock according to claim 1, which is characterized in that institute
It states non real-time system and carries out PHY hardware timeout and system time adjustment, include the following steps:
The pulse per second (PPS) of pulse per second (PPS) and GPS/ Beidou receiving module that PHY hardware clock is generated accesses CPLD processing module；
The time difference that CPLD processing module occurs mainboard pulse per second (PPS) with PHY pulse per second (PPS) counts；
Interruption is generated after the completion of the numeration of CPLD processing module, then will be counted by bus according to output to non-reality by output circuit
When system processor, non real-time system will count according to taking away, and is adjusted according to evidence of fetch to PHY hardware timeout.
4. a kind of method in non real-time system alignment PTP master clock according to claim 3, which is characterized in that institute
Stating CPLD processing module input time difference for occurring to mainboard pulse per second (PPS) with PHY pulse per second (PPS) of 50MHZ frequency counts, and uses
Two 16 digit counters are counted.
5. a kind of method in non real-time system alignment PTP master clock according to claim 4, which is characterized in that institute
It states non real-time system to be adjusted PHY hardware timeout, passes through the adjustment of single step time, fixed rate adjustment and interim speed adjust
It realizes.
6. a kind of method in non real-time system alignment PTP master clock according to claim 5, which is characterized in that institute
It states non real-time system to be adjusted PHY hardware timeout by the adjustment of single step time and fixed rate adjustment, include the following steps:
In the preceding n times effectively interrupted, the pulse deviation count value of real-time update counting；
In the N+1 times effectively interrupted, a coarse adjustment is carried out to time and fixed rate, the time of adjustment passes through following formula
(1) it calculates
Wherein, PPSCount is pulse deviation count value, and RATEDIVAL is that PHY exports the effective frequency division value of clock；
The fixed rate of adjustment is calculated by following formula (2)
Wherein, PrePPSCount is the count value of last pulse per second (PPS)；
Next, filtering carries out the single step adjustment of time when pulse deviation count value temporarily to carry out extreme value and filter after completing,
The adjusting parameter of fixed rate is calculated by following formula (3)
Rate=PreRate+34.3597 × PPSCount (3)
Wherein, PreRate is last calculating adjusted value, and the value adjusted every time is walked on the basis of upper primary adjusted value
Into, and average value filtering algorithm is used, every M adjustment is primary.
7. a kind of method in non real-time system alignment PTP master clock according to claim 6, which is characterized in that institute
The value that the value for stating N is 15, M is 10.
8. a kind of method in non real-time system alignment PTP master clock according to any one of claims 1 to 7, special
Sign is that the processor of the non real-time system of operation uses arm processor, and PTP chip uses DP83640 chip.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111726185A (en) * | 2019-03-20 | 2020-09-29 | 北京米文动力科技有限公司 | Method for synchronizing system clocks of external device and local computing device |
| CN111884746A (en) * | 2020-07-17 | 2020-11-03 | 爱瑟福信息科技(上海)有限公司 | Pps second pulse signal output method and system for gptp time synchronization on soc platform |
| CN113099466A (en) * | 2020-01-09 | 2021-07-09 | 大唐移动通信设备有限公司 | Time difference detection method and device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090034672A1 (en) * | 2007-04-17 | 2009-02-05 | Jae-Hun Cho | Method and apparatus for time synchronization using gps information in communication system |
| CN101789627A (en) * | 2010-01-06 | 2010-07-28 | 江苏方天电力技术有限公司 | High-precision Ethernet timing device |
| CN101923315A (en) * | 2009-06-17 | 2010-12-22 | 华东电力试验研究院有限公司 | Time synchronization method of electric power system and device thereof |
| CN102013967A (en) * | 2009-09-08 | 2011-04-13 | 郑州威科姆科技股份有限公司 | 1588 protocol-based beidou time synchronization device and application thereof |
| US20140114608A1 (en) * | 2012-10-19 | 2014-04-24 | Schweitzer Engineering Laboratories, Inc. | Time Distribution with Multi-Band Antenna |
-
2018
- 2018-12-21 CN CN201811571615.4A patent/CN109361485B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090034672A1 (en) * | 2007-04-17 | 2009-02-05 | Jae-Hun Cho | Method and apparatus for time synchronization using gps information in communication system |
| CN101923315A (en) * | 2009-06-17 | 2010-12-22 | 华东电力试验研究院有限公司 | Time synchronization method of electric power system and device thereof |
| CN102013967A (en) * | 2009-09-08 | 2011-04-13 | 郑州威科姆科技股份有限公司 | 1588 protocol-based beidou time synchronization device and application thereof |
| CN101789627A (en) * | 2010-01-06 | 2010-07-28 | 江苏方天电力技术有限公司 | High-precision Ethernet timing device |
| US20140114608A1 (en) * | 2012-10-19 | 2014-04-24 | Schweitzer Engineering Laboratories, Inc. | Time Distribution with Multi-Band Antenna |
Non-Patent Citations (2)
| Title |
|---|
| 张宁: "5G系统中高稳定主时钟技术的研究与实现", 《中国优秀硕士学位论文全文数据库》 * |
| 齐靓: "LXI设备中精确时钟同步协议的研究与实现", 《中国优秀硕士学位论文全文数据库》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111726185A (en) * | 2019-03-20 | 2020-09-29 | 北京米文动力科技有限公司 | Method for synchronizing system clocks of external device and local computing device |
| CN111726185B (en) * | 2019-03-20 | 2022-10-04 | 北京米文动力科技有限公司 | Method for synchronizing system clocks of external device and local computing device |
| CN113099466A (en) * | 2020-01-09 | 2021-07-09 | 大唐移动通信设备有限公司 | Time difference detection method and device |
| CN111884746A (en) * | 2020-07-17 | 2020-11-03 | 爱瑟福信息科技(上海)有限公司 | Pps second pulse signal output method and system for gptp time synchronization on soc platform |
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