CN102882669A - Two-wire interface time synchronization protocol method - Google Patents
Two-wire interface time synchronization protocol method Download PDFInfo
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- CN102882669A CN102882669A CN2012103019104A CN201210301910A CN102882669A CN 102882669 A CN102882669 A CN 102882669A CN 2012103019104 A CN2012103019104 A CN 2012103019104A CN 201210301910 A CN201210301910 A CN 201210301910A CN 102882669 A CN102882669 A CN 102882669A
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Abstract
The invention provides a two-wire interface time synchronization protocol method. The method comprises the following steps that: S0, a time-service master control board is defined; S1, the time-service master control board extracts time information; S2, the time-service master control board packages the time information; S3, the time-service master control board transmits the packaged time information to a controlled board; S4, the controlled board receives the packaged time information which is transmitted by the time-service master control board; S5, the controlled board decrypts the packaged time information; S6, the controlled board reads the time information; S7, the controlled board verifies the time information; and S8, the controlled board updates time; wherein in the S7, the controlled board verifies the time information by a cyclic redundancy check code. The method has the advantages of simplicity and reliability in requirements, and the method is high in time synchronization accuracy, low in cost and can be easily implemented.
Description
Technical Field
The invention relates to a time synchronization method, in particular to a two-wire interface time synchronization protocol method.
Background
The existing time synchronization protocol is mainly IEEE1588, and the protocol is widely applied to the fields of communication, industrial control and the like. IEEE1588 in the communication and industrial fields is implemented mainly on the basis of an Ethernet underlying network architecture, and IEEE1588 and Ethernet are designed for large and complex networks, require software and hardware to work cooperatively, are very complex and have very high cost. Although IEEE1588 can achieve an accuracy of 1 microsecond, it is not suitable for use in small systems, such as time synchronization between multiple circuit boards in a chassis.
Disclosure of Invention
In order to solve the above problems, the present invention provides a two-wire interface time synchronization protocol method. The invention provides a two-wire interface time synchronization protocol method, which solves the problem of reliable time synchronization among a plurality of circuit boards in a small system such as a chassis.
The technical scheme of the invention is realized as follows:
a two-wire interface time synchronization protocol method includes
S0: defining a time service main control board;
s1: the time service main control board extracts time information;
s2: the time service main control board packages the time information;
s3: the time service main control board sends the packaged time information to the controlled board;
s4: the controlled board receives the packaged time information sent by the time service main control board;
s5: the controlled board decrypts the packaged time information;
s6: the controlled board reads the time information;
s7: the controlled board checks the time information;
s8: controlled board update time; wherein,
in step S7, the controlled board checks the time information with a cyclic redundancy check code.
The two-wire interface time synchronization protocol method is characterized in that the time service main control board and the controlled board are connected in parallel through a low-frequency clock wire and a serial data wire, the time service main control board is provided with a timing clock, the timing clock is set to output a pulse every 0.1ms through the low-frequency clock wire, and meanwhile, packaged time information is sent to the controlled board through the serial data wire.
The two-wire interface time synchronization protocol method is characterized in that the pulse frequency is 8 KHz-12 KHz, and the duty ratio is 20% -70%.
The two-wire interface time synchronization protocol method includes that the time service master control board in step S0 includes a master time service master control board and a slave time service master control board, and step S5 includes:
s501, checking whether the time information of the main time service control board is complete, if so, connecting to S6, and if not, connecting to S502;
and S502, checking whether the time information of the slave time service main control board is complete, if so, performing S6, and if not, performing S1.
In the two-wire interface time synchronization protocol method, the step S7 includes 3 verification steps, which are as follows:
s701: physical electrical layer checking, wherein the occurring interference pulse information is eliminated by limiting the speed of a low-speed clock line and a serial data line;
s702: link data layer check for sending data packet containing positive and negative data, the data packet being accompanied by cyclic redundancy check code;
s703: and (4) system layer checking, namely checking time information by adopting a framework that two time service main control boards service time simultaneously.
The invention has the beneficial effects that: the time synchronization precision is higher, and the sub-subtle precision can be achieved; the method has the advantages that the method is simple to realize and supports master-slave backup, and the system reliability is greatly improved; the cost is low, and the whole protocol can be realized by using a low-cost programmable chip.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a flow chart of a two-wire interface time synchronization protocol method of the present invention;
fig. 2 is a flowchart of the controlled board checking time information in the two-wire interface time synchronization protocol method according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
1-2, a two-wire interface time synchronization protocol method includes
S0: defining a time service main control board, wherein the time service main control board comprises a master time service main control board and a slave time service main control board.
S1: and the time service main control board extracts the time information.
S2: the time service main control board packages the time information, and a 32-bit binary counter is filled into the sent time information data packet to realize the packaging of the time information.
S3: and the time service main control board sends the packaged time information to the controlled board.
S4: and the controlled board receives the packaged time information sent by the time service main control board.
S5: the controlled board decrypts the encapsulated time information, wherein,
s501, checking whether the time information of the master time service main control board is complete, if so, connecting to S6, and if not, connecting to S502;
and S502, checking whether the time information of the slave time service main control board is complete, if so, performing S6, and if not, performing S1.
S6: the controlled board reads the time information.
S7: the controlled board checks the time information through the cyclic redundancy check code, and the step comprises three checking steps which are respectively as follows:
s701, verifying a physical electrical layer, wherein the physical electrical layer is mainly used for limiting the speed of a low-speed clock line and a serial data line to provide a large time sequence margin, so that interference pulse information is eliminated;
s702, link data layer check, which is mainly used for sending data packets containing positive and negative data, wherein the data packets are attached with cyclic redundancy check codes, and can guarantee the correctness of the received time information again;
and S703, checking the system layer, namely checking the time information by adopting an architecture for simultaneously timing by two timing main control boards, and improving the timing reliability on the system layer.
S8: the controlled panel updates the time.
In the two-wire interface time synchronization protocol method, the time information is relative time information.
The two-wire interface time synchronization protocol method is characterized in that the time service main control board and the controlled board are connected in parallel through a low-frequency clock wire and a serial data wire, the time service main control board is provided with a timing clock, the timing clock is set to output a pulse every 0.1ms through the low-frequency clock wire, and meanwhile, packaged time information is sent to the controlled board through the serial data wire; the pulse frequency is 8KHz, and the duty ratio is 20%.
Example 2
The steps of a two-wire interface time synchronization protocol method of this embodiment are the same as those of embodiment 1.
The time information is relative time information. The time service main control board is connected with the controlled board in parallel through a low-frequency clock line and a serial data line, the time service main control board is provided with a timing clock, the timing clock is set to output a pulse every 0.1ms through the low-frequency clock line, and meanwhile, packaged time information is sent to the controlled board through the serial data line; the pulse frequency is 12KHz, and the duty ratio is 70%.
Example 3
The steps of a two-wire interface time synchronization protocol method of this embodiment are the same as those of embodiment 1.
The time information is relative time information. The time service main control board is connected with the controlled board in parallel through a low-frequency clock line and a serial data line, the time service main control board is provided with a timing clock, the timing clock is set to output a pulse every 0.1ms through the low-frequency clock line, and meanwhile, packaged time information is sent to the controlled board through the serial data line; the pulse frequency is 9KHz, and the duty ratio is 55%.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (5)
1. A two-wire interface time synchronization protocol method is characterized in that: comprises that
S0: defining a time service main control board;
s1: the time service main control board extracts time information;
s2: the time service main control board packages the time information;
s3: the time service main control board sends the packaged time information to the controlled board;
s4: the controlled board receives the packaged time information sent by the time service main control board;
s5: the controlled board decrypts the packaged time information;
s6: the controlled board reads the time information;
s7: the controlled board checks the time information;
s8: controlled board update time; wherein,
in step S7, the controlled board checks the time information with a cyclic redundancy check code.
2. The two-wire interface time synchronization protocol method according to claim 1, wherein the time service main control board and the controlled board are connected in parallel through a low frequency clock line and a serial data line, the time service main control board is provided with a timing clock, the timing clock is set to output a pulse through the low frequency clock line every 0.1ms, and the packaged time information is transmitted to the controlled board through the serial data line.
3. The two-wire interface time synchronization protocol method according to claim 2, wherein the pulse frequency is 8KHz to 12KHz, and the duty cycle is 20% to 70%.
4. The two-wire interface time synchronization protocol method according to claim 2, wherein the time service master board in step S0 includes a master time service master board and a slave time service master board, and step S5 includes:
s501, checking whether the time information of the main time service control board is complete, if so, connecting to S6, and if not, connecting to S502;
and S502, checking whether the time information of the slave time service main control board is complete, if so, performing S6, and if not, performing S1.
5. The two-wire interface time synchronization protocol method according to claim 4, wherein the step S7 includes 3 verification steps, specifically as follows:
s701: physical electrical layer checking, wherein the occurring interference pulse information is eliminated by limiting the speed of a low-speed clock line and a serial data line;
s702: link data layer check for sending data packet containing positive and negative data, the data packet being accompanied by cyclic redundancy check code;
s703: and (4) system layer checking, namely checking time information by adopting a framework that two time service main control boards service time simultaneously.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106899371A (en) * | 2015-12-18 | 2017-06-27 | 中兴通讯股份有限公司 | Method for synchronizing time and device |
| CN110912634A (en) * | 2019-10-25 | 2020-03-24 | 深圳震有科技股份有限公司 | Method for realizing clock synchronization based on SPI, storage medium and terminal equipment |
| WO2021147502A1 (en) * | 2020-01-20 | 2021-07-29 | 南京深视光点科技有限公司 | Method for global time synchronization by combining data packet and short pulse |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101296066A (en) * | 2008-06-30 | 2008-10-29 | 杭州华三通信技术有限公司 | Real time clock synchronization method of distributed system, master control board and cable fastener plate |
| CN102497245A (en) * | 2011-12-19 | 2012-06-13 | 杭州华三通信技术有限公司 | Clock synchronization method and clock management interface board |
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- 2012-08-23 CN CN2012103019104A patent/CN102882669A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101296066A (en) * | 2008-06-30 | 2008-10-29 | 杭州华三通信技术有限公司 | Real time clock synchronization method of distributed system, master control board and cable fastener plate |
| CN102497245A (en) * | 2011-12-19 | 2012-06-13 | 杭州华三通信技术有限公司 | Clock synchronization method and clock management interface board |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106899371A (en) * | 2015-12-18 | 2017-06-27 | 中兴通讯股份有限公司 | Method for synchronizing time and device |
| CN110912634A (en) * | 2019-10-25 | 2020-03-24 | 深圳震有科技股份有限公司 | Method for realizing clock synchronization based on SPI, storage medium and terminal equipment |
| WO2021147502A1 (en) * | 2020-01-20 | 2021-07-29 | 南京深视光点科技有限公司 | Method for global time synchronization by combining data packet and short pulse |
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