CN113140633A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN113140633A CN113140633A CN202010055754.2A CN202010055754A CN113140633A CN 113140633 A CN113140633 A CN 113140633A CN 202010055754 A CN202010055754 A CN 202010055754A CN 113140633 A CN113140633 A CN 113140633A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 173
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 238000000034 method Methods 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 238000002513 implantation Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 14
- 239000000758 substrate Substances 0.000 description 7
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- 230000005669 field effect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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Abstract
The invention discloses a semiconductor device and a manufacturing method thereof, the semiconductor device includes: a first conductive type semiconductor layer; a second conductivity type semiconductor region disposed within the first surface of the first conductivity type semiconductor layer; a first conductivity type semiconductor region disposed within the second conductivity type semiconductor region; a drift region disposed on a first surface of the first conductive type semiconductor layer, the drift region being of the first conductive type; a well region disposed in the drift region and contacting the first conductivity type semiconductor region, the well region being of a second conductivity type; a gate insulating layer formed at least on a side surface of the well region and contacting the first conductivity type semiconductor region; a gate electrode disposed on the gate insulating layer; and a source electrode disposed on the first conductive type semiconductor region. The sharp corner of the gate insulating layer of the semiconductor device is arranged above the first semiconductor device and is far away from a large electric field in the first conductive type semiconductor layer, so that the sharp corner electric field at the gate insulating layer can be reduced.
Description
Technical Field
The invention relates to the field of transistor structures, in particular to a semiconductor device and a manufacturing method thereof.
Background
The development of semiconductor device structures ranges from planar semiconductor devices to trench semiconductor devices. Compared with a planar semiconductor device, the groove semiconductor device has the advantages that the conducting channel is located in the vertical direction, parasitic JFET (junction field effect transistor) resistance of the planar semiconductor device is eliminated, the cell size is reduced, current density is obviously improved, and meanwhile on-resistance is also reduced. The conventional trench semiconductor device, as shown in fig. 10, includes a first conductive type semiconductor layer 10, a source region 20, a gate electrode 30, and a gate insulating layer 40. The bottom of the gate insulating layer 40 has two sharp corners exposed in the first conductive type semiconductor layer 10, and there are sharp electric fields at the two sharp corners due to a large electric field in the first conductive type semiconductor layer 10, thereby causing instability of the trench semiconductor device.
Disclosure of Invention
In view of the above, the present invention provides a semiconductor device and a method for manufacturing the same, so as to solve the problem that the trench semiconductor device is unstable due to the existence of a peak electric field at the bottom of the gate insulating layer of the trench semiconductor device.
According to a first aspect, embodiments of the present invention provide a semiconductor device, including: a first conductive type semiconductor layer; a second conductivity type semiconductor region disposed within the first surface of the first conductivity type semiconductor layer; a first conductivity type semiconductor region disposed within the second conductivity type semiconductor region; a drift region disposed on a first surface of the first conductive type semiconductor layer, the drift region being of the first conductive type; a well region disposed in the drift region and contacting the first conductivity type semiconductor region, the well region being of a second conductivity type; a gate insulating layer formed at least on a side surface of the well region and contacting the first conductivity type semiconductor region; a gate electrode disposed on the gate insulating layer; and a source electrode disposed on the first conductive type semiconductor region.
Optionally, the semiconductor device further comprises: and a drain electrode disposed on the second surface of the first conductive type semiconductor layer.
Optionally, the drift region is disposed between two adjacent sources.
Optionally, the gate insulating layer covers the drift region.
Optionally, the doping concentration of the well region is 1 × 1015cm-3-5×1018cm-3。
Optionally, the height of the drift region is 0.3 μm to 1.0 μm and the width of the drift region is 1.0 μm to 5.0 μm.
Optionally, the well region has a height of 0.1 μm to 0.5 μm and a width of 0.1 μm to 1.0 μm.
According to a second aspect, embodiments of the present invention provide a method of manufacturing a semiconductor device, including: forming a first conductive type semiconductor layer; forming a second conductive type semiconductor region within the first surface of the first conductive type semiconductor layer; forming a first conductivity type semiconductor region in the second conductivity type semiconductor region; forming a drift region on a first surface of the first conductive type semiconductor layer, the drift region being of the first conductive type; forming a well region in the drift region, the well region being in contact with the first conductivity type semiconductor region, the well region being of a second conductivity type; forming a gate insulating layer at least on a side surface of the well region, the gate insulating layer being in contact with the first conductivity type semiconductor region; forming a gate electrode on the gate insulating layer; a source electrode is formed on the first conductive type semiconductor region.
Optionally, forming a drift region on the first surface of the first conductive type semiconductor layer includes: forming a first conductive type material layer on a first surface of the first conductive type semiconductor layer by epitaxial growth; and removing part of the first conductive type material layer covering the upper part of the source region by an etching method to form a drift region.
Optionally, a well region is formed in the drift region, including: forming a well region in the drift region by ion implantation with an implantation energy of 50-900 KeV and an implantation dose of 5 × 1012cm-2-1×1014cm-2。
Optionally, the method of manufacturing a semiconductor device further comprises: a drain electrode is formed on the second surface of the first conductive type semiconductor layer.
According to the semiconductor device and the manufacturing method thereof provided by the embodiment of the invention, the drift region is arranged on the first surface of the first conductive type semiconductor layer, the well region is arranged in the drift region, and the gate insulating layer are at least formed on the side surface of the well region, so that the sharp corner of the gate insulating layer of the semiconductor device is arranged above the first semiconductor device and is far away from a large electric field in the first conductive type semiconductor layer, the electric field at the sharp corner of the gate insulating layer can be reduced, and the stability of the semiconductor device is improved; and the well region is arranged separately relative to the source region, so that the depth and the doping concentration of the well region are adjustable, the channel is formed on the side surface of the well region, and the channel mobility and the threshold voltage of the semiconductor device can be optimized by adjusting the depth and the doping concentration of the well region.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 shows a schematic diagram of a MOSFET in an implementation of the present invention;
fig. 2 is a sectional view showing a process of manufacturing a first conductivity type semiconductor layer in the method of manufacturing a semiconductor device in the embodiment of the present invention;
fig. 3 is a sectional view showing a process of manufacturing a second conductivity type semiconductor region in the method of manufacturing a semiconductor device in the embodiment of the present invention;
fig. 4 is a sectional view showing a process of manufacturing a first conductivity type semiconductor region in the method of manufacturing a semiconductor device in the embodiment of the present invention;
fig. 5 is a sectional view showing a process of manufacturing a drift region in a method of manufacturing a semiconductor device in an embodiment of the present invention;
fig. 6 is a sectional view showing a well region manufacturing process in the method of manufacturing the semiconductor device in the embodiment of the present invention;
fig. 7 is a sectional view showing a gate insulating layer manufacturing process in the method of manufacturing the semiconductor device in the embodiment of the present invention;
fig. 8 is a sectional view showing a gate manufacturing process in the method of manufacturing the semiconductor device in the embodiment of the present invention;
fig. 9 is a sectional view showing another drift region manufacturing process in the method of manufacturing the semiconductor device in the embodiment of the present invention;
fig. 10 shows a schematic diagram of a prior art trench MOSFET structure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
This invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art, and the present invention will only be defined by the appended claims. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity.
It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Also, it will be understood that when an element (e.g., a layer, region or substrate) is referred to as being "on" or extending "over" another element, it can be directly on or extend directly over the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
Relative terms (e.g., "below …" or "above …" or "upper" or "lower" or "horizontal" or "vertical") may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated in the figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.
In order to reduce the spike electric field at the bottom of the gate insulating layer of the trench semiconductor device, an embodiment of the present invention provides a semiconductor device, as shown in fig. 1, including a first conductivity type semiconductor layer 1; a second conductivity type semiconductor region 2 provided in the first surface of the first conductivity type semiconductor layer 1; a first conductivity type semiconductor region 6 provided within the second conductivity type semiconductor region 2; a drift region 3 disposed on a first surface of the first conductivity type semiconductor layer 1, the drift region 3 being of the first conductivity type; a well region 4 disposed in the drift region 3 and contacting the first conductivity type semiconductor region 6, the well region 4 being of a second conductivity type; a gate insulating layer 8 formed at least on the side of the well region 4 and in contact with the first conductivity type semiconductor region 6; a gate electrode 5 disposed on the gate insulating layer 8; and a source electrode 7 disposed on the first conductivity type semiconductor region 6.
Specifically, the first conductivity type may be N-type or P-type, and is not limited herein. In order to facilitate understanding of the present invention, the first conductivity type is an N-type in the embodiments of the present invention. The first conductive type semiconductor layer 1 includes a substrate 11 and a first drift region 12. The drift region 3 is a second drift region. The first drift region 12 and the drift region 3 are both of the first conductivity type, and the doping concentration of the first drift region 12 and the doping concentration of the drift region 3 may or may not be the same. And a gate insulating layer 8 formed at least on the side of the drift region 3 and in contact with the well region 4 and the first conductivity type semiconductor region 6, respectively. The well region 4 is a second P-well for forming a channel at the side of the well region 4. The doping concentration of the well region 4 is smaller than the doping concentration of the second conductivity type semiconductor region 2.
According to the semiconductor device provided by the embodiment of the invention, the drift region is arranged on the first surface of the first conductive type semiconductor layer, the well region is arranged in the drift region, and the gate insulating layer are at least formed on the side surface of the well region, so that the sharp corner of the gate insulating layer of the semiconductor device is arranged above the first semiconductor device and is far away from a large electric field in the first conductive type semiconductor layer, the electric field at the sharp corner of the gate insulating layer can be reduced, and the stability of the semiconductor device is improved; and the well region is arranged separately relative to the source region, so that the depth and the doping concentration of the well region are adjustable, the channel is formed on the side surface of the well region, and the channel mobility and the threshold voltage of the semiconductor device can be optimized by adjusting the depth and the doping concentration of the well region.
In an alternative embodiment, the semiconductor device further comprises: and a drain electrode disposed on the second surface of the first conductive type semiconductor layer 1. Specifically, the drain electrode is provided on the second surface of the substrate 11 away from the drift layer 12, and the drain electrode is provided on the second surface of the first conductivity type semiconductor layer 1, so that an NPN type semiconductor device can be formed.
In an alternative embodiment, the drift region 3 is disposed between two adjacent sources 7. Specifically, the drift region 3 is disposed between two adjacent source electrodes 7 and extends to be in contact with the first conductivity type semiconductor region 6, so that the well region 4 can be disposed within the drift region 3 and in contact with the first conductivity type semiconductor region 6, so that the channel can be in direct contact with the first conductivity type semiconductor region 6 to form a current path, and the gate can be formed on the side of the drift region 3 and in direct contact with the first conductivity type semiconductor region 6, so that one sharp corner of the gate insulating layer 8 is in direct contact with the source electrode 2 through the first conductivity type semiconductor region, and since the source electrode 2 is always grounded, the electric field of the sharp corner of the gate insulating layer 51 is always zero.
In an alternative embodiment, the gate insulation layer 8 covers the drift region 3. In particular, the gate insulation layer 8 may entirely cover the drift region.
In an alternative embodiment, the doping concentration of the well region 4 is preferably 1 × 1015cm-3-5×1018cm-3. The doping of the well region 4 is set to 1 x 1015cm-3-1×1018cm-3So that the doping concentration of the well region 4 is smaller and the resistance of the well region can be reduced.
In an alternative embodiment, the height of the drift region 3 is preferably 0.3 μm to 1.0 μm and the width of the drift region 3 is preferably 1.0 μm to 5.0 μm. Specifically, the height of the drift region 3 is set to 0.3 μm to 1.0 μm, and the width of the drift region 3 is set to 1.0 μm to 5.0 μm, so that the size of the drift region 3 is appropriate without making the size of the semiconductor device excessively large.
In an alternative embodiment, the height of the well region 4 is preferably 0.1 μm to 0.5 μm, and the width of the well region 4 is preferably 0.1 μm to 1.0 μm. Specifically, the well region 4 is disposed on the side of the drift region 3, the height of the well region 4 is set to 0.1 μm to 0.5 μm, and the width of the well region 4 is set to 0.1 μm to 1.0 μm, so that the size of the well region 4 is not too large and the resistance of the well region 4 is not so large.
In an alternative embodiment, the semiconductor device may be a MOSFET device, such as the MOSFET shown in fig. 1. Even more preferred are silicon carbide MOSFET devices. The semiconductor device may also be an Insulated Gate Bipolar Transistor (IGBT), a double differential field effect transistor or a metal oxide semiconductor controlled thyristor.
An embodiment of the present invention further provides a method for manufacturing a semiconductor device, including:
a first conductive type semiconductor layer 1 is formed as shown in fig. 2. The first conductivity type semiconductor layer 1 may be formed by a known technique, for example, by providing a first conductivity type substrate 11, and forming the first drift region 12 on the first conductivity type substrate 11 by means of epitaxial growth.
A second conductivity type semiconductor region 2 is formed in the first surface of the first conductivity type semiconductor layer 1 as shown in fig. 3. Specifically, the second conductivity type semiconductor region 2 may include a P-well region and a P region disposed on the P-well region. The P well region and the P region may be formed in the first surface of the first conductive type semiconductor 1 by plating, evaporation, ion implantation or epitaxial growth, respectively.
The first-conductivity-type semiconductor region 6 is formed within the second-conductivity-type semiconductor region 2 as shown in fig. 4. Specifically, the first conductivity-type semiconductor region 6 may be formed within the second conductivity-type semiconductor region 2 by means of plating, evaporation, ion implantation, or epitaxial growth.
A drift region is formed on a first surface of the first conductivity type semiconductor layer, the drift region being of the first conductivity type, a well region 4 is formed within the drift region 3, the well region 4 being in contact with a first conductivity type semiconductor region 6, the well region 4 being of the second conductivity type. Specifically, the first conductive type material layer 9 may be formed on the first surface of the first conductive type semiconductor 1 by means of plating, evaporation, ion implantation or epitaxial growth, as shown in fig. 5. Well regions 4 are formed in first conductivity type material layer 9 by ion implantation, trench filling, etc. The doping concentration of the well region 4 is smaller than the doping concentration of the second conductivity type semiconductor region 2 as shown in fig. 6. The drift region 3 is formed by removing a portion of the first-conductivity-type material layer 9 that partially covers the upper portion of the first-conductivity-type semiconductor region 6 by means of etch etching, as shown in fig. 7. The doping concentration of the drift region 3 and the doping concentration of the first drift region 12 in the first conductivity type semiconductor 1 may be the same or different, and when the doping concentration of the drift region 3 is the same as the doping concentration of the first drift region 12, the drift region 3 may be formed together with the first drift region 12.
A gate insulating layer 8 is formed at least on the side of the well region 4, the gate insulating layer 8 being in contact with the first conductivity type semiconductor region 6, as shown in fig. 8. Specifically, the gate insulating layer 8 is formed on the side of the drift region 3 so that the sharp corner of the gate insulating layer 8 is away from the large electric field in the first conductivity type semiconductor layer 1.
The gate electrode 5 is formed on the gate insulating layer 8 as shown in fig. 9.
A source electrode 7 is formed on the first conductivity type semiconductor region 6 as shown in fig. 1.
According to the manufacturing method of the semiconductor device, the drift region is arranged on the first surface of the first conduction type semiconductor layer, the well region is arranged in the drift region, and the grid electrode insulating layer are at least formed on the side face of the well region, so that the sharp corner of the grid electrode insulating layer of the semiconductor device is arranged above the first semiconductor device and is far away from a large electric field in the first conduction type semiconductor layer, the electric field at the sharp corner of the grid electrode insulating layer can be reduced, and the stability of the semiconductor device is improved; and the well region is arranged separately relative to the source region, so that the depth and the doping concentration of the well region are adjustable, the channel is formed on the side surface of the well region, and the channel mobility and the threshold voltage of the semiconductor device can be optimized by adjusting the depth and the doping concentration of the well region.
In an alternative embodiment, the well region 4 may be formed in the drift region 3 by ion implantation with a dose of 5 × 10, 50KeV to 900KeV12cm-2-1×1014cm-2. The well region 4 is formed in the drift region 3 by means of ion implantation, so that the doping concentration of the well region 4 can be controlled more accurately.
In an alternative embodiment, the method of manufacturing a semiconductor device further comprises: a drain electrode is formed on the second surface of the first conductive type semiconductor layer. Specifically, the drain electrode is disposed on a second surface of the substrate 11 away from the first drift region 12, and the drain electrode is disposed on a second surface of the first conductivity type semiconductor layer 1, so that an NPN type semiconductor device can be formed.
Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.
Claims (11)
1. A semiconductor device, comprising:
a first conductive type semiconductor layer;
a second conductivity type semiconductor region disposed within a first surface of the first conductivity type semiconductor layer;
a first conductivity type semiconductor region disposed within the second conductivity type semiconductor region;
a drift region disposed on a first surface of the first conductive type semiconductor layer, the drift region being of a first conductive type;
a well region disposed within the drift region and contacting the first conductivity type semiconductor region, the well region being of a second conductivity type;
a gate insulating layer formed at least on a side of the well region and contacting the first conductivity type semiconductor region;
a gate electrode disposed on the gate insulating layer;
a source electrode disposed on the first conductive type semiconductor region.
2. The semiconductor device according to claim 1, further comprising:
and a drain electrode disposed on the second surface of the first conductive type semiconductor layer.
3. The semiconductor device according to claim 1, wherein the drift region is provided between adjacent two of the source electrodes.
4. The semiconductor device of claim 1, wherein the gate insulating layer covers the drift region.
5. The semiconductor device of claim 1, wherein the doping concentration of the well region is 1 x 1015cm-3-5×1018cm-3。
6. The semiconductor device according to claim 1, wherein the height of the drift region is 0.3 μm to 1.0 μm, and the width of the drift region is 1.0 μm to 5.0 μm.
7. The power semiconductor device of claim 1, wherein the well region has a height of 0.1 μm to 0.5 μm and a width of 0.1 μm to 1.0 μm.
8. A method of manufacturing a semiconductor device, comprising:
forming a first conductive type semiconductor layer;
forming a second conductive type semiconductor region in the first surface of the first conductive type semiconductor layer;
forming a first conductive type semiconductor region within the second conductive type semiconductor region;
forming a drift region on a first surface of the first conductive type semiconductor layer, the drift region being of a first conductive type;
forming a well region in the drift region, the well region being in contact with the first conductivity type semiconductor region, the well region being of a second conductivity type;
forming a gate insulating layer at least on a side surface of the well region, the gate insulating layer being in contact with the first conductivity type semiconductor region;
forming a gate electrode on the gate insulating layer;
a source is formed on the first conductivity type semiconductor region.
9. The method of manufacturing a semiconductor device according to claim 8, wherein the forming a drift region on the first surface of the first conductivity type semiconductor layer comprises:
forming a first conductive type material layer on a first surface of the first conductive type semiconductor layer by epitaxial growth;
and removing part of the first conductive type material layer covering the upper part of the source region by an etching method to form the drift region.
10. The method of manufacturing a semiconductor device according to claim 8, wherein the forming of the well region in the drift region comprises:
forming a well region in the drift region by ion implantation with an implantation energy of 50-900 KeV and an implantation dose of 5 × 1012cm-2-1×1014cm-2。
11. The method of manufacturing a semiconductor device according to claim 8, further comprising:
a drain electrode is formed on the second surface of the first conductive type semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010055754.2A CN113140633B (en) | 2020-01-17 | 2020-01-17 | Semiconductor device and manufacturing method thereof |
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| CN1729577A (en) * | 2002-12-20 | 2006-02-01 | 克里公司 | Silicon carbide power metal-oxide semiconductor field effect transistors and manufacturing methods |
| US20080296771A1 (en) * | 2007-05-31 | 2008-12-04 | Cree, Inc. | Methods of fabricating silicon carbide power devices by at least partially removing an n-type silicon carbide substrate, and silicon carbide power devices so fabricated |
| US20090189228A1 (en) * | 2008-01-25 | 2009-07-30 | Qingchun Zhang | Semiconductor transistor with p type re-grown channel layer |
| US20120205739A1 (en) * | 2009-10-22 | 2012-08-16 | Panasonic Corporation | Semiconductor device and process for production thereof |
| CN105103297A (en) * | 2012-12-28 | 2015-11-25 | 科锐 | Semiconductor devices having reduced electric field at gate oxide layer |
| US20190229191A1 (en) * | 2016-07-14 | 2019-07-25 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing same |
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|---|---|---|---|---|
| CN1729577A (en) * | 2002-12-20 | 2006-02-01 | 克里公司 | Silicon carbide power metal-oxide semiconductor field effect transistors and manufacturing methods |
| US20080296771A1 (en) * | 2007-05-31 | 2008-12-04 | Cree, Inc. | Methods of fabricating silicon carbide power devices by at least partially removing an n-type silicon carbide substrate, and silicon carbide power devices so fabricated |
| US20090189228A1 (en) * | 2008-01-25 | 2009-07-30 | Qingchun Zhang | Semiconductor transistor with p type re-grown channel layer |
| US20120205739A1 (en) * | 2009-10-22 | 2012-08-16 | Panasonic Corporation | Semiconductor device and process for production thereof |
| CN105103297A (en) * | 2012-12-28 | 2015-11-25 | 科锐 | Semiconductor devices having reduced electric field at gate oxide layer |
| US20190229191A1 (en) * | 2016-07-14 | 2019-07-25 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing same |
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