CN113132161A - ZYNQ-based data acquisition and transmission method, device, equipment and storage medium - Google Patents
ZYNQ-based data acquisition and transmission method, device, equipment and storage medium Download PDFInfo
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- CN113132161A CN113132161A CN202110410701.2A CN202110410701A CN113132161A CN 113132161 A CN113132161 A CN 113132161A CN 202110410701 A CN202110410701 A CN 202110410701A CN 113132161 A CN113132161 A CN 113132161A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/02—Standardisation; Integration
- H04L41/0246—Exchanging or transporting network management information using the Internet; Embedding network management web servers in network elements; Web-services-based protocols
- H04L41/0266—Exchanging or transporting network management information using the Internet; Embedding network management web servers in network elements; Web-services-based protocols using meta-data, objects or commands for formatting management information, e.g. using eXtensible markup language [XML]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/062—Securing storage systems
- G06F3/0622—Securing storage systems in relation to access
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
- H04L41/0803—Configuration setting
Abstract
The invention discloses a ZYNQ-based data acquisition and transmission method, a ZYNQ-based data acquisition and transmission device, ZYNQ-based data acquisition and transmission equipment and a storage medium, wherein the ZYNQ-based data acquisition and transmission equipment comprises the following steps: receiving and analyzing configuration parameters sent by an upper computer to obtain an operation instruction; controlling an ADC module to collect data through a state machine at the PL end based on the operation instruction and writing the collected data into a memory; the data are read from the memory and transmitted to the upper computer, and the data acquisition and transmission rate can be well improved.
Description
Technical Field
The invention relates to the field of communication transmission, in particular to a ZYNQ-based data acquisition and transmission method, device, equipment and storage medium.
Background
Data acquisition systems have been commonly used in people's daily life; the existing data acquisition system usually acquires data through a single chip microcomputer, but the acquisition system of the single chip microcomputer has low acquisition rate, and the rate cannot meet the requirement of real-time data transmission processing due to low clock frequency, so that the acquisition and transmission efficiency of the data is limited.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the prior art.
Therefore, the invention provides a data acquisition and transmission method based on ZYNQ, which can well improve the data acquisition and transmission rate.
The invention also provides a ZYNQ-based data acquisition and transmission device applying the ZYNQ-based data acquisition and transmission method.
The invention also provides data acquisition and transmission equipment based on the ZYNQ, which applies the data acquisition and transmission method based on the ZYNQ.
The invention also provides a computer readable storage medium applying the ZYNQ-based data acquisition and transmission method.
The ZYNQ-based data acquisition and transmission method in the embodiment of the first aspect of the invention comprises the following steps:
receiving and analyzing configuration parameters sent by an upper computer to obtain an operation instruction;
controlling an ADC module to collect data through a state machine at the PL end based on the operation instruction and writing the collected data into a memory;
and reading data from the memory and transmitting the data to the upper computer.
The data acquisition and transmission method based on ZYNQ provided by the embodiment of the invention at least has the following beneficial effects: firstly, a ZYNQ chip receives configuration parameters sent by an upper computer, and then the configuration parameters are analyzed to obtain corresponding operation instructions; then controlling an ADC module to carry out data acquisition processing through a state machine at the PL end according to the obtained operation instruction, and writing the acquired data into a memory; then reading data from the memory and transmitting the data to the upper computer; the PL end is an FPGA which is composed of programmable logic units, and the FPGA adopts parallel processing, so that the data acquisition and transmission efficiency can be greatly improved, the data transmission is more stable, the real-time performance is better, and the data is not easy to lose.
According to some embodiments of the present invention, the receiving and analyzing the configuration parameters sent by the upper computer to obtain the operation instruction includes:
receiving configuration parameters sent by an upper computer through a CPU at a PS end;
and analyzing the configuration parameters through a CPU at the PS end to obtain an operation instruction.
According to some embodiments of the invention, the controlling, by the state machine at the PL end, the ADC module to collect data and write the collected data into the memory based on the operation instruction includes:
sending the operation instruction to a soft processor of a PL (packet data) end through a CPU (central processing unit) of the PS end;
starting a state machine of the PL end through a soft processor of the PL end;
controlling an ADC module to collect data through a state machine at a PL end;
and writing the collected data into a memory.
According to some embodiments of the invention, the reading of the data from the memory and the transmission of the data to the upper computer comprises:
when the data is written in the memory, a state machine at the PL end sends a trigger signal to a CPU at the PS end;
triggering a CPU at the PS end to read data from the memory;
and the read data is sent to the upper computer through the network port by the CPU at the PS end.
According to some embodiments of the invention, the memory is a RAM memory.
According to some embodiments of the invention, the ADC module comprises two 4-way channel AD9228 chips.
The ZYNQ-based data acquisition and transmission device comprises:
the processing unit is used for receiving and analyzing the configuration parameters sent by the upper computer to obtain an operation instruction;
the acquisition storage unit is used for controlling the ADC module to acquire data through a state machine at the PL terminal based on the operation instruction and writing the acquired data into a memory;
and the reading and sending unit is used for reading data from the memory and transmitting the data to the upper computer.
According to some embodiments of the invention, the processing unit comprises:
the receiving unit is used for receiving the configuration parameters sent by the upper computer through the CPU at the PS end;
and the analysis unit is used for analyzing the configuration parameters through the CPU at the PS end to obtain an operation instruction.
The ZYNQ-based data acquisition and transmission device provided by the embodiment of the invention at least has the following beneficial effects: firstly, a ZYNQ chip receives configuration parameters sent by an upper computer, and then the configuration parameters are analyzed to obtain corresponding operation instructions; then controlling an ADC module to carry out data acquisition processing through a state machine at the PL end according to the obtained operation instruction, and writing the acquired data into a memory; then reading data from the memory and transmitting the data to the upper computer; the PL end is an FPGA which is composed of programmable logic units, and the FPGA adopts parallel processing, so that the data acquisition and transmission efficiency can be greatly improved, the data transmission is more stable, the real-time performance is better, and the data is not easy to lose.
According to the data acquisition and transmission device based on ZYNQ of the third aspect of the invention, the data acquisition and transmission method based on ZYNQ of the first aspect of the invention can be applied.
The ZYNQ-based data acquisition and transmission equipment provided by the embodiment of the invention at least has the following beneficial effects: firstly, a ZYNQ chip receives configuration parameters sent by an upper computer, and then the configuration parameters are analyzed to obtain corresponding operation instructions; then controlling an ADC module to carry out data acquisition processing through a state machine at the PL end according to the obtained operation instruction, and writing the acquired data into a memory; then reading data from the memory and transmitting the data to the upper computer; the PL end is an FPGA which is composed of programmable logic units, and the FPGA adopts parallel processing, so that the data acquisition and transmission efficiency can be greatly improved, the data transmission is more stable, the real-time performance is better, and the data is not easy to lose.
According to the computer-readable storage medium of the fourth aspect of the present invention, the ZYNQ-based data collection and transmission method according to the first aspect of the present invention can be applied.
The computer-readable storage medium according to the embodiment of the invention has at least the following advantages: firstly, a ZYNQ chip receives configuration parameters sent by an upper computer, and then the configuration parameters are analyzed to obtain corresponding operation instructions; then controlling an ADC module to carry out data acquisition processing through a state machine at the PL end according to the obtained operation instruction, and writing the acquired data into a memory; then reading data from the memory and transmitting the data to the upper computer; the PL end is an FPGA which is composed of programmable logic units, and the FPGA adopts parallel processing, so that the data acquisition and transmission efficiency can be greatly improved, the data transmission is more stable, the real-time performance is better, and the data is not easy to lose.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a flowchart of a data acquisition and transmission method based on ZYNQ according to a first embodiment of the present invention;
fig. 2 is a flowchart of a first embodiment of the present invention for receiving and analyzing parameters in a ZYNQ-based data acquisition and transmission method;
fig. 3 is a flowchart of a data acquisition and transmission method based on ZYNQ according to a first embodiment of the present invention;
fig. 4 is a flowchart of a first embodiment of the present invention, in which data is read and sent in a data acquisition and transmission method based on ZYNQ;
FIG. 5 is a flowchart illustrating the operation of a state machine at the PL terminal in a ZYNQ-based data acquisition and transmission method according to a first embodiment of the present invention;
fig. 6 is a schematic structural diagram of an ADC module and an FPGA in the data acquisition and transmission method based on ZYNQ according to the first embodiment of the present invention;
FIG. 7 is a schematic structural diagram of a ZYNQ-based data acquisition and transmission device according to a second embodiment of the present invention;
fig. 8 is a schematic structural diagram of data acquisition and transmission equipment based on ZYNQ according to a third embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, unless otherwise explicitly defined, terms such as arrangement, connection and the like should be broadly construed, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the detailed contents of the technical solutions.
Description of the drawings: the ZYNQ chip comprises a PS end and a PL end; the PS end comprises a CPU of a hard core processor, and the PL end comprises an FPGA of a soft processor; by applying the ZYNQ chip, the general processing function of a CPU can be utilized, and the programmable logic part of an FPGA is also adopted. A high-speed interface is needed for high-speed data acquisition and transmission, so that the parallel processing function of the FPGA can be well completed. And secondly, synchronously processing asynchronous data by using BRAM resources aiming at different clock domains in the acquisition system.
Example one
Referring to fig. 1, a data acquisition and transmission method based on ZYNQ is provided in an embodiment of the present invention, where an embodiment includes, but is not limited to, the following steps:
and step S100, receiving and analyzing the configuration parameters sent by the upper computer to obtain an operation instruction.
In this embodiment, the step receives configuration parameters sent by an upper computer; the configuration parameters may include various operating modes that need to be configured, for example, how many hertz chirp signals and repetition periods related signals a radio frequency end needs to transmit through the SPI interface, and the configuration required for acquisition includes: the acquisition needs to acquire the number of frame data, and the number of points of one frame data needs to be sampled by an ADC; then analyzing the acquired configuration parameters to obtain corresponding operation instructions; the user can flexibly modify and configure various parameters through the upper computer, so that the data acquisition and transmission system can be flexibly controlled.
And step S200, controlling the ADC module to collect data through the state machine at the PL terminal based on the operation instruction, and writing the collected data into a memory.
In this embodiment, in this step, based on the obtained operation instruction, the state machine at the PL side controls the ADC module to perform data acquisition and writes the acquired data into the memory; the state machine of the PL end is compiled by verilog language, and the ADC module is controlled by the state machine to collect data, so that the efficiency of data collection and transmission is well improved.
And step S300, reading data from the memory and transmitting the data to the upper computer.
In this embodiment, in this step, the result waveform is calculated through the autocorrelation matrix, and the constant modulus constraint and the sparse frequency constraint are combined in the process of calculating the result waveform, so that the result waveform is obtained finally, the condition of mutual interference between waveforms can be well reduced, and the detection effect is improved.
Referring to fig. 2, in step S100, the following steps may be included, but not limited to:
step S110, receiving the configuration parameters sent by the upper computer through the CPU at the PS end.
In this embodiment, in this step, the CPU at the PS end in the ZYNQ acquisition board receives configuration parameters sent from the upper computer; and the upper computer sends the configuration parameters to a ZYNQ acquisition board in a serial port mode.
And step S120, analyzing the configuration parameters through the CPU at the PS end to obtain an operation instruction.
In this embodiment, the CPU at the PS end in this step can analyze and process the configuration parameters, so as to convert the configuration parameters sent by the upper computer into corresponding operation instructions.
Referring to fig. 3, in step S200, the following steps may be included, but not limited to:
in step S210, the CPU on the PS side sends an operation instruction to the soft processor on the PL side.
In this embodiment, the CPU at the PS end in this step sends the analyzed operation instruction to the soft-core processor at the PL end, so as to control the soft-core processor to complete a corresponding operation.
Step S220, starting the state machine of the PL end through the soft processor of the PL end.
In this embodiment, the soft processor at the PL end of this step starts a pre-programmed state machine, and prepares for the running of the state machine.
And step S230, controlling the ADC module to collect data through the state machine at the PL end.
In this embodiment, the state machine in this step controls the ADC module to perform data acquisition, so that the efficiency of data acquisition and transmission is well improved.
Step S240, writing the acquired data into a memory.
In this embodiment, the step writes the collected data into the memory, and prepares for subsequent data transmission.
Referring to fig. 4, in step S300, the following steps may be included, but not limited to:
in step S310, when the memory is full of data, a trigger signal is sent to the CPU on the PS side through the state machine on the PL side.
In this embodiment, in this step, when the data is written in the memory, the state machine sends a trigger signal to the CPU at the PS end to notify the CPU to perform read transmission of the collected data.
And step S320, triggering the CPU at the PS end to read data from the memory.
In this embodiment, in this step, after receiving the trigger signal sent by the state machine, the CPU triggers an interrupt at the PS terminal, and then the CPU reads data from the memory.
And step S330, sending the read data to an upper computer through a network port by the CPU of the PS end.
In this embodiment, in this step, the CPU reads data from the memory and triggers the network port, and sends the data to the upper computer through the UDP protocol, so that subsequent signal processing and analysis can be performed in the upper computer.
In some embodiments of the invention, the memory is a RAM memory. RAM memory is a common memory, and has a fast data storage rate.
In some embodiments of the invention, the ADC module includes two 4-channel AD9228 chips. The ADC module is formed by combining two AD9228 chips with 4 channels, so that data acquisition and transmission processing of 8 channels can be realized, and the data acquisition and transmission efficiency is well improved.
Referring to fig. 5, in some embodiments of the present invention, the state machine operates as follows: firstly, the starting state machine is in an idle state Sz and waits for a starting instruction sent by the upper computer all the time, and if the instruction of the upper computer comes, the idle state jumps to an Sza state. The number of frames needed at this time is judged in this state, if the number of frames is less than the condition of collecting the number of frames at this time, the next state is jumped to S0, otherwise, the idle state Sz is jumped to, after the state of S0 is entered, at this time, the state waits for the feedback pulse sent back by the radio frequency front end, if the pulse is received, the judgment is made again by S0, if the number of the collected chirp satisfies the number that needs to be stored for one frame, the next judgment is jumped to, at this time, if the number of the skipped chirp satisfies the number of frames, the state of Sza frame is jumped to, otherwise, the state of S0 is jumped to, and the chirp that a frame needs to be skipped is continuously judged. If the number of the chirp stored in a frame is not satisfied at first, the state is switched to S0a, and further, whether a section of stably collected waste number of the chirp needs to be discarded is judged, if so, the state is switched to S1, and frame header coding is performed. And after the data is completely written, the next state S2 is entered, the state writes the acquired data into the RAM, when the RAM is fully written, a trigger signal is given to the RAM, the interruption of the PS end is triggered, the CPU calls the data written into the RAM by the state machine into the memory, the network port is triggered, and the data is uploaded through a UDP protocol.
Referring to fig. 6, in some embodiments of the invention, the ADC chip is combined using two AD9228 with 4-way channels, and the input of the analog signal is connected to the rf front-end through the SAMTEC using 60 pins. The clock for ADC is provided by the clock in FPG A via programmable I/O output, and the ADC chip returns two clocks, namely data output clock (DCO) and data frame output clock (FCO). When receiving the LVDS serial signals output by the ADC, the FPGA needs to consider the phase difference between the DCO edge and the data edge, and only sets reasonable time sequence constraint so as to meet the establishment time and the holding time and eliminate the metastable state. Meanwhile, the DCO and the FCO are required to determine a phase relationship, because the data collected by the DCO is only a series of bit streams although the data is correct, the highest bit or the lowest bit of the data cannot be determined, and the data can be recovered only by performing bit sequence adjustment through the FCO. The data is substantially synchronized to the phase of the FCO, with the rising edge of the FCO aligned with the most significant bits of the data. The double-port BRAM is used for performing ping-pong operation, so that data reading is accelerated, and synchronous processing is performed on data in different clock domains.
According to the scheme, the ZYNQ chip firstly receives the configuration parameters sent by the upper computer, and then analyzes the configuration parameters to obtain corresponding operation instructions; then controlling an ADC module to carry out data acquisition processing through a state machine at the PL end according to the obtained operation instruction, and writing the acquired data into a memory; then reading data from the memory and transmitting the data to the upper computer; the PL end is an FPGA which is composed of programmable logic units, and the FPGA adopts parallel processing, so that the data acquisition and transmission efficiency can be greatly improved, the data transmission is more stable, the real-time performance is better, and the data is not easy to lose.
Example two
Referring to fig. 7, a second embodiment of the present invention provides a data acquisition and transmission device 1000 based on ZYNQ, including: the processing unit 1100 is configured to receive and analyze the configuration parameters sent by the upper computer to obtain an operation instruction; the acquisition and storage unit 1200 is used for controlling the ADC module to acquire data through a state machine at the PL end based on the operation instruction and writing the acquired data into a memory;
and a reading and sending unit 1300, configured to read data from the memory and transmit the data to the upper computer.
In some embodiments of the invention, the processing unit 1100 comprises:
a receiving unit 1110, configured to receive, through a CPU at a PS end, configuration parameters sent by an upper computer;
the parsing unit 1120 is configured to parse the configuration parameter through the CPU at the PS end to obtain an operation instruction.
It should be noted that, since the data acquisition and transmission device based on ZYNQ in the present embodiment is based on the same inventive concept as the data acquisition and transmission method based on ZYNQ in the first embodiment, the corresponding content in the first method embodiment is also applicable to the embodiment of the present system, and will not be described in detail here.
According to the scheme, the ZYNQ chip firstly receives the configuration parameters sent by the upper computer, and then analyzes the configuration parameters to obtain corresponding operation instructions; then controlling an ADC module to carry out data acquisition processing through a state machine at the PL end according to the obtained operation instruction, and writing the acquired data into a memory; then reading data from the memory and transmitting the data to the upper computer; the PL end is an FPGA which is composed of programmable logic units, and the FPGA adopts parallel processing, so that the data acquisition and transmission efficiency can be greatly improved, the data transmission is more stable, the real-time performance is better, and the data is not easy to lose.
EXAMPLE III
Referring to fig. 8, a third embodiment of the present invention provides a ZYNQ-based data acquisition and transmission apparatus 400, which includes at least one control processor 401 and a memory 402 for communication connection with the at least one control processor 401; the memory 402 stores instructions executable by the at least one control processor 401, and the instructions are executed by the at least one control processor 401 to enable the at least one control processor 401 to execute the ZYNQ-based data collection and transmission method according to the first embodiment.
Example four
The fourth embodiment of the present invention further provides a computer-readable storage medium, where the computer-readable storage medium stores executable instructions of a data acquisition and transmission device based on ZYNQ, where the executable instructions of the data acquisition and transmission device based on ZYNQ are used to enable the data acquisition and transmission device based on ZYNQ to perform the data acquisition and transmission method based on ZYNQ, for example, to perform the above-described method steps S100 to S300 in fig. 1, so as to implement the function of the unit 1000 and 1300 in fig. 7.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
Claims (10)
1. A data acquisition and transmission method based on ZYNQ is characterized by comprising the following steps:
receiving and analyzing configuration parameters sent by an upper computer to obtain an operation instruction;
controlling an ADC module to collect data through a state machine at the PL end based on the operation instruction and writing the collected data into a memory;
and reading data from the memory and transmitting the data to the upper computer.
2. The ZYNQ-based data acquisition and transmission method as claimed in claim 1,
the receiving and analyzing of the configuration parameters sent by the upper computer to obtain the operation instruction comprises:
receiving configuration parameters sent by an upper computer through a CPU at a PS end;
and analyzing the configuration parameters through a CPU at the PS end to obtain an operation instruction.
3. The ZYNQ-based data acquisition and transmission method as claimed in claim 2,
the controlling, by the state machine of the PL end, the ADC module to collect data and write the collected data into the memory based on the operation instruction includes:
sending the operation instruction to a soft processor of a PL (packet data) end through a CPU (central processing unit) of the PS end;
starting a state machine of the PL end through a soft processor of the PL end;
controlling an ADC module to collect data through a state machine at a PL end;
and writing the collected data into a memory.
4. The ZYNQ-based data acquisition and transmission method as claimed in claim 3,
the reading data from the memory and transmitting the data to the upper computer comprises:
when the data is written in the memory, a state machine at the PL end sends a trigger signal to a CPU at the PS end;
triggering a CPU at the PS end to read data from the memory;
and the read data is sent to the upper computer through the network port by the CPU at the PS end.
5. The ZYNQ-based data acquisition and transmission method according to claim 1, wherein:
the memory is a RAM memory.
6. The ZYNQ-based data acquisition and transmission method according to claim 1, wherein:
the ADC module comprises two AD9228 chips with 4 channels.
7. A data acquisition transmission device based on ZYNQ, characterized by comprising:
the processing unit is used for receiving and analyzing the configuration parameters sent by the upper computer to obtain an operation instruction;
the acquisition storage unit is used for controlling the ADC module to acquire data through a state machine at the PL terminal based on the operation instruction and writing the acquired data into a memory;
and the reading and sending unit is used for reading data from the memory and transmitting the data to the upper computer.
8. The ZYNQ-based data acquisition and transmission device as claimed in claim 7,
the processing unit includes:
the receiving unit is used for receiving the configuration parameters sent by the upper computer through the CPU at the PS end;
and the analysis unit is used for analyzing the configuration parameters through the CPU at the PS end to obtain an operation instruction.
9. The utility model provides a data acquisition transmission equipment based on ZYNQ which characterized in that: comprises at least one control processor and a memory for communicative connection with the at least one control processor; the memory stores instructions executable by the at least one control processor to enable the at least one control processor to perform the ZYNQ-based data acquisition transmission method of any one of claims 1 to 6.
10. A computer-readable storage medium characterized by: the computer readable storage medium having stored thereon ZYNQ-based data acquisition transmission device executable instructions for causing a ZYNQ-based data acquisition transmission device to perform the ZYNQ-based data acquisition transmission method of any of claims 1 to 6.
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| WO2024000117A1 (en) * | 2022-06-27 | 2024-01-04 | 西门子股份公司 | Edge computing device and method, and internet of things system |
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