CN115622958B - ZYNQ system and virtual MAC implementation method - Google Patents
ZYNQ system and virtual MAC implementation method Download PDFInfo
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- CN115622958B CN115622958B CN202211261363.1A CN202211261363A CN115622958B CN 115622958 B CN115622958 B CN 115622958B CN 202211261363 A CN202211261363 A CN 202211261363A CN 115622958 B CN115622958 B CN 115622958B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/109—Integrated on microchip, e.g. switch-on-chip
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L61/00—Network arrangements, protocols or services for addressing or naming
- H04L61/09—Mapping addresses
- H04L61/25—Mapping addresses of the same type
- H04L61/2503—Translation of Internet protocol [IP] addresses
- H04L61/2557—Translation policies or rules
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to the field of network communication, and particularly discloses a ZYNQ system and a virtual MAC (media access control) implementation method, wherein the ZYNQ system comprises an FPGA (field programmable gate array) chip, an ARM (advanced RISC machine) processor, a DDR (double data Rate) memory and a plurality of PHY (physical layer) transceivers; the PHY transceivers are used for sending and receiving data packets and interacting with the FPGA chip; the DDR memory is provided with a read cache area and a write cache area; the ARM processor comprises a virtual MAC module and a kernel protocol stack, when receiving a data packet, the virtual MAC module reads information records of the FPGA chip, copies the data packet from a read cache area of the DDR memory and sends the data packet to the kernel protocol stack; when a data packet is sent, the kernel protocol stack actively transmits the data packet, and the virtual MAC module copies the data packet to a write cache area in the DDR storage area and writes the information of the data packet into the FPGA chip; the invention can realize high-efficiency and stable MAC processing link in a low-cost mode through the cooperation of the FPGA chip and the ARM processor, and has high portability and strong maintainability of the whole system.
Description
Technical Field
The invention relates to the field of network communication, in particular to a ZYNQ system and a virtual MAC implementation method.
Background
In the broadcast television front-end equipment, gigabit ethernet is often used as a transmission stream interaction mode of the whole system, and a single equipment is at least provided with a management port and a data port, but with the continuous progress of technology and the continuous improvement of customer requirements, the bandwidth of the data port of the equipment is increased, so that a mode is needed to increase the transmission bandwidth of the equipment.
In the existing mode, the network port is updated to be the tera Ethernet, but the network port needs to be supported by clients, the equipment cost is increased, and the limitation is larger.
The second existing mode is to add one or even more gigabit ports for data transmission. However, the general processing chip only has two hard core MACs, namely only can be externally connected with two PHY chips, if more PHYs are needed to be accessed, expensive fees are paid to purchase a third party MAC driving module, the development cost is greatly increased, the purchased driving module has a single function, the bottom layer code cannot be modified according to the use scene, and the post maintenance is not facilitated.
Disclosure of Invention
Aiming at the problems of high development cost, large limitation and unfavorable post maintenance, the invention provides a ZYNQ system and a virtual MAC realization method, which can realize a high-efficiency and stable MAC processing link in a low-cost mode through the cooperation of an FPGA chip and an ARM processor, and the whole system has high portability and strong maintainability.
In order to solve the technical problems, the invention provides the following specific scheme:
the embodiment of the application provides a ZYNQ system, which comprises an FPGA chip, an ARM processor, a DDR memory and a plurality of PHY transceivers;
the PHY transceivers are used for sending and receiving data packets and interacting with the FPGA chip;
the DDR memory is provided with a read cache area and a write cache area;
the FPGA chip caches and records the received data packets, writes the data packets into a read cache area of the DDR memory, reads the data packets from the write cache area on the DDR memory and sends the data packets to the PHY transceiver;
the ARM processor comprises a virtual MAC module and a kernel protocol stack, when receiving a data packet, the virtual MAC module reads information records of the FPGA chip, copies the data packet from a read cache area of the DDR memory and sends the data packet to the kernel protocol stack; when a data packet is sent, the kernel protocol stack actively transmits the data packet, and the virtual MAC module copies the data packet to a write cache area in the DDR storage area and writes information of the data packet into the FPGA chip.
In some embodiments, the DDR memory is programmed with a read cache area and a write cache area, comprising:
the DDR memory is provided with a read cache area and a write cache area of each PHY receiver according to the number of the PHY receivers, the read cache area and the write cache area of each PHY receiver cannot be crossed, and the areas between the PHY receivers cannot be crossed, so that the accuracy of reading data packets and writing data packets is ensured.
In some embodiments, the FPGA chip includes an RX receive, a TX transmit, and a register;
the RX receiving end is used for caching the received data packet in an internal data RAM and recording the information of the data packet in the internal information RAM;
the TX transmitting end is configured to record information of a data packet to be transmitted in an internal information RAM, and buffer the data packet to be transmitted in the internal data RAM;
the register is used for temporarily storing information of the information RAM in the RX receiving end and the information of the information RAM in the TX sending end, so that the virtual MAC module can copy the data packet from the corresponding read cache area on the DDR memory according to the information RAM in the RX receiving end, and the FPGA chip can conveniently read the data packet from the corresponding write cache area on the DDR memory according to the information RAM in the TX receiving end.
In some embodiments, the virtual MAC module reads the information record of the FPGA chip when receiving the data packet, copies the data packet from the read buffer area of the DDR memory, and sends the data packet to the kernel protocol stack, and includes:
when receiving the data packet, the virtual MAC module reads information of the information RAM in the RX receiving end through the register, copies the data packet from the read cache area of the DDR memory and sends the data packet to the kernel protocol stack.
In some embodiments, when sending the data packet, the kernel protocol stack actively issues the data packet, the virtual MAC module copies the data packet to a write buffer area in the DDR memory area, and writes information of the data packet to the FPGA chip, including:
when the data packet is sent, the kernel protocol stack actively sends the data packet, the virtual MAC module copies the data packet to a write cache area in the DDR storage area, and the information of the data packet is written into an information RAM in the TX sending end of the FPGA chip through a register.
The embodiment of the application also provides a virtual MAC implementation method, which is applied to the ZYNQ system described in any one of the above, and comprises the following steps:
initializing a virtual MAC module;
receiving the data packet by the virtual MAC module;
and the virtual MAC module transmits the data packet.
In some embodiments, the initializing of the virtual MAC module comprises:
the virtual MAC module interacts with the FPGA chip through an AXI_CPU bus;
the virtual MAC module analyzes the equipment tree, maps the AXI_CPU bus address to the virtual address space of the kernel through the kernel function, and returns a corresponding virtual address;
the DDR memory address is mapped to the virtual address space of the kernel through the kernel function, and the corresponding virtual address is returned.
In some embodiments, the receiving of the data packet by the virtual MAC module includes:
the FPGA chip triggers a hard interrupt to wake up the virtual MAC module, the virtual MAC module reads information records of the FPGA chip, copies data packets from a read cache area of the DDR memory and sends the data packets to a kernel protocol stack.
In some embodiments, the FPGA chip triggers a hard interrupt to wake up a virtual MAC module, the virtual MAC module reads information records of the FPGA chip, copies data packets from a read cache area of the DDR memory, and sends the data packets to a kernel protocol stack, including:
the FPGA chip triggers the hard interrupt to wake up the virtual MAC module, the virtual MAC module reads information record of the FPGA chip, copies the data packet from a read cache area of the DDR memory, performs CRC check on the current data packet, discards and records the current data packet if the data is abnormal, packages the data packet into a socket buffer format if the data is normal, and sends the data packet to a kernel protocol stack.
In some embodiments, the sending of the data packet by the virtual MAC module includes:
the kernel protocol stack actively transmits the data packet, and the virtual MAC module copies the data packet to a write cache area in the DDR storage area and writes the information of the data packet into the FPGA chip.
Compared with the prior art, the invention has the beneficial effects that: the ZYNQ system comprises an FPGA chip, an ARM processor, a DDR memory and a plurality of PHY transceivers, wherein the ARM processor comprises a virtual MAC module and a kernel protocol stack, and an efficient and stable MAC processing link is realized in a low-cost mode through cooperation of the FPGA chip and the ARM processor, so that the portability of the whole system is high, and the maintainability is strong.
Drawings
FIG. 1 is a schematic diagram of a ZYNQ system provided in an embodiment of the present invention;
fig. 2 is a flowchart of initializing a virtual MAC module according to an embodiment of the present invention;
fig. 3 is a flowchart of a receiving a data packet by a virtual MAC module according to an embodiment of the present invention;
fig. 4 is a flowchart of a transmission of a data packet by a virtual MAC module according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. The described embodiments are some, but not all, embodiments of the invention.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, based on the embodiments of the invention, which are apparent to those of ordinary skill in the art without inventive faculty, are intended to be within the scope of the invention.
For example, a ZYNQ system comprising an FPGA chip, an ARM processor, a DDR memory, and a plurality of PHY transceivers; the PHY transceivers are used for sending and receiving data packets and interacting with the FPGA chip; the DDR memory is provided with a read cache area and a write cache area; the FPGA chip caches and records the received data packets, writes the data packets into a read cache area of the DDR memory, reads the data packets from the write cache area on the DDR memory and sends the data packets to the PHY transceiver; the ARM processor comprises a virtual MAC module and a kernel protocol stack, when receiving a data packet, the virtual MAC module reads information records of the FPGA chip, copies the data packet from a read cache area of the DDR memory and sends the data packet to the kernel protocol stack; when a data packet is sent, the kernel protocol stack actively transmits the data packet, and the virtual MAC module copies the data packet to a write cache area in the DDR storage area and writes information of the data packet into the FPGA chip.
According to the ZYNQ system and the virtual MAC implementation method, the ZYNQ system comprises an FPGA chip, an ARM processor, a DDR memory and a plurality of PHY transceivers, the ARM processor comprises a virtual MAC module and a kernel protocol stack, and an efficient and stable MAC processing link is realized in a low-cost mode through cooperation of the FPGA chip and the ARM processor, so that the portability of the whole system is high, and the maintainability is strong.
Embodiment one:
referring to FIG. 1, FIG. 1 shows a schematic diagram of a ZYNQ system in an embodiment of the present application.
A ZYNQ system comprises an FPGA chip, an ARM processor, a DDR memory and a plurality of PHY transceivers.
The FPGA chip belongs to a semi-custom circuit in an application-specific integrated circuit, is a programmable logic array, can effectively solve the problem of fewer original device gates, and has a basic structure comprising a programmable input/output unit, a configurable logic block, a digital clock management module, an embedded RAM, wiring resources, an embedded special hard core and an embedded functional unit in a bottom layer.
The ARM processor can use a large number of registers, the instruction execution speed is higher, most data operations are completed in the registers, and the ARM processor has the characteristics of flexible and simple addressing mode, high execution efficiency and the like.
The DDR memory is a memory space which can be directly addressed by a CPU and is made of a semiconductor device, and is characterized in that the data access speed is high, data are transmitted twice in one clock period, data can be transmitted once in the rising period and the falling period of the clock respectively, and the DDR memory has higher data transmission rate.
The PHY transceiver is configured to implement an ethernet physical layer function, and may transmit and receive ethernet packets.
In this example, the plurality of PHY transceivers are used to send and receive data packets and interact with the FPGA chip, for example, to send ethernet data packets to the FPGA chip or to receive ethernet data packets from the FPGA chip, and the use of the plurality of PHY transceivers can increase the transmission bandwidth of the device, so as to meet the use requirements of customers.
The DDR memory is provided with a read cache area and a write cache area, so that the FPGA chip can conveniently write the received data packet into the read cache area, and the virtual MAC module can conveniently copy the data packet into the write cache area.
And the FPGA chip is used for caching and recording information of the received data packet, writing the data packet into a read cache area of the DDR memory, reading the data packet from the write cache area on the DDR memory and sending the data packet to the PHY transceiver.
When the FPGA chip detects that a data packet is input, the data packet is cached, information of the data packet is recorded after analysis, the data packet is written into a read cache area of the designated DDR memory through a DMA channel, and hard interrupt is triggered.
The ARM processor comprises a virtual MAC module and a kernel protocol stack, when receiving the data packet, the virtual MAC module reads the information record of the FPGA chip, copies the data packet from the read cache area of the DDR memory and sends the data packet to the kernel protocol stack; when a data packet is sent, the kernel protocol stack actively transmits the data packet, and the virtual MAC module copies the data packet to a write cache area in the DDR storage area and writes information of the data packet into the FPGA chip.
The virtual MAC module is in an idle state normally, after being awakened by the hard interrupt, the virtual MAC module triggers interrupt service, and then reads information records of the FPGA chip, such as the recorded packet length and packet number, so as to obtain the current packet number, if the packet number is not 0, the virtual MAC module copies data packets from a read cache area appointed by the DDR memory according to the packet length and sends the data packets to a kernel protocol stack. When the kernel protocol stack actively issues the data packet, when the data packet arrives, the kernel protocol stack only processes one data packet at a time, so that the data packet is firstly received after the sending queue is suspended, then the data packet is copied to a write cache area appointed by the DDR memory, and information of the data packet is written into the FPGA chip, for example, the packet length and the cheap address of the data packet are written into the FPGA chip.
According to the ZYNQ system provided by the example, a virtual MAC module is utilized, a data packet received by an FPGA chip is written into a read cache area of a DDR memory through cooperation of the FPGA chip and an ARM processor, the ARM processor can copy the data packet from the read cache area of the DDR memory to a kernel protocol stack only by reading information records of the FPGA chip through the virtual MAC module, and the DDR memory only needs to be in charge of storing the data packet; when a data packet needs to be sent to a PHY transceiver, a kernel protocol stack of an ARM processor actively transmits the data packet, a virtual MAC module copies the data packet to a write cache area in a DDR memory and writes information of the data packet into an FPGA chip, the FPGA chip reads a corresponding data packet from the write cache area on the DDR memory according to the information of the data packet written by the virtual MAC module and sends the corresponding data packet to the PHY transceiver, the traditional mode that the data packet information of the DDR memory needs to be read first and the data packet in the DDR memory can be read continuously according to the data packet information is replaced, the problem of complicated processing flow is solved, the copying of the DDR memory is not required to be involved twice, the efficiency is effectively improved, an efficient and stable MAC processing link is realized in a low-cost mode, and the whole system is high in portability and strong in maintainability.
Embodiment two:
DDR memory, planned with read buffer area and write buffer area, includes:
the DDR memory is provided with a read cache area and a write cache area of each PHY receiver according to the number of the PHY receivers, the read cache area and the write cache area of each PHY receiver cannot be crossed, and the areas between the PHY receivers cannot be crossed, so that the accuracy of reading data packets and writing data packets is ensured.
Referring to fig. 1, a plurality of PHY receivers are shown together, each PHY receiver interacts with the FPGA chip, and the DDR memory is configured with a read buffer area and a write buffer area corresponding to the number of each PHY receiver according to the number of PHY receivers, so that the FPGA chip writes the received data packet of each PHY receiver into the read buffer area corresponding to the DDR memory, and the virtual MAC module copies the data packet into the write buffer area specified by the DDR memory.
In this example, the FPGA chip includes an RX receiver, a TX transmitter, and registers; the RX receiving end is used for caching the received data packet in an internal data RAM and recording the information of the data packet in the internal information RAM; the TX transmitting end is used for recording the information of the data packet to be transmitted in an internal information RAM and caching the data packet to be transmitted in the internal data RAM; the register is used for temporarily storing information of the information RAM in the RX receiving end and the information of the information RAM in the TX sending end, so that the virtual MAC module can copy the data packet from the corresponding read cache area on the DDR memory according to the information RAM in the RX receiving end, and the FPGA chip can conveniently read the data packet from the corresponding write cache area on the DDR memory according to the information RAM in the TX receiving end.
For example, when receiving a data packet, the virtual MAC module reads an information record of the FPGA chip, copies the data packet from a read buffer area of the DDR memory, and sends the data packet to the kernel protocol stack.
When a data packet is sent, the kernel protocol stack actively sends the data packet, the virtual MAC module copies the data packet to a write cache area in the DDR storage area, and writes information of the data packet into the FPGA chip, specifically, when the data packet is sent, the kernel protocol stack actively sends the data packet, the virtual MAC module copies the data packet to the write cache area in the DDR storage area, and writes information of the data packet into an information RAM in a TX sending end of the FPGA chip through a register.
It should be noted that, when receiving a data packet, the virtual MAC module reads information of the information RAM in the RX receiving end through the register, where the information may be a packet length and a packet number of the data packet recorded in the information RAM in the RX receiving end, so that the virtual MAC module copies the data packet from a corresponding read buffer area of the DDR memory. When a data packet is sent, the kernel protocol stack actively sends the data packet, the virtual MAC module copies the data packet to a write cache area in the DDR storage area, and writes information of the data packet into an information RAM in a TX sending end of the FPGA chip through a register, wherein the information can be a packet length and an offset address of the data packet, so that the FPGA chip can read the data packet from a corresponding write cache area on the DDR storage according to the packet length and the offset address and send the data packet to the PHY transceiver.
Embodiment III:
the embodiment of the application also provides a virtual MAC implementation method, which is applied to the ZYNQ system in the embodiment, and comprises the following steps: initializing a virtual MAC module, receiving a data packet by the virtual MAC module and transmitting the data packet by the virtual MAC module.
Referring to fig. 2, the initialization of the virtual MAC module includes:
the virtual MAC module interacts with the FPGA chip through an AXI_CPU bus; the virtual MAC module analyzes the equipment tree, maps the AXI_CPU bus address to the virtual address space of the kernel through the kernel function, and returns a corresponding virtual address; the DDR memory address is mapped to the virtual address space of the kernel through the kernel function, and the corresponding virtual address is returned.
Specifically, the virtual MAC module is finally compiled into a ko driving file, all parameters to be customized according to different projects are defined on a device tree, the virtual MAC module firstly analyzes the device tree, then maps the axi_cpu bus address to the virtual address space of the kernel through the kernel function ioremap, the function returns a virtual address after mapping is successful, and reading and writing the virtual address on software is equivalent to operating as the axi_cpu bus to read and write a register of the FPGA chip. Similarly, the DDR memory address is mapped onto the virtual address space of the kernel through the kernel function ioremap, the function returns a virtual address after mapping is successful, and software can read and write the DDR memory. Registering network device drivers with the kernel according to the current number of PHY transceivers, and binding and registering hard interrupts and service functions thereof for each network device driver. In order to use NAPI soft interruption later, the NAPI is related to the network equipment in advance, and finally the network equipment sending queue is activated for the data interaction between the kernel protocol stack and the network equipment drive. After these actions are completed, the program enters a CPU background idle state waiting to be awakened by a hard interrupt.
Referring to fig. 3, the receiving of the data packet by the virtual MAC module includes:
the FPGA chip triggers a hard interrupt to wake up the virtual MAC module, the virtual MAC module reads information records of the FPGA chip, copies data packets from a read cache area of the DDR memory and sends the data packets to a kernel protocol stack.
After the virtual MAC module copies the data packet from the read cache area of the DDR memory, CRC check is carried out on the current data packet, if the data is abnormal, the data packet is discarded and recorded, and if the data is normal, the data packet is packaged into a socket buffer format and sent to a kernel protocol stack. The socket buffer is an important data structure in the Linux kernel network module and is used for managing and controlling information of receiving or sending data packets.
Specifically, the PHY transceiver receives a network data packet, the FPGA chip processes the data packet (protocol conversion and packet filtering, which are not described in detail herein), writes the processed data packet into a read buffer area of the designated DDR memory, records packet length information of the received data packet and an offset address of the buffer location in an information RAM of the RX receiving end, and triggers a hard interrupt to wake up the virtual MAC module. After the virtual MAC module responds to the interrupt, the ARM processor reads the packet length and the offset address in the information RAM of the RX receiving end through the register, and then reads the corresponding data packet from the DDR memory. In the interrupt service function, the processing returns are ended after only suspending the hard interrupt trigger and starting the NAPI soft interrupt. This is because the large amount of network data frequently triggers hard interrupts, and by minimizing the hard interrupt processing time, it is possible to avoid the CPU from getting involved in hard interrupts and having no time to process other traffic. The NAPI soft interrupt mainly detects the number of packets in a cycle within a preset time and processes data, and comprises the steps of reading the packets from the DDR memory, packaging the packets into a specified format, sending the packets to a kernel protocol stack, exiting the soft interrupt when the time is used up or when no cache data exists currently, and restarting the hard interrupt.
Referring to fig. 4, the transmission of a packet by a virtual MAC module includes:
the kernel protocol stack actively transmits the data packet, and the virtual MAC module copies the data packet to a write cache area in the DDR storage area and writes the information of the data packet into the FPGA chip.
Specifically, when a data packet arrives, the kernel protocol stack actively issues the data packet, and only one data packet is processed at a time, so that the data packet is firstly received after a transmission queue is suspended, then the data packet is copied to a designated write buffer area of the DDR memory, the packet length and the offset address are written into an information RAM of a TX receiving end of the FPGA chip through a register, the FPGA chip always judges whether the information RAM of the TX receiving end has data, if the information RAM of the TX receiving end has data, packet information is read from the information RAM of the TX receiving end, then the data packet is read from the DDR memory according to the information, and then the data packet is transmitted to the PHY transceiver, and actual output is completed.
In summary, according to the ZYNQ system and the virtual MAC implementation method provided by the invention, the virtual MAC module is utilized, the data packet received by the FPGA chip is written into the read cache area of the DDR memory through cooperation of the FPGA chip and the ARM processor, the ARM processor can copy the data packet from the read cache area of the DDR memory to the kernel protocol stack only by reading the information record of the FPGA chip through the virtual MAC module, and the DDR memory only needs to be responsible for storing the data packet; when a data packet needs to be sent to a PHY transceiver, a kernel protocol stack of an ARM processor actively transmits the data packet, a virtual MAC module copies the data packet to a write cache area in a DDR memory and writes information of the data packet into an FPGA chip, the FPGA chip reads a corresponding data packet from the write cache area on the DDR memory according to the information of the data packet written by the virtual MAC module and sends the corresponding data packet to the PHY transceiver, the traditional mode that the data packet information of the DDR memory needs to be read first and the data packet in the DDR memory can be read continuously according to the data packet information is replaced, the problem of complicated processing flow is solved, the copying of the DDR memory is not required to be involved twice, the efficiency is effectively improved, an efficient and stable MAC processing link is realized in a low-cost mode, and the whole system is high in portability and strong in maintainability.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples illustrate only a few embodiments of the invention and are described in detail herein without thereby limiting the scope of the invention. It should be noted that it is possible for a person skilled in the art to make several variants and modifications without departing from the inventive concept, which fall within the scope of protection of the present invention, which is therefore subject to the appended claims.
Claims (10)
1. The ZYNQ system is characterized by comprising an FPGA chip, an ARM processor, a DDR memory and a plurality of PHY transceivers;
the PHY transceivers are used for sending and receiving data packets and interacting with the FPGA chip;
the DDR memory is provided with a read cache area and a write cache area;
the FPGA chip caches and records the received data packets, writes the data packets into a read cache area of the DDR memory, reads the data packets from the write cache area on the DDR memory and sends the data packets to the PHY transceiver;
the ARM processor comprises a virtual MAC module and a kernel protocol stack, when receiving a data packet, the virtual MAC module reads information records of the FPGA chip, copies the data packet from a read cache area of the DDR memory and sends the data packet to the kernel protocol stack; when a data packet is sent, the kernel protocol stack actively transmits the data packet, and the virtual MAC module copies the data packet to a write cache area in the DDR storage area and writes information of the data packet into the FPGA chip.
2. The ZYNQ system of claim 1, wherein the DDR memory is programmed with a read cache area and a write cache area, comprising:
the DDR memory is provided with a read cache area and a write cache area of each PHY receiver according to the number of the PHY receivers.
3. The ZYNQ system of claim 1 wherein the FPGA chip comprises an RX receive, a TX transmit, and a register;
the RX receiving end is used for caching the received data packet in an internal data RAM and recording the information of the data packet in the internal information RAM;
the TX transmitting end is configured to record information of a data packet to be transmitted in an internal information RAM, and buffer the data packet to be transmitted in the internal data RAM;
the register is used for temporarily storing information of the information RAM in the RX receiving end and the information of the information RAM in the TX transmitting end.
4. The ZYNQ system of claim 3 wherein the virtual MAC module reads information records of the FPGA chip, copies data packets from the read cache area of the DDR memory and sends the data packets to the kernel protocol stack upon receipt of the data packets, comprising:
when receiving the data packet, the virtual MAC module reads information of the information RAM in the RX receiving end through the register, copies the data packet from the read cache area of the DDR memory and sends the data packet to the kernel protocol stack.
5. The ZYNQ system of claim 3 wherein the kernel protocol stack actively issues the data packet when sending the data packet, the virtual MAC module copies the data packet to a write buffer area in the DDR memory area, and writes information of the data packet to the FPGA chip, comprising:
when the data packet is sent, the kernel protocol stack actively sends the data packet, the virtual MAC module copies the data packet to a write cache area in the DDR storage area, and the information of the data packet is written into an information RAM in the TX sending end of the FPGA chip through a register.
6. A virtual MAC implementation method, applied to the ZYNQ system of any one of claims 1-5, the method comprising:
initializing a virtual MAC module;
receiving the data packet by the virtual MAC module;
and the virtual MAC module transmits the data packet.
7. The virtual MAC implementation method of claim 6, wherein the initializing of the virtual MAC module comprises:
the virtual MAC module interacts with the FPGA chip through an AXI_CPU bus;
the virtual MAC module analyzes the equipment tree, maps the AXI_CPU bus address to the virtual address space of the kernel through the kernel function, and returns a corresponding virtual address;
the DDR memory address is mapped to the virtual address space of the kernel through the kernel function, and the corresponding virtual address is returned.
8. The method for implementing virtual MAC as claimed in claim 6, wherein the receiving of the data packet by the virtual MAC module includes:
the FPGA chip triggers a hard interrupt to wake up the virtual MAC module, the virtual MAC module reads information records of the FPGA chip, copies data packets from a read cache area of the DDR memory and sends the data packets to a kernel protocol stack.
9. The method for implementing virtual MAC according to claim 8, wherein the FPGA chip triggers a hard interrupt to wake up the virtual MAC module, the virtual MAC module reads an information record of the FPGA chip, copies a data packet from a read buffer area of the DDR memory, and sends the data packet to a kernel protocol stack, including:
the FPGA chip triggers the hard interrupt to wake up the virtual MAC module, the virtual MAC module reads information record of the FPGA chip, copies the data packet from a read cache area of the DDR memory, performs CRC check on the current data packet, discards and records the current data packet if the data is abnormal, packages the data packet into a socket buffer format if the data is normal, and sends the data packet to a kernel protocol stack.
10. The method for implementing virtual MAC as claimed in claim 6, wherein the sending of the data packet by the virtual MAC module includes:
the kernel protocol stack actively transmits the data packet, and the virtual MAC module copies the data packet to a write cache area in the DDR storage area and writes the information of the data packet into the FPGA chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211261363.1A CN115622958B (en) | 2022-10-14 | 2022-10-14 | ZYNQ system and virtual MAC implementation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113132161A (en) * | 2021-04-14 | 2021-07-16 | 五邑大学 | ZYNQ-based data acquisition and transmission method, device, equipment and storage medium |
| WO2021209051A1 (en) * | 2020-04-17 | 2021-10-21 | 深圳市中兴微电子技术有限公司 | On-chip cache device, on-chip cache read/write method, and computer readable medium |
| CN114500393A (en) * | 2021-12-31 | 2022-05-13 | 伟乐视讯科技股份有限公司 | Communication method and communication equipment for one-to-many PHY (physical layer) modules of MAC (media access control) |
| CN114780449A (en) * | 2022-04-01 | 2022-07-22 | 扬州宇安电子科技有限公司 | Data storage and transmission system based on ZYNQ chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2021209051A1 (en) * | 2020-04-17 | 2021-10-21 | 深圳市中兴微电子技术有限公司 | On-chip cache device, on-chip cache read/write method, and computer readable medium |
| CN113132161A (en) * | 2021-04-14 | 2021-07-16 | 五邑大学 | ZYNQ-based data acquisition and transmission method, device, equipment and storage medium |
| CN114500393A (en) * | 2021-12-31 | 2022-05-13 | 伟乐视讯科技股份有限公司 | Communication method and communication equipment for one-to-many PHY (physical layer) modules of MAC (media access control) |
| CN114780449A (en) * | 2022-04-01 | 2022-07-22 | 扬州宇安电子科技有限公司 | Data storage and transmission system based on ZYNQ chip |
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